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Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +01001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * @file op_model_ppro.h
Andi Kleenb9917022008-08-18 14:50:31 +02003 * Family 6 perfmon and architectural perfmon MSR operations
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 *
5 * @remark Copyright 2002 OProfile authors
Andi Kleenb9917022008-08-18 14:50:31 +02006 * @remark Copyright 2008 Intel Corporation
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 * @remark Read the file COPYING
8 *
9 * @author John Levon
10 * @author Philippe Elie
11 * @author Graydon Hoare
Andi Kleenb9917022008-08-18 14:50:31 +020012 * @author Andi Kleen
Robert Richter3370d352009-05-25 15:10:32 +020013 * @author Robert Richter <robert.richter@amd.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014 */
15
16#include <linux/oprofile.h>
Andi Kleenb9917022008-08-18 14:50:31 +020017#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <asm/ptrace.h>
19#include <asm/msr.h>
20#include <asm/apic.h>
Don Zickus3e4ff112006-06-26 13:57:01 +020021#include <asm/nmi.h>
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +010022
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#include "op_x86_model.h"
24#include "op_counter.h"
25
Andi Kleenb9917022008-08-18 14:50:31 +020026static int num_counters = 2;
27static int counter_width = 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Robert Richter3370d352009-05-25 15:10:32 +020029#define MSR_PPRO_EVENTSEL_RESERVED ((0xFFFFFFFFULL<<32)|(1ULL<<21))
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
Maarten Lankhorst1d12d352011-08-01 11:08:59 -040031static u64 reset_value[OP_MAX_COUNTER];
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +010032
Robert Richter83300ce2010-03-23 20:01:54 +010033static void ppro_shutdown(struct op_msrs const * const msrs)
34{
35 int i;
36
37 for (i = 0; i < num_counters; ++i) {
38 if (!msrs->counters[i].addr)
39 continue;
40 release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
41 release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
42 }
Robert Richter83300ce2010-03-23 20:01:54 +010043}
44
Robert Richter8617f982010-02-26 17:20:55 +010045static int ppro_fill_in_addresses(struct op_msrs * const msrs)
Linus Torvalds1da177e2005-04-16 15:20:36 -070046{
Don Zickuscb9c4482006-09-26 10:52:26 +020047 int i;
48
Andi Kleenb9917022008-08-18 14:50:31 +020049 for (i = 0; i < num_counters; i++) {
Robert Richterd0e41202010-03-23 19:33:21 +010050 if (!reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
Robert Richter8617f982010-02-26 17:20:55 +010051 goto fail;
Robert Richterd0e41202010-03-23 19:33:21 +010052 if (!reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i)) {
53 release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
Robert Richter8617f982010-02-26 17:20:55 +010054 goto fail;
Robert Richterd0e41202010-03-23 19:33:21 +010055 }
56 /* both registers must be reserved */
57 msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
58 msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
Robert Richter8617f982010-02-26 17:20:55 +010059 continue;
60 fail:
61 if (!counter_config[i].enabled)
62 continue;
63 op_x86_warn_reserved(i);
64 ppro_shutdown(msrs);
65 return -EBUSY;
Don Zickuscb9c4482006-09-26 10:52:26 +020066 }
Robert Richter8617f982010-02-26 17:20:55 +010067
68 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070069}
70
71
Robert Richteref8828d2009-05-25 19:31:44 +020072static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
73 struct op_msrs const * const msrs)
Linus Torvalds1da177e2005-04-16 15:20:36 -070074{
Robert Richter3370d352009-05-25 15:10:32 +020075 u64 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 int i;
77
Andi Kleenb9917022008-08-18 14:50:31 +020078 if (cpu_has_arch_perfmon) {
79 union cpuid10_eax eax;
80 eax.full = cpuid_eax(0xa);
Tim Blechmann780eef92009-02-19 17:34:03 +010081
82 /*
83 * For Core2 (family 6, model 15), don't reset the
84 * counter width:
85 */
86 if (!(eax.split.version_id == 0 &&
Tejun Heo7b543a52010-12-18 16:30:05 +010087 __this_cpu_read(cpu_info.x86) == 6 &&
88 __this_cpu_read(cpu_info.x86_model) == 15)) {
Tim Blechmann780eef92009-02-19 17:34:03 +010089
90 if (counter_width < eax.split.bit_width)
91 counter_width = eax.split.bit_width;
92 }
Andi Kleenb9917022008-08-18 14:50:31 +020093 }
94
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 /* clear all counters */
Robert Richter6e63ea42009-07-07 19:25:39 +020096 for (i = 0; i < num_counters; ++i) {
Robert Richter8617f982010-02-26 17:20:55 +010097 if (!msrs->controls[i].addr)
Don Zickuscb9c4482006-09-26 10:52:26 +020098 continue;
Robert Richter3370d352009-05-25 15:10:32 +020099 rdmsrl(msrs->controls[i].addr, val);
Robert Richterbb1165d2010-03-01 14:21:23 +0100100 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
Robert Richter98a2e732010-02-23 18:14:58 +0100101 op_x86_warn_in_use(i);
Robert Richter3370d352009-05-25 15:10:32 +0200102 val &= model->reserved;
103 wrmsrl(msrs->controls[i].addr, val);
Robert Richterd0e41202010-03-23 19:33:21 +0100104 /*
105 * avoid a false detection of ctr overflows in NMI *
106 * handler
107 */
Andi Kleenb9917022008-08-18 14:50:31 +0200108 wrmsrl(msrs->counters[i].addr, -1LL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 }
110
111 /* enable active counters */
Andi Kleenb9917022008-08-18 14:50:31 +0200112 for (i = 0; i < num_counters; ++i) {
Robert Richter217d3cf2009-06-04 02:36:44 +0200113 if (counter_config[i].enabled && msrs->counters[i].addr) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 reset_value[i] = counter_config[i].count;
Andi Kleenb9917022008-08-18 14:50:31 +0200115 wrmsrl(msrs->counters[i].addr, -reset_value[i]);
Robert Richter3370d352009-05-25 15:10:32 +0200116 rdmsrl(msrs->controls[i].addr, val);
117 val &= model->reserved;
118 val |= op_x86_get_ctrl(model, &counter_config[i]);
119 wrmsrl(msrs->controls[i].addr, val);
Don Zickuscb9c4482006-09-26 10:52:26 +0200120 } else {
121 reset_value[i] = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122 }
123 }
124}
125
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100126
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127static int ppro_check_ctrs(struct pt_regs * const regs,
128 struct op_msrs const * const msrs)
129{
Andi Kleen7c64ade2008-11-07 14:02:49 +0100130 u64 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 int i;
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100132
Robert Richter6e63ea42009-07-07 19:25:39 +0200133 for (i = 0; i < num_counters; ++i) {
Don Zickuscb9c4482006-09-26 10:52:26 +0200134 if (!reset_value[i])
135 continue;
Andi Kleen7c64ade2008-11-07 14:02:49 +0100136 rdmsrl(msrs->counters[i].addr, val);
Robert Richter42399ad2009-05-25 17:59:06 +0200137 if (val & (1ULL << (counter_width - 1)))
138 continue;
139 oprofile_add_sample(regs, i);
140 wrmsrl(msrs->counters[i].addr, -reset_value[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141 }
142
143 /* Only P6 based Pentium M need to re-unmask the apic vector but it
144 * doesn't hurt other P6 variant */
145 apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
146
147 /* We can't work out if we really handled an interrupt. We
148 * might have caught a *second* counter just after overflowing
149 * the interrupt for this counter then arrives
150 * and we don't find a counter that's overflowed, so we
151 * would return 0 and get dazed + confused. Instead we always
152 * assume we found an overflow. This sucks.
153 */
154 return 1;
155}
156
Paolo Ciarrocchi8b45b722008-02-19 23:43:25 +0100157
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158static void ppro_start(struct op_msrs const * const msrs)
159{
Robert Richterdea37662009-05-25 18:11:52 +0200160 u64 val;
Arun Sharma6b77df02006-09-29 02:00:01 -0700161 int i;
Don Zickuscb9c4482006-09-26 10:52:26 +0200162
Andi Kleenb9917022008-08-18 14:50:31 +0200163 for (i = 0; i < num_counters; ++i) {
Arun Sharma6b77df02006-09-29 02:00:01 -0700164 if (reset_value[i]) {
Robert Richterdea37662009-05-25 18:11:52 +0200165 rdmsrl(msrs->controls[i].addr, val);
Robert Richterbb1165d2010-03-01 14:21:23 +0100166 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
Robert Richterdea37662009-05-25 18:11:52 +0200167 wrmsrl(msrs->controls[i].addr, val);
Arun Sharma6b77df02006-09-29 02:00:01 -0700168 }
Don Zickuscb9c4482006-09-26 10:52:26 +0200169 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170}
171
172
173static void ppro_stop(struct op_msrs const * const msrs)
174{
Robert Richterdea37662009-05-25 18:11:52 +0200175 u64 val;
Arun Sharma6b77df02006-09-29 02:00:01 -0700176 int i;
Don Zickuscb9c4482006-09-26 10:52:26 +0200177
Andi Kleenb9917022008-08-18 14:50:31 +0200178 for (i = 0; i < num_counters; ++i) {
Arun Sharma6b77df02006-09-29 02:00:01 -0700179 if (!reset_value[i])
180 continue;
Robert Richterdea37662009-05-25 18:11:52 +0200181 rdmsrl(msrs->controls[i].addr, val);
Robert Richterbb1165d2010-03-01 14:21:23 +0100182 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
Robert Richterdea37662009-05-25 18:11:52 +0200183 wrmsrl(msrs->controls[i].addr, val);
Don Zickuscb9c4482006-09-26 10:52:26 +0200184 }
185}
186
Robert Richter259a83a2009-07-09 15:12:35 +0200187struct op_x86_model_spec op_ppro_spec = {
Robert Richter849620f2009-05-14 17:10:52 +0200188 .num_counters = 2,
189 .num_controls = 2,
Robert Richter3370d352009-05-25 15:10:32 +0200190 .reserved = MSR_PPRO_EVENTSEL_RESERVED,
Robert Richterc92960f2008-09-05 17:12:36 +0200191 .fill_in_addresses = &ppro_fill_in_addresses,
192 .setup_ctrs = &ppro_setup_ctrs,
193 .check_ctrs = &ppro_check_ctrs,
194 .start = &ppro_start,
195 .stop = &ppro_stop,
196 .shutdown = &ppro_shutdown
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197};
Andi Kleenb9917022008-08-18 14:50:31 +0200198
199/*
200 * Architectural performance monitoring.
201 *
202 * Newer Intel CPUs (Core1+) have support for architectural
203 * events described in CPUID 0xA. See the IA32 SDM Vol3b.18 for details.
204 * The advantage of this is that it can be done without knowing about
205 * the specific CPU.
206 */
207
Robert Richtere4192942008-10-12 15:12:34 -0400208static void arch_perfmon_setup_counters(void)
Andi Kleenb9917022008-08-18 14:50:31 +0200209{
210 union cpuid10_eax eax;
211
212 eax.full = cpuid_eax(0xa);
213
214 /* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */
Tejun Heo7b543a52010-12-18 16:30:05 +0100215 if (eax.split.version_id == 0 && __this_cpu_read(cpu_info.x86) == 6 &&
216 __this_cpu_read(cpu_info.x86_model) == 15) {
Andi Kleenb9917022008-08-18 14:50:31 +0200217 eax.split.version_id = 2;
Robert Richter948b1bb2010-03-29 18:36:50 +0200218 eax.split.num_counters = 2;
Andi Kleenb9917022008-08-18 14:50:31 +0200219 eax.split.bit_width = 40;
220 }
221
Robert Richter298557d2011-08-16 23:39:53 +0200222 num_counters = min((int)eax.split.num_counters, OP_MAX_COUNTER);
Andi Kleenb9917022008-08-18 14:50:31 +0200223
224 op_arch_perfmon_spec.num_counters = num_counters;
225 op_arch_perfmon_spec.num_controls = num_counters;
226}
227
Robert Richtere4192942008-10-12 15:12:34 -0400228static int arch_perfmon_init(struct oprofile_operations *ignore)
229{
230 arch_perfmon_setup_counters();
231 return 0;
232}
233
Andi Kleenb9917022008-08-18 14:50:31 +0200234struct op_x86_model_spec op_arch_perfmon_spec = {
Robert Richter3370d352009-05-25 15:10:32 +0200235 .reserved = MSR_PPRO_EVENTSEL_RESERVED,
Robert Richtere4192942008-10-12 15:12:34 -0400236 .init = &arch_perfmon_init,
Andi Kleenb9917022008-08-18 14:50:31 +0200237 /* num_counters/num_controls filled in at runtime */
Robert Richter5a289392008-10-15 22:19:41 +0200238 .fill_in_addresses = &ppro_fill_in_addresses,
Andi Kleenb9917022008-08-18 14:50:31 +0200239 /* user space does the cpuid check for available events */
Robert Richter5a289392008-10-15 22:19:41 +0200240 .setup_ctrs = &ppro_setup_ctrs,
241 .check_ctrs = &ppro_check_ctrs,
242 .start = &ppro_start,
243 .stop = &ppro_stop,
244 .shutdown = &ppro_shutdown
Andi Kleenb9917022008-08-18 14:50:31 +0200245};