Paolo Ciarrocchi | 8b45b72 | 2008-02-19 23:43:25 +0100 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * @file op_model_ppro.h |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 3 | * Family 6 perfmon and architectural perfmon MSR operations |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * |
| 5 | * @remark Copyright 2002 OProfile authors |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 6 | * @remark Copyright 2008 Intel Corporation |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * @remark Read the file COPYING |
| 8 | * |
| 9 | * @author John Levon |
| 10 | * @author Philippe Elie |
| 11 | * @author Graydon Hoare |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 12 | * @author Andi Kleen |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 13 | * @author Robert Richter <robert.richter@amd.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <linux/oprofile.h> |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 17 | #include <linux/slab.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <asm/ptrace.h> |
| 19 | #include <asm/msr.h> |
| 20 | #include <asm/apic.h> |
Don Zickus | 3e4ff11 | 2006-06-26 13:57:01 +0200 | [diff] [blame] | 21 | #include <asm/nmi.h> |
Paolo Ciarrocchi | 8b45b72 | 2008-02-19 23:43:25 +0100 | [diff] [blame] | 22 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #include "op_x86_model.h" |
| 24 | #include "op_counter.h" |
| 25 | |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 26 | static int num_counters = 2; |
| 27 | static int counter_width = 32; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 29 | #define MSR_PPRO_EVENTSEL_RESERVED ((0xFFFFFFFFULL<<32)|(1ULL<<21)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | |
Maarten Lankhorst | 1d12d35 | 2011-08-01 11:08:59 -0400 | [diff] [blame] | 31 | static u64 reset_value[OP_MAX_COUNTER]; |
Paolo Ciarrocchi | 8b45b72 | 2008-02-19 23:43:25 +0100 | [diff] [blame] | 32 | |
Robert Richter | 83300ce | 2010-03-23 20:01:54 +0100 | [diff] [blame] | 33 | static void ppro_shutdown(struct op_msrs const * const msrs) |
| 34 | { |
| 35 | int i; |
| 36 | |
| 37 | for (i = 0; i < num_counters; ++i) { |
| 38 | if (!msrs->counters[i].addr) |
| 39 | continue; |
| 40 | release_perfctr_nmi(MSR_P6_PERFCTR0 + i); |
| 41 | release_evntsel_nmi(MSR_P6_EVNTSEL0 + i); |
| 42 | } |
Robert Richter | 83300ce | 2010-03-23 20:01:54 +0100 | [diff] [blame] | 43 | } |
| 44 | |
Robert Richter | 8617f98 | 2010-02-26 17:20:55 +0100 | [diff] [blame] | 45 | static int ppro_fill_in_addresses(struct op_msrs * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 46 | { |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 47 | int i; |
| 48 | |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 49 | for (i = 0; i < num_counters; i++) { |
Robert Richter | d0e4120 | 2010-03-23 19:33:21 +0100 | [diff] [blame] | 50 | if (!reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i)) |
Robert Richter | 8617f98 | 2010-02-26 17:20:55 +0100 | [diff] [blame] | 51 | goto fail; |
Robert Richter | d0e4120 | 2010-03-23 19:33:21 +0100 | [diff] [blame] | 52 | if (!reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i)) { |
| 53 | release_perfctr_nmi(MSR_P6_PERFCTR0 + i); |
Robert Richter | 8617f98 | 2010-02-26 17:20:55 +0100 | [diff] [blame] | 54 | goto fail; |
Robert Richter | d0e4120 | 2010-03-23 19:33:21 +0100 | [diff] [blame] | 55 | } |
| 56 | /* both registers must be reserved */ |
| 57 | msrs->counters[i].addr = MSR_P6_PERFCTR0 + i; |
| 58 | msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i; |
Robert Richter | 8617f98 | 2010-02-26 17:20:55 +0100 | [diff] [blame] | 59 | continue; |
| 60 | fail: |
| 61 | if (!counter_config[i].enabled) |
| 62 | continue; |
| 63 | op_x86_warn_reserved(i); |
| 64 | ppro_shutdown(msrs); |
| 65 | return -EBUSY; |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 66 | } |
Robert Richter | 8617f98 | 2010-02-26 17:20:55 +0100 | [diff] [blame] | 67 | |
| 68 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | } |
| 70 | |
| 71 | |
Robert Richter | ef8828d | 2009-05-25 19:31:44 +0200 | [diff] [blame] | 72 | static void ppro_setup_ctrs(struct op_x86_model_spec const *model, |
| 73 | struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | { |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 75 | u64 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | int i; |
| 77 | |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 78 | if (cpu_has_arch_perfmon) { |
| 79 | union cpuid10_eax eax; |
| 80 | eax.full = cpuid_eax(0xa); |
Tim Blechmann | 780eef9 | 2009-02-19 17:34:03 +0100 | [diff] [blame] | 81 | |
| 82 | /* |
| 83 | * For Core2 (family 6, model 15), don't reset the |
| 84 | * counter width: |
| 85 | */ |
| 86 | if (!(eax.split.version_id == 0 && |
Tejun Heo | 7b543a5 | 2010-12-18 16:30:05 +0100 | [diff] [blame] | 87 | __this_cpu_read(cpu_info.x86) == 6 && |
| 88 | __this_cpu_read(cpu_info.x86_model) == 15)) { |
Tim Blechmann | 780eef9 | 2009-02-19 17:34:03 +0100 | [diff] [blame] | 89 | |
| 90 | if (counter_width < eax.split.bit_width) |
| 91 | counter_width = eax.split.bit_width; |
| 92 | } |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 93 | } |
| 94 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | /* clear all counters */ |
Robert Richter | 6e63ea4 | 2009-07-07 19:25:39 +0200 | [diff] [blame] | 96 | for (i = 0; i < num_counters; ++i) { |
Robert Richter | 8617f98 | 2010-02-26 17:20:55 +0100 | [diff] [blame] | 97 | if (!msrs->controls[i].addr) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 98 | continue; |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 99 | rdmsrl(msrs->controls[i].addr, val); |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 100 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) |
Robert Richter | 98a2e73 | 2010-02-23 18:14:58 +0100 | [diff] [blame] | 101 | op_x86_warn_in_use(i); |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 102 | val &= model->reserved; |
| 103 | wrmsrl(msrs->controls[i].addr, val); |
Robert Richter | d0e4120 | 2010-03-23 19:33:21 +0100 | [diff] [blame] | 104 | /* |
| 105 | * avoid a false detection of ctr overflows in NMI * |
| 106 | * handler |
| 107 | */ |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 108 | wrmsrl(msrs->counters[i].addr, -1LL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | /* enable active counters */ |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 112 | for (i = 0; i < num_counters; ++i) { |
Robert Richter | 217d3cf | 2009-06-04 02:36:44 +0200 | [diff] [blame] | 113 | if (counter_config[i].enabled && msrs->counters[i].addr) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | reset_value[i] = counter_config[i].count; |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 115 | wrmsrl(msrs->counters[i].addr, -reset_value[i]); |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 116 | rdmsrl(msrs->controls[i].addr, val); |
| 117 | val &= model->reserved; |
| 118 | val |= op_x86_get_ctrl(model, &counter_config[i]); |
| 119 | wrmsrl(msrs->controls[i].addr, val); |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 120 | } else { |
| 121 | reset_value[i] = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 122 | } |
| 123 | } |
| 124 | } |
| 125 | |
Paolo Ciarrocchi | 8b45b72 | 2008-02-19 23:43:25 +0100 | [diff] [blame] | 126 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 127 | static int ppro_check_ctrs(struct pt_regs * const regs, |
| 128 | struct op_msrs const * const msrs) |
| 129 | { |
Andi Kleen | 7c64ade | 2008-11-07 14:02:49 +0100 | [diff] [blame] | 130 | u64 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 131 | int i; |
Paolo Ciarrocchi | 8b45b72 | 2008-02-19 23:43:25 +0100 | [diff] [blame] | 132 | |
Robert Richter | 6e63ea4 | 2009-07-07 19:25:39 +0200 | [diff] [blame] | 133 | for (i = 0; i < num_counters; ++i) { |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 134 | if (!reset_value[i]) |
| 135 | continue; |
Andi Kleen | 7c64ade | 2008-11-07 14:02:49 +0100 | [diff] [blame] | 136 | rdmsrl(msrs->counters[i].addr, val); |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame] | 137 | if (val & (1ULL << (counter_width - 1))) |
| 138 | continue; |
| 139 | oprofile_add_sample(regs, i); |
| 140 | wrmsrl(msrs->counters[i].addr, -reset_value[i]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | /* Only P6 based Pentium M need to re-unmask the apic vector but it |
| 144 | * doesn't hurt other P6 variant */ |
| 145 | apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED); |
| 146 | |
| 147 | /* We can't work out if we really handled an interrupt. We |
| 148 | * might have caught a *second* counter just after overflowing |
| 149 | * the interrupt for this counter then arrives |
| 150 | * and we don't find a counter that's overflowed, so we |
| 151 | * would return 0 and get dazed + confused. Instead we always |
| 152 | * assume we found an overflow. This sucks. |
| 153 | */ |
| 154 | return 1; |
| 155 | } |
| 156 | |
Paolo Ciarrocchi | 8b45b72 | 2008-02-19 23:43:25 +0100 | [diff] [blame] | 157 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | static void ppro_start(struct op_msrs const * const msrs) |
| 159 | { |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 160 | u64 val; |
Arun Sharma | 6b77df0 | 2006-09-29 02:00:01 -0700 | [diff] [blame] | 161 | int i; |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 162 | |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 163 | for (i = 0; i < num_counters; ++i) { |
Arun Sharma | 6b77df0 | 2006-09-29 02:00:01 -0700 | [diff] [blame] | 164 | if (reset_value[i]) { |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 165 | rdmsrl(msrs->controls[i].addr, val); |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 166 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 167 | wrmsrl(msrs->controls[i].addr, val); |
Arun Sharma | 6b77df0 | 2006-09-29 02:00:01 -0700 | [diff] [blame] | 168 | } |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 169 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | |
| 173 | static void ppro_stop(struct op_msrs const * const msrs) |
| 174 | { |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 175 | u64 val; |
Arun Sharma | 6b77df0 | 2006-09-29 02:00:01 -0700 | [diff] [blame] | 176 | int i; |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 177 | |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 178 | for (i = 0; i < num_counters; ++i) { |
Arun Sharma | 6b77df0 | 2006-09-29 02:00:01 -0700 | [diff] [blame] | 179 | if (!reset_value[i]) |
| 180 | continue; |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 181 | rdmsrl(msrs->controls[i].addr, val); |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 182 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 183 | wrmsrl(msrs->controls[i].addr, val); |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 184 | } |
| 185 | } |
| 186 | |
Robert Richter | 259a83a | 2009-07-09 15:12:35 +0200 | [diff] [blame] | 187 | struct op_x86_model_spec op_ppro_spec = { |
Robert Richter | 849620f | 2009-05-14 17:10:52 +0200 | [diff] [blame] | 188 | .num_counters = 2, |
| 189 | .num_controls = 2, |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 190 | .reserved = MSR_PPRO_EVENTSEL_RESERVED, |
Robert Richter | c92960f | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 191 | .fill_in_addresses = &ppro_fill_in_addresses, |
| 192 | .setup_ctrs = &ppro_setup_ctrs, |
| 193 | .check_ctrs = &ppro_check_ctrs, |
| 194 | .start = &ppro_start, |
| 195 | .stop = &ppro_stop, |
| 196 | .shutdown = &ppro_shutdown |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 197 | }; |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 198 | |
| 199 | /* |
| 200 | * Architectural performance monitoring. |
| 201 | * |
| 202 | * Newer Intel CPUs (Core1+) have support for architectural |
| 203 | * events described in CPUID 0xA. See the IA32 SDM Vol3b.18 for details. |
| 204 | * The advantage of this is that it can be done without knowing about |
| 205 | * the specific CPU. |
| 206 | */ |
| 207 | |
Robert Richter | e419294 | 2008-10-12 15:12:34 -0400 | [diff] [blame] | 208 | static void arch_perfmon_setup_counters(void) |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 209 | { |
| 210 | union cpuid10_eax eax; |
| 211 | |
| 212 | eax.full = cpuid_eax(0xa); |
| 213 | |
| 214 | /* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */ |
Tejun Heo | 7b543a5 | 2010-12-18 16:30:05 +0100 | [diff] [blame] | 215 | if (eax.split.version_id == 0 && __this_cpu_read(cpu_info.x86) == 6 && |
| 216 | __this_cpu_read(cpu_info.x86_model) == 15) { |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 217 | eax.split.version_id = 2; |
Robert Richter | 948b1bb | 2010-03-29 18:36:50 +0200 | [diff] [blame] | 218 | eax.split.num_counters = 2; |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 219 | eax.split.bit_width = 40; |
| 220 | } |
| 221 | |
Robert Richter | 298557d | 2011-08-16 23:39:53 +0200 | [diff] [blame] | 222 | num_counters = min((int)eax.split.num_counters, OP_MAX_COUNTER); |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 223 | |
| 224 | op_arch_perfmon_spec.num_counters = num_counters; |
| 225 | op_arch_perfmon_spec.num_controls = num_counters; |
| 226 | } |
| 227 | |
Robert Richter | e419294 | 2008-10-12 15:12:34 -0400 | [diff] [blame] | 228 | static int arch_perfmon_init(struct oprofile_operations *ignore) |
| 229 | { |
| 230 | arch_perfmon_setup_counters(); |
| 231 | return 0; |
| 232 | } |
| 233 | |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 234 | struct op_x86_model_spec op_arch_perfmon_spec = { |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 235 | .reserved = MSR_PPRO_EVENTSEL_RESERVED, |
Robert Richter | e419294 | 2008-10-12 15:12:34 -0400 | [diff] [blame] | 236 | .init = &arch_perfmon_init, |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 237 | /* num_counters/num_controls filled in at runtime */ |
Robert Richter | 5a28939 | 2008-10-15 22:19:41 +0200 | [diff] [blame] | 238 | .fill_in_addresses = &ppro_fill_in_addresses, |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 239 | /* user space does the cpuid check for available events */ |
Robert Richter | 5a28939 | 2008-10-15 22:19:41 +0200 | [diff] [blame] | 240 | .setup_ctrs = &ppro_setup_ctrs, |
| 241 | .check_ctrs = &ppro_check_ctrs, |
| 242 | .start = &ppro_start, |
| 243 | .stop = &ppro_stop, |
| 244 | .shutdown = &ppro_shutdown |
Andi Kleen | b991702 | 2008-08-18 14:50:31 +0200 | [diff] [blame] | 245 | }; |