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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-pxa/irq.c
3 *
eric miaoe3630db2008-03-04 11:42:26 +08004 * Generic PXA IRQ handling
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +020017#include <linux/syscore_ops.h>
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080018#include <linux/io.h>
19#include <linux/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
Jamie Iles5a567d72011-10-08 11:20:42 +010021#include <asm/exception.h>
22
Russell Kinga09e64f2008-08-05 16:14:15 +010023#include <mach/hardware.h>
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080024#include <mach/irqs.h>
Linus Walleijf55be1b2011-09-28 09:11:30 +010025#include <mach/gpio-pxa.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
27#include "generic.h"
28
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080029#define IRQ_BASE (void __iomem *)io_p2v(0x40d00000)
Haojian Zhuangc482ae42009-11-02 14:02:21 -050030
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080031#define ICIP (0x000)
32#define ICMR (0x004)
33#define ICLR (0x008)
34#define ICFR (0x00c)
35#define ICPR (0x010)
36#define ICCR (0x014)
37#define ICHP (0x018)
38#define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \
39 ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \
40 (0x144 + (((i) - 64) << 2)))
Eric Miaoa551e4f2011-04-27 22:48:05 +080041#define ICHP_VAL_IRQ (1 << 31)
42#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080043#define IPR_VALID (1 << 31)
44#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
45
46#define MAX_INTERNAL_IRQS 128
Linus Torvalds1da177e2005-04-16 15:20:36 -070047
48/*
49 * This is for peripheral IRQs internal to the PXA chip.
50 */
51
eric miaof6fb7af2008-03-04 13:53:05 +080052static int pxa_internal_irq_nr;
53
Haojian Zhuangbb71bdd2010-11-17 19:03:36 +080054static inline int cpu_has_ipr(void)
55{
56 return !cpu_is_pxa25x();
57}
58
Eric Miaoa1015a12011-01-12 16:42:24 -060059static inline void __iomem *irq_base(int i)
60{
61 static unsigned long phys_base[] = {
62 0x40d00000,
63 0x40d0009c,
64 0x40d00130,
65 };
66
67 return (void __iomem *)io_p2v(phys_base[i]);
68}
69
Eric Miao5d284e32011-04-27 22:48:04 +080070void pxa_mask_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070071{
Lennert Buytenheka3f4c922010-11-29 11:18:26 +010072 void __iomem *base = irq_data_get_irq_chip_data(d);
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080073 uint32_t icmr = __raw_readl(base + ICMR);
74
Lennert Buytenheka3f4c922010-11-29 11:18:26 +010075 icmr &= ~(1 << IRQ_BIT(d->irq));
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080076 __raw_writel(icmr, base + ICMR);
Linus Torvalds1da177e2005-04-16 15:20:36 -070077}
78
Eric Miao5d284e32011-04-27 22:48:04 +080079void pxa_unmask_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070080{
Lennert Buytenheka3f4c922010-11-29 11:18:26 +010081 void __iomem *base = irq_data_get_irq_chip_data(d);
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080082 uint32_t icmr = __raw_readl(base + ICMR);
83
Lennert Buytenheka3f4c922010-11-29 11:18:26 +010084 icmr |= 1 << IRQ_BIT(d->irq);
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +080085 __raw_writel(icmr, base + ICMR);
Linus Torvalds1da177e2005-04-16 15:20:36 -070086}
87
eric miaof6fb7af2008-03-04 13:53:05 +080088static struct irq_chip pxa_internal_irq_chip = {
David Brownell38c677c2006-08-01 22:26:25 +010089 .name = "SC",
Lennert Buytenheka3f4c922010-11-29 11:18:26 +010090 .irq_ack = pxa_mask_irq,
91 .irq_mask = pxa_mask_irq,
92 .irq_unmask = pxa_unmask_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -070093};
94
Eric Miaoa58fbcd2009-01-06 17:37:37 +080095/*
96 * GPIO IRQs for GPIO 0 and 1
97 */
Lennert Buytenheka3f4c922010-11-29 11:18:26 +010098static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type)
Eric Miaoa58fbcd2009-01-06 17:37:37 +080099{
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100100 int gpio = d->irq - IRQ_GPIO0;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800101
102 if (__gpio_is_occupied(gpio)) {
103 pr_err("%s failed: GPIO is configured\n", __func__);
104 return -EINVAL;
105 }
106
107 if (type & IRQ_TYPE_EDGE_RISING)
108 GRER0 |= GPIO_bit(gpio);
109 else
110 GRER0 &= ~GPIO_bit(gpio);
111
112 if (type & IRQ_TYPE_EDGE_FALLING)
113 GFER0 |= GPIO_bit(gpio);
114 else
115 GFER0 &= ~GPIO_bit(gpio);
116
117 return 0;
118}
119
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100120static void pxa_ack_low_gpio(struct irq_data *d)
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800121{
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100122 GEDR0 = (1 << (d->irq - IRQ_GPIO0));
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800123}
124
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800125static struct irq_chip pxa_low_gpio_chip = {
126 .name = "GPIO-l",
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100127 .irq_ack = pxa_ack_low_gpio,
Eric Miaoa1015a12011-01-12 16:42:24 -0600128 .irq_mask = pxa_mask_irq,
129 .irq_unmask = pxa_unmask_irq,
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100130 .irq_set_type = pxa_set_low_gpio_type,
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800131};
132
Eric Miaoa551e4f2011-04-27 22:48:05 +0800133asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
134{
135 uint32_t icip, icmr, mask;
136
137 do {
138 icip = __raw_readl(IRQ_BASE + ICIP);
139 icmr = __raw_readl(IRQ_BASE + ICMR);
140 mask = icip & icmr;
141
142 if (mask == 0)
143 break;
144
145 handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
146 } while (1);
147}
148
149asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
150{
151 uint32_t ichp;
152
153 do {
154 __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));
155
156 if ((ichp & ICHP_VAL_IRQ) == 0)
157 break;
158
159 handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
160 } while (1);
161}
162
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800163static void __init pxa_init_low_gpio_irq(set_wake_t fn)
164{
165 int irq;
166
167 /* clear edge detection on GPIO 0 and 1 */
168 GFER0 &= ~0x3;
169 GRER0 &= ~0x3;
170 GEDR0 = 0x3;
171
172 for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +0100173 irq_set_chip_and_handler(irq, &pxa_low_gpio_chip,
174 handle_edge_irq);
Thomas Gleixner9323f2612011-03-24 13:29:39 +0100175 irq_set_chip_data(irq, irq_base(0));
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800176 set_irq_flags(irq, IRQF_VALID);
177 }
178
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100179 pxa_low_gpio_chip.irq_set_wake = fn;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800180}
181
eric miaob9e25ac2008-03-04 14:19:58 +0800182void __init pxa_init_irq(int irq_nr, set_wake_t fn)
Eric Miao53665a52007-06-06 06:36:04 +0100183{
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800184 int irq, i, n;
Eric Miao53665a52007-06-06 06:36:04 +0100185
Haojian Zhuangc482ae42009-11-02 14:02:21 -0500186 BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
187
eric miaof6fb7af2008-03-04 13:53:05 +0800188 pxa_internal_irq_nr = irq_nr;
Eric Miao53665a52007-06-06 06:36:04 +0100189
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800190 for (n = 0; n < irq_nr; n += 32) {
Marek Vasut1b624fb2011-01-10 23:53:12 +0100191 void __iomem *base = irq_base(n >> 5);
Eric Miao53665a52007-06-06 06:36:04 +0100192
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800193 __raw_writel(0, base + ICMR); /* disable all IRQs */
194 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
195 for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
196 /* initialize interrupt priority */
197 if (cpu_has_ipr())
198 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
199
200 irq = PXA_IRQ(i);
Thomas Gleixnerf38c02f2011-03-24 13:35:09 +0100201 irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
202 handle_level_irq);
Thomas Gleixner9323f2612011-03-24 13:29:39 +0100203 irq_set_chip_data(irq, base);
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800204 set_irq_flags(irq, IRQF_VALID);
205 }
Haojian Zhuangd2c37062009-08-19 19:49:31 +0800206 }
207
Eric Miao53665a52007-06-06 06:36:04 +0100208 /* only unmasked interrupts kick us out of idle */
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800209 __raw_writel(1, irq_base(0) + ICCR);
Eric Miao53665a52007-06-06 06:36:04 +0100210
Lennert Buytenheka3f4c922010-11-29 11:18:26 +0100211 pxa_internal_irq_chip.irq_set_wake = fn;
Eric Miaoa58fbcd2009-01-06 17:37:37 +0800212 pxa_init_low_gpio_irq(fn);
eric miaoc95530c2007-08-29 10:22:17 +0100213}
eric miaoc01655042008-01-28 23:00:02 +0000214
215#ifdef CONFIG_PM
Haojian Zhuangc482ae42009-11-02 14:02:21 -0500216static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
217static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
eric miaoc01655042008-01-28 23:00:02 +0000218
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200219static int pxa_irq_suspend(void)
eric miaoc01655042008-01-28 23:00:02 +0000220{
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800221 int i;
eric miaof6fb7af2008-03-04 13:53:05 +0800222
Marek Vasut1b624fb2011-01-10 23:53:12 +0100223 for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800224 void __iomem *base = irq_base(i);
225
226 saved_icmr[i] = __raw_readl(base + ICMR);
227 __raw_writel(0, base + ICMR);
eric miaoc01655042008-01-28 23:00:02 +0000228 }
Eric Miaoc70f5a62010-01-11 20:39:37 +0800229
Haojian Zhuangbb71bdd2010-11-17 19:03:36 +0800230 if (cpu_has_ipr()) {
Eric Miaoc70f5a62010-01-11 20:39:37 +0800231 for (i = 0; i < pxa_internal_irq_nr; i++)
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800232 saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
Eric Miaoc70f5a62010-01-11 20:39:37 +0800233 }
eric miaoc01655042008-01-28 23:00:02 +0000234
235 return 0;
236}
237
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200238static void pxa_irq_resume(void)
eric miaoc01655042008-01-28 23:00:02 +0000239{
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800240 int i;
eric miaof6fb7af2008-03-04 13:53:05 +0800241
Marek Vasut1b624fb2011-01-10 23:53:12 +0100242 for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800243 void __iomem *base = irq_base(i);
244
245 __raw_writel(saved_icmr[i], base + ICMR);
246 __raw_writel(0, base + ICLR);
247 }
248
Marek Vasut57879b82011-01-10 00:29:04 +0100249 if (cpu_has_ipr())
Eric Miaoc70f5a62010-01-11 20:39:37 +0800250 for (i = 0; i < pxa_internal_irq_nr; i++)
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800251 __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
Eric Miaoc70f5a62010-01-11 20:39:37 +0800252
Haojian Zhuanga79a9ad2010-11-24 11:54:22 +0800253 __raw_writel(1, IRQ_BASE + ICCR);
eric miaoc01655042008-01-28 23:00:02 +0000254}
255#else
256#define pxa_irq_suspend NULL
257#define pxa_irq_resume NULL
258#endif
259
Rafael J. Wysocki2eaa03b2011-04-22 22:03:11 +0200260struct syscore_ops pxa_irq_syscore_ops = {
eric miaoc01655042008-01-28 23:00:02 +0000261 .suspend = pxa_irq_suspend,
262 .resume = pxa_irq_resume,
263};