Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file contains work-arounds for x86 and x86_64 platform bugs. |
| 3 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | #include <linux/pci.h> |
| 5 | #include <linux/irq.h> |
| 6 | |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 7 | #include <asm/hpet.h> |
| 8 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI) |
| 10 | |
Andrew Morton | a86f34b | 2007-05-02 19:27:04 +0200 | [diff] [blame] | 11 | static void __devinit quirk_intel_irqbalance(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | { |
| 13 | u8 config, rev; |
Matthew Wilcox | 9585ca0 | 2008-02-10 23:18:15 -0500 | [diff] [blame] | 14 | u16 word; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | |
| 16 | /* BIOS may enable hardware IRQ balancing for |
| 17 | * E7520/E7320/E7525(revision ID 0x9 and below) |
| 18 | * based platforms. |
| 19 | * Disable SW irqbalance/affinity on those platforms. |
| 20 | */ |
Andrew Morton | a86f34b | 2007-05-02 19:27:04 +0200 | [diff] [blame] | 21 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | if (rev > 0x9) |
| 23 | return; |
| 24 | |
Andrew Morton | a86f34b | 2007-05-02 19:27:04 +0200 | [diff] [blame] | 25 | /* enable access to config space*/ |
| 26 | pci_read_config_byte(dev, 0xf4, &config); |
| 27 | pci_write_config_byte(dev, 0xf4, config|0x2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Matthew Wilcox | 9585ca0 | 2008-02-10 23:18:15 -0500 | [diff] [blame] | 29 | /* |
| 30 | * read xTPR register. We may not have a pci_dev for device 8 |
| 31 | * because it might be hidden until the above write. |
| 32 | */ |
| 33 | pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | |
| 35 | if (!(word & (1 << 13))) { |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 36 | dev_info(&dev->dev, "Intel E7520/7320/7525 detected; " |
| 37 | "disabling irq balancing and affinity\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | noirqdebug_setup(""); |
| 39 | #ifdef CONFIG_PROC_FS |
| 40 | no_irq_affinity = 1; |
| 41 | #endif |
| 42 | } |
| 43 | |
Andrew Morton | a86f34b | 2007-05-02 19:27:04 +0200 | [diff] [blame] | 44 | /* put back the original value for config space*/ |
Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 45 | if (!(config & 0x2)) |
Andrew Morton | a86f34b | 2007-05-02 19:27:04 +0200 | [diff] [blame] | 46 | pci_write_config_byte(dev, 0xf4, config); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | } |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 48 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, |
| 49 | quirk_intel_irqbalance); |
| 50 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, |
| 51 | quirk_intel_irqbalance); |
| 52 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, |
| 53 | quirk_intel_irqbalance); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | #endif |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 55 | |
| 56 | #if defined(CONFIG_HPET_TIMER) |
| 57 | unsigned long force_hpet_address; |
| 58 | |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 59 | static enum { |
| 60 | NONE_FORCE_HPET_RESUME, |
| 61 | OLD_ICH_FORCE_HPET_RESUME, |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 62 | ICH_FORCE_HPET_RESUME, |
Carlos Corbacho | d79a5f8 | 2007-10-19 18:51:27 +0100 | [diff] [blame] | 63 | VT8237_FORCE_HPET_RESUME, |
| 64 | NVIDIA_FORCE_HPET_RESUME, |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 65 | ATI_FORCE_HPET_RESUME, |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 66 | } force_hpet_resume_type; |
| 67 | |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 68 | static void __iomem *rcba_base; |
| 69 | |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 70 | static void ich_force_hpet_resume(void) |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 71 | { |
| 72 | u32 val; |
| 73 | |
| 74 | if (!force_hpet_address) |
| 75 | return; |
| 76 | |
| 77 | if (rcba_base == NULL) |
| 78 | BUG(); |
| 79 | |
| 80 | /* read the Function Disable register, dword mode only */ |
| 81 | val = readl(rcba_base + 0x3404); |
| 82 | if (!(val & 0x80)) { |
| 83 | /* HPET disabled in HPTC. Trying to enable */ |
| 84 | writel(val | 0x80, rcba_base + 0x3404); |
| 85 | } |
| 86 | |
| 87 | val = readl(rcba_base + 0x3404); |
| 88 | if (!(val & 0x80)) |
| 89 | BUG(); |
| 90 | else |
| 91 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); |
| 92 | |
| 93 | return; |
| 94 | } |
| 95 | |
| 96 | static void ich_force_enable_hpet(struct pci_dev *dev) |
| 97 | { |
| 98 | u32 val; |
| 99 | u32 uninitialized_var(rcba); |
| 100 | int err = 0; |
| 101 | |
| 102 | if (hpet_address || force_hpet_address) |
| 103 | return; |
| 104 | |
| 105 | pci_read_config_dword(dev, 0xF0, &rcba); |
| 106 | rcba &= 0xFFFFC000; |
| 107 | if (rcba == 0) { |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 108 | dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; " |
| 109 | "cannot force enable HPET\n"); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 110 | return; |
| 111 | } |
| 112 | |
| 113 | /* use bits 31:14, 16 kB aligned */ |
| 114 | rcba_base = ioremap_nocache(rcba, 0x4000); |
| 115 | if (rcba_base == NULL) { |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 116 | dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; " |
| 117 | "cannot force enable HPET\n"); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 118 | return; |
| 119 | } |
| 120 | |
| 121 | /* read the Function Disable register, dword mode only */ |
| 122 | val = readl(rcba_base + 0x3404); |
| 123 | |
| 124 | if (val & 0x80) { |
| 125 | /* HPET is enabled in HPTC. Just not reported by BIOS */ |
| 126 | val = val & 0x3; |
| 127 | force_hpet_address = 0xFED00000 | (val << 12); |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 128 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
| 129 | "0x%lx\n", force_hpet_address); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 130 | iounmap(rcba_base); |
| 131 | return; |
| 132 | } |
| 133 | |
| 134 | /* HPET disabled in HPTC. Trying to enable */ |
| 135 | writel(val | 0x80, rcba_base + 0x3404); |
| 136 | |
| 137 | val = readl(rcba_base + 0x3404); |
| 138 | if (!(val & 0x80)) { |
| 139 | err = 1; |
| 140 | } else { |
| 141 | val = val & 0x3; |
| 142 | force_hpet_address = 0xFED00000 | (val << 12); |
| 143 | } |
| 144 | |
| 145 | if (err) { |
| 146 | force_hpet_address = 0; |
| 147 | iounmap(rcba_base); |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 148 | dev_printk(KERN_DEBUG, &dev->dev, |
| 149 | "Failed to force enable HPET\n"); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 150 | } else { |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 151 | force_hpet_resume_type = ICH_FORCE_HPET_RESUME; |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 152 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
| 153 | "0x%lx\n", force_hpet_address); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 154 | } |
| 155 | } |
| 156 | |
| 157 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 158 | ich_force_enable_hpet); |
Krzysztof Oledzki | 74e411c | 2008-06-04 03:40:17 +0200 | [diff] [blame] | 159 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, |
| 160 | ich_force_enable_hpet); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 161 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 162 | ich_force_enable_hpet); |
Venki Pallipadi | ed6fb17 | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 163 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 164 | ich_force_enable_hpet); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 165 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 166 | ich_force_enable_hpet); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 167 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 168 | ich_force_enable_hpet); |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 169 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 170 | ich_force_enable_hpet); |
Janne Kulmala | bacbe99 | 2008-12-16 13:39:57 +0200 | [diff] [blame] | 171 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, |
| 172 | ich_force_enable_hpet); |
Alistair John Strachan | dff244a | 2008-01-30 13:33:39 +0100 | [diff] [blame] | 173 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, |
| 174 | ich_force_enable_hpet); |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 175 | |
| 176 | |
| 177 | static struct pci_dev *cached_dev; |
| 178 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 179 | static void hpet_print_force_info(void) |
| 180 | { |
| 181 | printk(KERN_INFO "HPET not enabled in BIOS. " |
| 182 | "You might try hpet=force boot option\n"); |
| 183 | } |
| 184 | |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 185 | static void old_ich_force_hpet_resume(void) |
| 186 | { |
| 187 | u32 val; |
| 188 | u32 uninitialized_var(gen_cntl); |
| 189 | |
| 190 | if (!force_hpet_address || !cached_dev) |
| 191 | return; |
| 192 | |
| 193 | pci_read_config_dword(cached_dev, 0xD0, &gen_cntl); |
| 194 | gen_cntl &= (~(0x7 << 15)); |
| 195 | gen_cntl |= (0x4 << 15); |
| 196 | |
| 197 | pci_write_config_dword(cached_dev, 0xD0, gen_cntl); |
| 198 | pci_read_config_dword(cached_dev, 0xD0, &gen_cntl); |
| 199 | val = gen_cntl >> 15; |
| 200 | val &= 0x7; |
| 201 | if (val == 0x4) |
| 202 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); |
| 203 | else |
| 204 | BUG(); |
| 205 | } |
| 206 | |
| 207 | static void old_ich_force_enable_hpet(struct pci_dev *dev) |
| 208 | { |
| 209 | u32 val; |
| 210 | u32 uninitialized_var(gen_cntl); |
| 211 | |
| 212 | if (hpet_address || force_hpet_address) |
| 213 | return; |
| 214 | |
| 215 | pci_read_config_dword(dev, 0xD0, &gen_cntl); |
| 216 | /* |
| 217 | * Bit 17 is HPET enable bit. |
| 218 | * Bit 16:15 control the HPET base address. |
| 219 | */ |
| 220 | val = gen_cntl >> 15; |
| 221 | val &= 0x7; |
| 222 | if (val & 0x4) { |
| 223 | val &= 0x3; |
| 224 | force_hpet_address = 0xFED00000 | (val << 12); |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 225 | dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n", |
| 226 | force_hpet_address); |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 227 | return; |
| 228 | } |
| 229 | |
| 230 | /* |
| 231 | * HPET is disabled. Trying enabling at FED00000 and check |
| 232 | * whether it sticks |
| 233 | */ |
| 234 | gen_cntl &= (~(0x7 << 15)); |
| 235 | gen_cntl |= (0x4 << 15); |
| 236 | pci_write_config_dword(dev, 0xD0, gen_cntl); |
| 237 | |
| 238 | pci_read_config_dword(dev, 0xD0, &gen_cntl); |
| 239 | |
| 240 | val = gen_cntl >> 15; |
| 241 | val &= 0x7; |
| 242 | if (val & 0x4) { |
| 243 | /* HPET is enabled in HPTC. Just not reported by BIOS */ |
| 244 | val &= 0x3; |
| 245 | force_hpet_address = 0xFED00000 | (val << 12); |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 246 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
| 247 | "0x%lx\n", force_hpet_address); |
Venki Pallipadi | 32a2da6 | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 248 | cached_dev = dev; |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 249 | force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME; |
| 250 | return; |
| 251 | } |
| 252 | |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 253 | dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n"); |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 254 | } |
| 255 | |
Udo A. Steinberg | 158ad32 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 256 | /* |
| 257 | * Undocumented chipset features. Make sure that the user enforced |
| 258 | * this. |
| 259 | */ |
| 260 | static void old_ich_force_enable_hpet_user(struct pci_dev *dev) |
| 261 | { |
| 262 | if (hpet_force_user) |
| 263 | old_ich_force_enable_hpet(dev); |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 264 | else |
| 265 | hpet_print_force_info(); |
Udo A. Steinberg | 158ad32 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 266 | } |
| 267 | |
Joe Buehler | 4c2a997 | 2008-06-09 08:55:20 -0400 | [diff] [blame] | 268 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, |
| 269 | old_ich_force_enable_hpet_user); |
Udo A. Steinberg | 158ad32 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 270 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, |
| 271 | old_ich_force_enable_hpet_user); |
| 272 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, |
| 273 | old_ich_force_enable_hpet_user); |
| 274 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, |
| 275 | old_ich_force_enable_hpet_user); |
| 276 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, |
| 277 | old_ich_force_enable_hpet_user); |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 278 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 279 | old_ich_force_enable_hpet); |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 280 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12, |
Thomas Gleixner | 7649223 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 281 | old_ich_force_enable_hpet); |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 282 | |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 283 | |
| 284 | static void vt8237_force_hpet_resume(void) |
| 285 | { |
| 286 | u32 val; |
| 287 | |
| 288 | if (!force_hpet_address || !cached_dev) |
| 289 | return; |
| 290 | |
| 291 | val = 0xfed00000 | 0x80; |
| 292 | pci_write_config_dword(cached_dev, 0x68, val); |
| 293 | |
| 294 | pci_read_config_dword(cached_dev, 0x68, &val); |
| 295 | if (val & 0x80) |
| 296 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); |
| 297 | else |
| 298 | BUG(); |
| 299 | } |
| 300 | |
| 301 | static void vt8237_force_enable_hpet(struct pci_dev *dev) |
| 302 | { |
| 303 | u32 uninitialized_var(val); |
| 304 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 305 | if (hpet_address || force_hpet_address) |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 306 | return; |
| 307 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 308 | if (!hpet_force_user) { |
| 309 | hpet_print_force_info(); |
| 310 | return; |
| 311 | } |
| 312 | |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 313 | pci_read_config_dword(dev, 0x68, &val); |
| 314 | /* |
| 315 | * Bit 7 is HPET enable bit. |
| 316 | * Bit 31:10 is HPET base address (contrary to what datasheet claims) |
| 317 | */ |
| 318 | if (val & 0x80) { |
| 319 | force_hpet_address = (val & ~0x3ff); |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 320 | dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n", |
| 321 | force_hpet_address); |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 322 | return; |
| 323 | } |
| 324 | |
| 325 | /* |
| 326 | * HPET is disabled. Trying enabling at FED00000 and check |
| 327 | * whether it sticks |
| 328 | */ |
| 329 | val = 0xfed00000 | 0x80; |
| 330 | pci_write_config_dword(dev, 0x68, val); |
| 331 | |
| 332 | pci_read_config_dword(dev, 0x68, &val); |
| 333 | if (val & 0x80) { |
| 334 | force_hpet_address = (val & ~0x3ff); |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 335 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at " |
| 336 | "0x%lx\n", force_hpet_address); |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 337 | cached_dev = dev; |
| 338 | force_hpet_resume_type = VT8237_FORCE_HPET_RESUME; |
| 339 | return; |
| 340 | } |
| 341 | |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 342 | dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n"); |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 343 | } |
| 344 | |
| 345 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, |
| 346 | vt8237_force_enable_hpet); |
| 347 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, |
| 348 | vt8237_force_enable_hpet); |
| 349 | |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 350 | static void ati_force_hpet_resume(void) |
| 351 | { |
| 352 | pci_write_config_dword(cached_dev, 0x14, 0xfed00000); |
| 353 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); |
| 354 | } |
| 355 | |
Andreas Herrmann | e7250b8 | 2008-09-05 18:33:26 +0200 | [diff] [blame] | 356 | static u32 ati_ixp4x0_rev(struct pci_dev *dev) |
| 357 | { |
| 358 | u32 d; |
| 359 | u8 b; |
| 360 | |
| 361 | pci_read_config_byte(dev, 0xac, &b); |
| 362 | b &= ~(1<<5); |
| 363 | pci_write_config_byte(dev, 0xac, b); |
| 364 | pci_read_config_dword(dev, 0x70, &d); |
| 365 | d |= 1<<8; |
| 366 | pci_write_config_dword(dev, 0x70, d); |
| 367 | pci_read_config_dword(dev, 0x8, &d); |
| 368 | d &= 0xff; |
| 369 | dev_printk(KERN_DEBUG, &dev->dev, "SB4X0 revision 0x%x\n", d); |
| 370 | return d; |
| 371 | } |
| 372 | |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 373 | static void ati_force_enable_hpet(struct pci_dev *dev) |
| 374 | { |
Andreas Herrmann | e7250b8 | 2008-09-05 18:33:26 +0200 | [diff] [blame] | 375 | u32 d, val; |
| 376 | u8 b; |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 377 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 378 | if (hpet_address || force_hpet_address) |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 379 | return; |
| 380 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 381 | if (!hpet_force_user) { |
| 382 | hpet_print_force_info(); |
| 383 | return; |
| 384 | } |
| 385 | |
Andreas Herrmann | e7250b8 | 2008-09-05 18:33:26 +0200 | [diff] [blame] | 386 | d = ati_ixp4x0_rev(dev); |
| 387 | if (d < 0x82) |
| 388 | return; |
| 389 | |
| 390 | /* base address */ |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 391 | pci_write_config_dword(dev, 0x14, 0xfed00000); |
| 392 | pci_read_config_dword(dev, 0x14, &val); |
Andreas Herrmann | e7250b8 | 2008-09-05 18:33:26 +0200 | [diff] [blame] | 393 | |
| 394 | /* enable interrupt */ |
| 395 | outb(0x72, 0xcd6); b = inb(0xcd7); |
| 396 | b |= 0x1; |
| 397 | outb(0x72, 0xcd6); outb(b, 0xcd7); |
| 398 | outb(0x72, 0xcd6); b = inb(0xcd7); |
| 399 | if (!(b & 0x1)) |
| 400 | return; |
| 401 | pci_read_config_dword(dev, 0x64, &d); |
| 402 | d |= (1<<10); |
| 403 | pci_write_config_dword(dev, 0x64, d); |
| 404 | pci_read_config_dword(dev, 0x64, &d); |
| 405 | if (!(d & (1<<10))) |
| 406 | return; |
| 407 | |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 408 | force_hpet_address = val; |
| 409 | force_hpet_resume_type = ATI_FORCE_HPET_RESUME; |
| 410 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n", |
| 411 | force_hpet_address); |
| 412 | cached_dev = dev; |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 413 | } |
| 414 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS, |
| 415 | ati_force_enable_hpet); |
| 416 | |
Carlos Corbacho | d79a5f8 | 2007-10-19 18:51:27 +0100 | [diff] [blame] | 417 | /* |
| 418 | * Undocumented chipset feature taken from LinuxBIOS. |
| 419 | */ |
| 420 | static void nvidia_force_hpet_resume(void) |
| 421 | { |
| 422 | pci_write_config_dword(cached_dev, 0x44, 0xfed00001); |
| 423 | printk(KERN_DEBUG "Force enabled HPET at resume\n"); |
| 424 | } |
| 425 | |
| 426 | static void nvidia_force_enable_hpet(struct pci_dev *dev) |
| 427 | { |
| 428 | u32 uninitialized_var(val); |
| 429 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 430 | if (hpet_address || force_hpet_address) |
Carlos Corbacho | d79a5f8 | 2007-10-19 18:51:27 +0100 | [diff] [blame] | 431 | return; |
| 432 | |
Thomas Gleixner | 7c4728f | 2008-05-10 21:42:14 +0200 | [diff] [blame] | 433 | if (!hpet_force_user) { |
| 434 | hpet_print_force_info(); |
| 435 | return; |
| 436 | } |
| 437 | |
Carlos Corbacho | d79a5f8 | 2007-10-19 18:51:27 +0100 | [diff] [blame] | 438 | pci_write_config_dword(dev, 0x44, 0xfed00001); |
| 439 | pci_read_config_dword(dev, 0x44, &val); |
| 440 | force_hpet_address = val & 0xfffffffe; |
| 441 | force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME; |
bjorn.helgaas@hp.com | 9ed8855 | 2007-12-17 14:09:40 -0700 | [diff] [blame] | 442 | dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n", |
Carlos Corbacho | d79a5f8 | 2007-10-19 18:51:27 +0100 | [diff] [blame] | 443 | force_hpet_address); |
| 444 | cached_dev = dev; |
| 445 | return; |
| 446 | } |
| 447 | |
| 448 | /* ISA Bridges */ |
| 449 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050, |
| 450 | nvidia_force_enable_hpet); |
| 451 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051, |
| 452 | nvidia_force_enable_hpet); |
Udo A. Steinberg | b196884 | 2007-10-19 20:35:02 +0200 | [diff] [blame] | 453 | |
Carlos Corbacho | 1b82ba6 | 2007-10-19 19:34:15 +0100 | [diff] [blame] | 454 | /* LPC bridges */ |
Zbigniew Luszpinski | 96bcf45 | 2008-03-19 15:51:50 +0100 | [diff] [blame] | 455 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260, |
| 456 | nvidia_force_enable_hpet); |
Carlos Corbacho | 1b82ba6 | 2007-10-19 19:34:15 +0100 | [diff] [blame] | 457 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360, |
| 458 | nvidia_force_enable_hpet); |
| 459 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361, |
| 460 | nvidia_force_enable_hpet); |
| 461 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362, |
| 462 | nvidia_force_enable_hpet); |
| 463 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363, |
| 464 | nvidia_force_enable_hpet); |
| 465 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364, |
| 466 | nvidia_force_enable_hpet); |
| 467 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365, |
| 468 | nvidia_force_enable_hpet); |
| 469 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366, |
| 470 | nvidia_force_enable_hpet); |
| 471 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367, |
| 472 | nvidia_force_enable_hpet); |
| 473 | |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 474 | void force_hpet_resume(void) |
| 475 | { |
| 476 | switch (force_hpet_resume_type) { |
Harvey Harrison | 4a5a77d | 2008-02-06 22:39:44 +0100 | [diff] [blame] | 477 | case ICH_FORCE_HPET_RESUME: |
| 478 | ich_force_hpet_resume(); |
| 479 | return; |
| 480 | case OLD_ICH_FORCE_HPET_RESUME: |
| 481 | old_ich_force_hpet_resume(); |
| 482 | return; |
| 483 | case VT8237_FORCE_HPET_RESUME: |
| 484 | vt8237_force_hpet_resume(); |
| 485 | return; |
| 486 | case NVIDIA_FORCE_HPET_RESUME: |
| 487 | nvidia_force_hpet_resume(); |
| 488 | return; |
Andreas Herrmann | e8aa466 | 2008-05-09 11:49:11 +0200 | [diff] [blame] | 489 | case ATI_FORCE_HPET_RESUME: |
| 490 | ati_force_hpet_resume(); |
| 491 | return; |
Harvey Harrison | 4a5a77d | 2008-02-06 22:39:44 +0100 | [diff] [blame] | 492 | default: |
Venki Pallipadi | bfe0c1c | 2007-10-12 23:04:24 +0200 | [diff] [blame] | 493 | break; |
| 494 | } |
| 495 | } |
| 496 | |
Venki Pallipadi | d54bd57 | 2007-10-12 23:04:23 +0200 | [diff] [blame] | 497 | #endif |