Andy Walls | b152642 | 2008-08-30 16:03:44 -0300 | [diff] [blame] | 1 | /* |
| 2 | * cx18 driver PCI memory mapped IO access routines |
| 3 | * |
| 4 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> |
| 5 | * Copyright (C) 2008 Andy Walls <awalls@radix.net> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 20 | * 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include "cx18-driver.h" |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 24 | #include "cx18-io.h" |
Andy Walls | b152642 | 2008-08-30 16:03:44 -0300 | [diff] [blame] | 25 | #include "cx18-irq.h" |
| 26 | |
Andy Walls | d267d85 | 2008-09-28 21:46:02 -0300 | [diff] [blame] | 27 | void cx18_log_statistics(struct cx18 *cx) |
| 28 | { |
| 29 | int i; |
| 30 | |
| 31 | if (!(cx18_debug & CX18_DBGFLG_INFO)) |
| 32 | return; |
| 33 | |
| 34 | for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++) |
| 35 | CX18_DEBUG_INFO("retried_write[%d] = %d\n", i, |
| 36 | atomic_read(&cx->mmio_stats.retried_write[i])); |
| 37 | for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++) |
| 38 | CX18_DEBUG_INFO("retried_read[%d] = %d\n", i, |
| 39 | atomic_read(&cx->mmio_stats.retried_read[i])); |
| 40 | return; |
| 41 | } |
| 42 | |
| 43 | void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr) |
| 44 | { |
| 45 | int i; |
| 46 | for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { |
| 47 | cx18_raw_writel_noretry(cx, val, addr); |
| 48 | if (val == cx18_raw_readl_noretry(cx, addr)) |
| 49 | break; |
| 50 | } |
| 51 | cx18_log_write_retries(cx, i, addr); |
| 52 | } |
| 53 | |
| 54 | u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr) |
| 55 | { |
| 56 | int i; |
| 57 | u32 val; |
| 58 | for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { |
| 59 | val = cx18_raw_readl_noretry(cx, addr); |
| 60 | if (val != 0xffffffff) /* PCI bus read error */ |
| 61 | break; |
| 62 | } |
| 63 | cx18_log_read_retries(cx, i, addr); |
| 64 | return val; |
| 65 | } |
| 66 | |
| 67 | u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr) |
| 68 | { |
| 69 | int i; |
| 70 | u16 val; |
| 71 | for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { |
| 72 | val = cx18_raw_readw_noretry(cx, addr); |
| 73 | if (val != 0xffff) /* PCI bus read error */ |
| 74 | break; |
| 75 | } |
| 76 | cx18_log_read_retries(cx, i, addr); |
| 77 | return val; |
| 78 | } |
| 79 | |
| 80 | void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr) |
| 81 | { |
| 82 | int i; |
| 83 | for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { |
| 84 | cx18_writel_noretry(cx, val, addr); |
| 85 | if (val == cx18_readl_noretry(cx, addr)) |
| 86 | break; |
| 87 | } |
| 88 | cx18_log_write_retries(cx, i, addr); |
| 89 | } |
| 90 | |
| 91 | void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr) |
| 92 | { |
| 93 | int i; |
| 94 | for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { |
| 95 | cx18_writew_noretry(cx, val, addr); |
| 96 | if (val == cx18_readw_noretry(cx, addr)) |
| 97 | break; |
| 98 | } |
| 99 | cx18_log_write_retries(cx, i, addr); |
| 100 | } |
| 101 | |
| 102 | void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr) |
| 103 | { |
| 104 | int i; |
| 105 | for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { |
| 106 | cx18_writeb_noretry(cx, val, addr); |
| 107 | if (val == cx18_readb_noretry(cx, addr)) |
| 108 | break; |
| 109 | } |
| 110 | cx18_log_write_retries(cx, i, addr); |
| 111 | } |
| 112 | |
| 113 | u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr) |
| 114 | { |
| 115 | int i; |
| 116 | u32 val; |
| 117 | for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { |
| 118 | val = cx18_readl_noretry(cx, addr); |
| 119 | if (val != 0xffffffff) /* PCI bus read error */ |
| 120 | break; |
| 121 | } |
| 122 | cx18_log_read_retries(cx, i, addr); |
| 123 | return val; |
| 124 | } |
| 125 | |
| 126 | u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr) |
| 127 | { |
| 128 | int i; |
| 129 | u16 val; |
| 130 | for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { |
| 131 | val = cx18_readw_noretry(cx, addr); |
| 132 | if (val != 0xffff) /* PCI bus read error */ |
| 133 | break; |
| 134 | } |
| 135 | cx18_log_read_retries(cx, i, addr); |
| 136 | return val; |
| 137 | } |
| 138 | |
| 139 | u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr) |
| 140 | { |
| 141 | int i; |
| 142 | u8 val; |
| 143 | for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { |
| 144 | val = cx18_readb_noretry(cx, addr); |
| 145 | if (val != 0xff) /* PCI bus read error */ |
| 146 | break; |
| 147 | } |
| 148 | cx18_log_read_retries(cx, i, addr); |
| 149 | return val; |
| 150 | } |
| 151 | |
Andy Walls | b152642 | 2008-08-30 16:03:44 -0300 | [diff] [blame] | 152 | void cx18_memcpy_fromio(struct cx18 *cx, void *to, |
| 153 | const void __iomem *from, unsigned int len) |
| 154 | { |
Hans Verkuil | 2796073 | 2008-09-06 14:02:43 -0300 | [diff] [blame] | 155 | const u8 __iomem *src = from; |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 156 | u8 *dst = to; |
| 157 | |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 158 | /* Align reads on the CX23418's addresses */ |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 159 | if ((len > 0) && ((unsigned long) src & 1)) { |
| 160 | *dst = cx18_readb(cx, src); |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 161 | len--; |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 162 | dst++; |
| 163 | src++; |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 164 | } |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 165 | if ((len > 1) && ((unsigned long) src & 2)) { |
| 166 | *((u16 *)dst) = cx18_raw_readw(cx, src); |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 167 | len -= 2; |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 168 | dst += 2; |
| 169 | src += 2; |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 170 | } |
| 171 | while (len > 3) { |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 172 | *((u32 *)dst) = cx18_raw_readl(cx, src); |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 173 | len -= 4; |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 174 | dst += 4; |
| 175 | src += 4; |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 176 | } |
| 177 | if (len > 1) { |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 178 | *((u16 *)dst) = cx18_raw_readw(cx, src); |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 179 | len -= 2; |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 180 | dst += 2; |
| 181 | src += 2; |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 182 | } |
| 183 | if (len > 0) |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 184 | *dst = cx18_readb(cx, src); |
Andy Walls | b152642 | 2008-08-30 16:03:44 -0300 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count) |
| 188 | { |
Hans Verkuil | 2796073 | 2008-09-06 14:02:43 -0300 | [diff] [blame] | 189 | u8 __iomem *dst = addr; |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 190 | u16 val2 = val | (val << 8); |
| 191 | u32 val4 = val2 | (val2 << 16); |
| 192 | |
| 193 | /* Align writes on the CX23418's addresses */ |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 194 | if ((count > 0) && ((unsigned long)dst & 1)) { |
| 195 | cx18_writeb(cx, (u8) val, dst); |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 196 | count--; |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 197 | dst++; |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 198 | } |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 199 | if ((count > 1) && ((unsigned long)dst & 2)) { |
| 200 | cx18_writew(cx, val2, dst); |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 201 | count -= 2; |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 202 | dst += 2; |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 203 | } |
| 204 | while (count > 3) { |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 205 | cx18_writel(cx, val4, dst); |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 206 | count -= 4; |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 207 | dst += 4; |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 208 | } |
| 209 | if (count > 1) { |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 210 | cx18_writew(cx, val2, dst); |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 211 | count -= 2; |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 212 | dst += 2; |
Andy Walls | c641d09 | 2008-09-01 00:40:41 -0300 | [diff] [blame] | 213 | } |
| 214 | if (count > 0) |
Andy Walls | ac2b97b | 2008-09-04 13:16:40 -0300 | [diff] [blame] | 215 | cx18_writeb(cx, (u8) val, dst); |
Andy Walls | b152642 | 2008-08-30 16:03:44 -0300 | [diff] [blame] | 216 | } |
| 217 | |
| 218 | void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) |
| 219 | { |
| 220 | u32 r; |
| 221 | cx18_write_reg(cx, val, SW1_INT_STATUS); |
| 222 | r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); |
| 223 | cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI); |
| 224 | } |
| 225 | |
| 226 | void cx18_sw1_irq_disable(struct cx18 *cx, u32 val) |
| 227 | { |
| 228 | u32 r; |
| 229 | r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); |
| 230 | cx18_write_reg(cx, r & ~val, SW1_INT_ENABLE_PCI); |
| 231 | } |
| 232 | |
| 233 | void cx18_sw2_irq_enable(struct cx18 *cx, u32 val) |
| 234 | { |
| 235 | u32 r; |
| 236 | cx18_write_reg(cx, val, SW2_INT_STATUS); |
| 237 | r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); |
| 238 | cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI); |
| 239 | } |
| 240 | |
| 241 | void cx18_sw2_irq_disable(struct cx18 *cx, u32 val) |
| 242 | { |
| 243 | u32 r; |
| 244 | r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); |
| 245 | cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_PCI); |
| 246 | } |
| 247 | |
| 248 | void cx18_setup_page(struct cx18 *cx, u32 addr) |
| 249 | { |
| 250 | u32 val; |
| 251 | val = cx18_read_reg(cx, 0xD000F8); |
| 252 | val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00); |
| 253 | cx18_write_reg(cx, val, 0xD000F8); |
| 254 | } |