Andy Walls | b152642 | 2008-08-30 16:03:44 -0300 | [diff] [blame^] | 1 | /* |
| 2 | * cx18 driver PCI memory mapped IO access routines |
| 3 | * |
| 4 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> |
| 5 | * Copyright (C) 2008 Andy Walls <awalls@radix.net> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 20 | * 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include "cx18-driver.h" |
| 24 | #include "cx18-irq.h" |
| 25 | |
| 26 | void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr) |
| 27 | { |
| 28 | __raw_writel(val, addr); |
| 29 | } |
| 30 | |
| 31 | u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr) |
| 32 | { |
| 33 | return __raw_readl(addr); |
| 34 | } |
| 35 | |
| 36 | u32 cx18_write_sync(struct cx18 *cx, u32 val, void __iomem *addr) |
| 37 | { |
| 38 | writel(val, addr); |
| 39 | return readl(addr); |
| 40 | } |
| 41 | |
| 42 | void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr) |
| 43 | { |
| 44 | writel(val, addr); |
| 45 | } |
| 46 | |
| 47 | u32 cx18_readl(struct cx18 *cx, const void __iomem *addr) |
| 48 | { |
| 49 | return readl(addr); |
| 50 | } |
| 51 | |
| 52 | |
| 53 | /* Access "register" region of CX23418 memory mapped I/O */ |
| 54 | u32 cx18_read_reg(struct cx18 *cx, u32 reg) |
| 55 | { |
| 56 | return readl(cx->reg_mem + reg); |
| 57 | } |
| 58 | |
| 59 | void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg) |
| 60 | { |
| 61 | writel(val, cx->reg_mem + reg); |
| 62 | } |
| 63 | |
| 64 | u32 cx18_write_reg_sync(struct cx18 *cx, u32 val, u32 reg) |
| 65 | { |
| 66 | return cx18_write_sync(cx, val, cx->reg_mem + reg); |
| 67 | } |
| 68 | |
| 69 | /* Access "encoder memory" region of CX23418 memory mapped I/O */ |
| 70 | u32 cx18_read_enc(struct cx18 *cx, u32 addr) |
| 71 | { |
| 72 | return readl(cx->enc_mem + addr); |
| 73 | } |
| 74 | |
| 75 | void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr) |
| 76 | { |
| 77 | writel(val, cx->enc_mem + addr); |
| 78 | } |
| 79 | |
| 80 | u32 cx18_write_enc_sync(struct cx18 *cx, u32 val, u32 addr) |
| 81 | { |
| 82 | return cx18_write_sync(cx, val, cx->enc_mem + addr); |
| 83 | } |
| 84 | |
| 85 | void cx18_memcpy_fromio(struct cx18 *cx, void *to, |
| 86 | const void __iomem *from, unsigned int len) |
| 87 | { |
| 88 | memcpy_fromio(to, from, len); |
| 89 | } |
| 90 | |
| 91 | void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count) |
| 92 | { |
| 93 | memset_io(addr, val, count); |
| 94 | } |
| 95 | |
| 96 | void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) |
| 97 | { |
| 98 | u32 r; |
| 99 | cx18_write_reg(cx, val, SW1_INT_STATUS); |
| 100 | r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); |
| 101 | cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI); |
| 102 | } |
| 103 | |
| 104 | void cx18_sw1_irq_disable(struct cx18 *cx, u32 val) |
| 105 | { |
| 106 | u32 r; |
| 107 | r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); |
| 108 | cx18_write_reg(cx, r & ~val, SW1_INT_ENABLE_PCI); |
| 109 | } |
| 110 | |
| 111 | void cx18_sw2_irq_enable(struct cx18 *cx, u32 val) |
| 112 | { |
| 113 | u32 r; |
| 114 | cx18_write_reg(cx, val, SW2_INT_STATUS); |
| 115 | r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); |
| 116 | cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI); |
| 117 | } |
| 118 | |
| 119 | void cx18_sw2_irq_disable(struct cx18 *cx, u32 val) |
| 120 | { |
| 121 | u32 r; |
| 122 | r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); |
| 123 | cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_PCI); |
| 124 | } |
| 125 | |
| 126 | void cx18_setup_page(struct cx18 *cx, u32 addr) |
| 127 | { |
| 128 | u32 val; |
| 129 | val = cx18_read_reg(cx, 0xD000F8); |
| 130 | val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00); |
| 131 | cx18_write_reg(cx, val, 0xD000F8); |
| 132 | } |
| 133 | |
| 134 | /* Tries to recover from the CX23418 responding improperly on the PCI bus */ |
| 135 | int cx18_pci_try_recover(struct cx18 *cx) |
| 136 | { |
| 137 | u16 status; |
| 138 | |
| 139 | pci_read_config_word(cx->dev, PCI_STATUS, &status); |
| 140 | pci_write_config_word(cx->dev, PCI_STATUS, status); |
| 141 | return 0; |
| 142 | } |