blob: 3a32deda765dab3487e1174467f923ceede19fc6 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
3 * IBM Corp.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +100011#undef DEBUG
Linus Torvalds1da177e2005-04-16 15:20:36 -070012
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include <linux/string.h>
17#include <linux/init.h>
18#include <linux/bootmem.h>
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +100019#include <linux/irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
21#include <asm/sections.h>
22#include <asm/io.h>
23#include <asm/prom.h>
24#include <asm/pci-bridge.h>
25#include <asm/machdep.h>
26#include <asm/iommu.h>
Stephen Rothwelld3878992005-09-28 02:50:25 +100027#include <asm/ppc-pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Paul Mackerras0cb7b2a2005-10-29 22:07:56 +100029#include "maple.h"
30
Linus Torvalds1da177e2005-04-16 15:20:36 -070031#ifdef DEBUG
32#define DBG(x...) printk(x)
33#else
34#define DBG(x...)
35#endif
36
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +100037static struct pci_controller *u3_agp, *u3_ht, *u4_pcie;
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
39static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
40{
41 for (; node != 0;node = node->sibling) {
Jeremy Kerreeb2b722006-07-12 15:40:17 +100042 const int *bus_range;
43 const unsigned int *class_code;
Linus Torvalds1da177e2005-04-16 15:20:36 -070044 int len;
45
46 /* For PCI<->PCI bridges or CardBus bridges, we go down */
Jeremy Kerreeb2b722006-07-12 15:40:17 +100047 class_code = get_property(node, "class-code", NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -070048 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
49 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
50 continue;
Jeremy Kerreeb2b722006-07-12 15:40:17 +100051 bus_range = get_property(node, "bus-range", &len);
Linus Torvalds1da177e2005-04-16 15:20:36 -070052 if (bus_range != NULL && len > 2 * sizeof(int)) {
53 if (bus_range[1] > higher)
54 higher = bus_range[1];
55 }
56 higher = fixup_one_level_bus_range(node->child, higher);
57 }
58 return higher;
59}
60
61/* This routine fixes the "bus-range" property of all bridges in the
62 * system since they tend to have their "last" member wrong on macs
63 *
64 * Note that the bus numbers manipulated here are OF bus numbers, they
65 * are not Linux bus numbers.
66 */
67static void __init fixup_bus_range(struct device_node *bridge)
68{
Jeremy Kerreeb2b722006-07-12 15:40:17 +100069 int *bus_range;
70 struct property *prop;
Linus Torvalds1da177e2005-04-16 15:20:36 -070071 int len;
72
73 /* Lookup the "bus-range" property for the hose */
Jeremy Kerreeb2b722006-07-12 15:40:17 +100074 prop = of_find_property(bridge, "bus-range", &len);
75 if (prop == NULL || prop->value == NULL || len < 2 * sizeof(int)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 printk(KERN_WARNING "Can't get bus-range for %s\n",
77 bridge->full_name);
78 return;
79 }
Jeremy Kerreeb2b722006-07-12 15:40:17 +100080 bus_range = (int *)prop->value;
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
82}
83
84
Nathan Lynchcc9881c2006-09-21 14:31:13 -050085static unsigned long u3_agp_cfa0(u8 devfn, u8 off)
86{
87 return (1 << (unsigned long)PCI_SLOT(devfn)) |
88 ((unsigned long)PCI_FUNC(devfn) << 8) |
89 ((unsigned long)off & 0xFCUL);
90}
Linus Torvalds1da177e2005-04-16 15:20:36 -070091
Nathan Lynchcc9881c2006-09-21 14:31:13 -050092static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off)
93{
94 return ((unsigned long)bus << 16) |
95 ((unsigned long)devfn << 8) |
96 ((unsigned long)off & 0xFCUL) |
97 1UL;
98}
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
Al Viro8c42ec22006-09-23 01:37:41 +0100100static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101 u8 bus, u8 dev_fn, u8 offset)
102{
103 unsigned int caddr;
104
105 if (bus == hose->first_busno) {
106 if (dev_fn < (11 << 3))
Al Viro8c42ec22006-09-23 01:37:41 +0100107 return NULL;
Nathan Lynchcc9881c2006-09-21 14:31:13 -0500108 caddr = u3_agp_cfa0(dev_fn, offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 } else
Nathan Lynchcc9881c2006-09-21 14:31:13 -0500110 caddr = u3_agp_cfa1(bus, dev_fn, offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111
112 /* Uninorth will return garbage if we don't read back the value ! */
113 do {
114 out_le32(hose->cfg_addr, caddr);
115 } while (in_le32(hose->cfg_addr) != caddr);
116
117 offset &= 0x07;
Al Viro8c42ec22006-09-23 01:37:41 +0100118 return hose->cfg_data + offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119}
120
121static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
122 int offset, int len, u32 *val)
123{
124 struct pci_controller *hose;
Al Viro8c42ec22006-09-23 01:37:41 +0100125 volatile void __iomem *addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126
127 hose = pci_bus_to_host(bus);
128 if (hose == NULL)
129 return PCIBIOS_DEVICE_NOT_FOUND;
130
131 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
132 if (!addr)
133 return PCIBIOS_DEVICE_NOT_FOUND;
134 /*
135 * Note: the caller has already checked that offset is
136 * suitably aligned and that len is 1, 2 or 4.
137 */
138 switch (len) {
139 case 1:
Al Viro8c42ec22006-09-23 01:37:41 +0100140 *val = in_8(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141 break;
142 case 2:
Al Viro8c42ec22006-09-23 01:37:41 +0100143 *val = in_le16(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144 break;
145 default:
Al Viro8c42ec22006-09-23 01:37:41 +0100146 *val = in_le32(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 break;
148 }
149 return PCIBIOS_SUCCESSFUL;
150}
151
152static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
153 int offset, int len, u32 val)
154{
155 struct pci_controller *hose;
Al Viro8c42ec22006-09-23 01:37:41 +0100156 volatile void __iomem *addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157
158 hose = pci_bus_to_host(bus);
159 if (hose == NULL)
160 return PCIBIOS_DEVICE_NOT_FOUND;
161
162 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
163 if (!addr)
164 return PCIBIOS_DEVICE_NOT_FOUND;
165 /*
166 * Note: the caller has already checked that offset is
167 * suitably aligned and that len is 1, 2 or 4.
168 */
169 switch (len) {
170 case 1:
Al Viro8c42ec22006-09-23 01:37:41 +0100171 out_8(addr, val);
172 (void) in_8(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173 break;
174 case 2:
Al Viro8c42ec22006-09-23 01:37:41 +0100175 out_le16(addr, val);
176 (void) in_le16(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177 break;
178 default:
Al Viro8c42ec22006-09-23 01:37:41 +0100179 out_le32(addr, val);
180 (void) in_le32(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 break;
182 }
183 return PCIBIOS_SUCCESSFUL;
184}
185
186static struct pci_ops u3_agp_pci_ops =
187{
188 u3_agp_read_config,
189 u3_agp_write_config
190};
191
Nathan Lynchcc9881c2006-09-21 14:31:13 -0500192static unsigned long u3_ht_cfa0(u8 devfn, u8 off)
193{
194 return (devfn << 8) | off;
195}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196
Nathan Lynchcc9881c2006-09-21 14:31:13 -0500197static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off)
198{
199 return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
200}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201
Al Viro8c42ec22006-09-23 01:37:41 +0100202static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 u8 bus, u8 devfn, u8 offset)
204{
205 if (bus == hose->first_busno) {
206 if (PCI_SLOT(devfn) == 0)
Al Viro8c42ec22006-09-23 01:37:41 +0100207 return NULL;
208 return hose->cfg_data + u3_ht_cfa0(devfn, offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209 } else
Al Viro8c42ec22006-09-23 01:37:41 +0100210 return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211}
212
213static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
214 int offset, int len, u32 *val)
215{
216 struct pci_controller *hose;
Al Viro8c42ec22006-09-23 01:37:41 +0100217 volatile void __iomem *addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218
219 hose = pci_bus_to_host(bus);
220 if (hose == NULL)
221 return PCIBIOS_DEVICE_NOT_FOUND;
222
Nathan Lynchd608df52006-09-21 14:25:34 -0500223 if (offset > 0xff)
224 return PCIBIOS_BAD_REGISTER_NUMBER;
225
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
227 if (!addr)
228 return PCIBIOS_DEVICE_NOT_FOUND;
229
230 /*
231 * Note: the caller has already checked that offset is
232 * suitably aligned and that len is 1, 2 or 4.
233 */
234 switch (len) {
235 case 1:
Al Viro8c42ec22006-09-23 01:37:41 +0100236 *val = in_8(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237 break;
238 case 2:
Al Viro8c42ec22006-09-23 01:37:41 +0100239 *val = in_le16(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240 break;
241 default:
Al Viro8c42ec22006-09-23 01:37:41 +0100242 *val = in_le32(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243 break;
244 }
245 return PCIBIOS_SUCCESSFUL;
246}
247
248static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
249 int offset, int len, u32 val)
250{
251 struct pci_controller *hose;
Al Viro8c42ec22006-09-23 01:37:41 +0100252 volatile void __iomem *addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253
254 hose = pci_bus_to_host(bus);
255 if (hose == NULL)
256 return PCIBIOS_DEVICE_NOT_FOUND;
257
Nathan Lynchd608df52006-09-21 14:25:34 -0500258 if (offset > 0xff)
259 return PCIBIOS_BAD_REGISTER_NUMBER;
260
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
262 if (!addr)
263 return PCIBIOS_DEVICE_NOT_FOUND;
264 /*
265 * Note: the caller has already checked that offset is
266 * suitably aligned and that len is 1, 2 or 4.
267 */
268 switch (len) {
269 case 1:
Al Viro8c42ec22006-09-23 01:37:41 +0100270 out_8(addr, val);
271 (void) in_8(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 break;
273 case 2:
Al Viro8c42ec22006-09-23 01:37:41 +0100274 out_le16(addr, val);
275 (void) in_le16(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276 break;
277 default:
Al Viro8c42ec22006-09-23 01:37:41 +0100278 out_le32(addr, val);
279 (void) in_le32(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 break;
281 }
282 return PCIBIOS_SUCCESSFUL;
283}
284
285static struct pci_ops u3_ht_pci_ops =
286{
287 u3_ht_read_config,
288 u3_ht_write_config
289};
290
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +1000291static unsigned int u4_pcie_cfa0(unsigned int devfn, unsigned int off)
292{
293 return (1 << PCI_SLOT(devfn)) |
294 (PCI_FUNC(devfn) << 8) |
295 ((off >> 8) << 28) |
296 (off & 0xfcu);
297}
298
299static unsigned int u4_pcie_cfa1(unsigned int bus, unsigned int devfn,
300 unsigned int off)
301{
302 return (bus << 16) |
303 (devfn << 8) |
304 ((off >> 8) << 28) |
305 (off & 0xfcu) | 1u;
306}
307
308static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
309 u8 bus, u8 dev_fn, int offset)
310{
311 unsigned int caddr;
312
313 if (bus == hose->first_busno)
314 caddr = u4_pcie_cfa0(dev_fn, offset);
315 else
316 caddr = u4_pcie_cfa1(bus, dev_fn, offset);
317
318 /* Uninorth will return garbage if we don't read back the value ! */
319 do {
320 out_le32(hose->cfg_addr, caddr);
321 } while (in_le32(hose->cfg_addr) != caddr);
322
323 offset &= 0x03;
324 return hose->cfg_data + offset;
325}
326
327static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
328 int offset, int len, u32 *val)
329{
330 struct pci_controller *hose;
331 volatile void __iomem *addr;
332
333 hose = pci_bus_to_host(bus);
334 if (hose == NULL)
335 return PCIBIOS_DEVICE_NOT_FOUND;
336 if (offset >= 0x1000)
337 return PCIBIOS_BAD_REGISTER_NUMBER;
338 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
339 if (!addr)
340 return PCIBIOS_DEVICE_NOT_FOUND;
341 /*
342 * Note: the caller has already checked that offset is
343 * suitably aligned and that len is 1, 2 or 4.
344 */
345 switch (len) {
346 case 1:
347 *val = in_8(addr);
348 break;
349 case 2:
350 *val = in_le16(addr);
351 break;
352 default:
353 *val = in_le32(addr);
354 break;
355 }
356 return PCIBIOS_SUCCESSFUL;
357}
358static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
359 int offset, int len, u32 val)
360{
361 struct pci_controller *hose;
362 volatile void __iomem *addr;
363
364 hose = pci_bus_to_host(bus);
365 if (hose == NULL)
366 return PCIBIOS_DEVICE_NOT_FOUND;
367 if (offset >= 0x1000)
368 return PCIBIOS_BAD_REGISTER_NUMBER;
369 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
370 if (!addr)
371 return PCIBIOS_DEVICE_NOT_FOUND;
372 /*
373 * Note: the caller has already checked that offset is
374 * suitably aligned and that len is 1, 2 or 4.
375 */
376 switch (len) {
377 case 1:
378 out_8(addr, val);
379 (void) in_8(addr);
380 break;
381 case 2:
382 out_le16(addr, val);
383 (void) in_le16(addr);
384 break;
385 default:
386 out_le32(addr, val);
387 (void) in_le32(addr);
388 break;
389 }
390 return PCIBIOS_SUCCESSFUL;
391}
392
393static struct pci_ops u4_pcie_pci_ops =
394{
395 u4_pcie_read_config,
396 u4_pcie_write_config
397};
398
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399static void __init setup_u3_agp(struct pci_controller* hose)
400{
401 /* On G5, we move AGP up to high bus number so we don't need
402 * to reassign bus numbers for HT. If we ever have P2P bridges
Paul Mackerras399fe2b2005-10-20 20:57:05 +1000403 * on AGP, we'll have to move pci_assign_all_buses to the
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404 * pci_controller structure so we enable it for AGP and not for
405 * HT childs.
406 * We hard code the address because of the different size of
407 * the reg address cell, we shall fix that by killing struct
408 * reg_property and using some accessor functions instead
409 */
Anton Blanchard3238e9c2005-09-12 13:14:26 +1000410 hose->first_busno = 0xf0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411 hose->last_busno = 0xff;
412 hose->ops = &u3_agp_pci_ops;
413 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
414 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
415
416 u3_agp = hose;
417}
418
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +1000419static void __init setup_u4_pcie(struct pci_controller* hose)
420{
421 /* We currently only implement the "non-atomic" config space, to
422 * be optimised later.
423 */
424 hose->ops = &u4_pcie_pci_ops;
425 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
426 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
427
428 /* The bus contains a bridge from root -> device, we need to
429 * make it visible on bus 0 so that we pick the right type
430 * of config cycles. If we didn't, we would have to force all
431 * config cycles to be type 1. So we override the "bus-range"
432 * property here
433 */
434 hose->first_busno = 0x00;
435 hose->last_busno = 0xff;
436 u4_pcie = hose;
437}
438
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439static void __init setup_u3_ht(struct pci_controller* hose)
440{
441 hose->ops = &u3_ht_pci_ops;
442
443 /* We hard code the address because of the different size of
444 * the reg address cell, we shall fix that by killing struct
445 * reg_property and using some accessor functions instead
446 */
Al Viro8c42ec22006-09-23 01:37:41 +0100447 hose->cfg_data = ioremap(0xf2000000, 0x02000000);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448
449 hose->first_busno = 0;
450 hose->last_busno = 0xef;
451
452 u3_ht = hose;
453}
454
455static int __init add_bridge(struct device_node *dev)
456{
457 int len;
458 struct pci_controller *hose;
459 char* disp_name;
Jeremy Kerreeb2b722006-07-12 15:40:17 +1000460 const int *bus_range;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700461 int primary = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462
463 DBG("Adding PCI host bridge %s\n", dev->full_name);
464
Jeremy Kerreeb2b722006-07-12 15:40:17 +1000465 bus_range = get_property(dev, "bus-range", &len);
Anton Blanchard3238e9c2005-09-12 13:14:26 +1000466 if (bus_range == NULL || len < 2 * sizeof(int)) {
467 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
468 dev->full_name);
469 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470
Benjamin Herrenschmidtb5166cc2005-11-15 16:05:33 +1100471 hose = pcibios_alloc_controller(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700472 if (hose == NULL)
473 return -ENOMEM;
Anton Blanchard3238e9c2005-09-12 13:14:26 +1000474 hose->first_busno = bus_range ? bus_range[0] : 0;
475 hose->last_busno = bus_range ? bus_range[1] : 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477 disp_name = NULL;
Anton Blanchard3238e9c2005-09-12 13:14:26 +1000478 if (device_is_compatible(dev, "u3-agp")) {
479 setup_u3_agp(hose);
480 disp_name = "U3-AGP";
481 primary = 0;
482 } else if (device_is_compatible(dev, "u3-ht")) {
483 setup_u3_ht(hose);
484 disp_name = "U3-HT";
485 primary = 1;
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +1000486 } else if (device_is_compatible(dev, "u4-pcie")) {
487 setup_u4_pcie(hose);
488 disp_name = "U4-PCIE";
489 primary = 0;
Anton Blanchard3238e9c2005-09-12 13:14:26 +1000490 }
491 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
492 disp_name, hose->first_busno, hose->last_busno);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493
Anton Blanchard3238e9c2005-09-12 13:14:26 +1000494 /* Interpret the "ranges" property */
495 /* This also maps the I/O region and sets isa_io/mem_base */
Paul Mackerrasf7abbc12005-10-22 15:03:21 +1000496 pci_process_bridge_OF_ranges(hose, dev, primary);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497
Anton Blanchard3238e9c2005-09-12 13:14:26 +1000498 /* Fixup "bus-range" OF property */
499 fixup_bus_range(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500
501 return 0;
502}
503
504
Benjamin Herrenschmidtf90bb152006-11-11 17:24:51 +1100505void __devinit maple_pci_irq_fixup(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506{
Benjamin Herrenschmidtf90bb152006-11-11 17:24:51 +1100507 DBG(" -> maple_pci_irq_fixup\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508
Benjamin Herrenschmidtf90bb152006-11-11 17:24:51 +1100509 /* Fixup IRQ for PCIe host */
510 if (u4_pcie != NULL && dev->bus->number == 0 &&
511 pci_bus_to_host(dev->bus) == u4_pcie) {
512 printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n");
513 dev->irq = irq_create_mapping(NULL, 1);
514 if (dev->irq != NO_IRQ)
515 set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +1000516 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517
Benjamin Herrenschmidtf90bb152006-11-11 17:24:51 +1100518 /* Hide AMD8111 IDE interrupt when in legacy mode so
519 * the driver calls pci_get_legacy_ide_irq()
520 */
521 if (dev->vendor == PCI_VENDOR_ID_AMD &&
522 dev->device == PCI_DEVICE_ID_AMD_8111_IDE &&
523 (dev->class & 5) != 5) {
524 dev->irq = NO_IRQ;
525 }
526
527 DBG(" <- maple_pci_irq_fixup\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528}
529
530static void __init maple_fixup_phb_resources(void)
531{
532 struct pci_controller *hose, *tmp;
533
534 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
535 unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +1000536
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 hose->io_resource.start += offset;
538 hose->io_resource.end += offset;
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +1000539
Greg Kroah-Hartman685143a2006-06-12 15:18:31 -0700540 printk(KERN_INFO "PCI Host %d, io start: %llx; io end: %llx\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541 hose->global_number,
Greg Kroah-Hartman685143a2006-06-12 15:18:31 -0700542 (unsigned long long)hose->io_resource.start,
543 (unsigned long long)hose->io_resource.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544 }
545}
546
547void __init maple_pci_init(void)
548{
549 struct device_node *np, *root;
550 struct device_node *ht = NULL;
551
552 /* Probe root PCI hosts, that is on U3 the AGP host and the
553 * HyperTransport host. That one is actually "kept" around
554 * and actually added last as it's resource management relies
555 * on the AGP resources to have been setup first
556 */
557 root = of_find_node_by_path("/");
558 if (root == NULL) {
559 printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n");
560 return;
561 }
562 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
563 if (np->name == NULL)
564 continue;
565 if (strcmp(np->name, "pci") == 0) {
566 if (add_bridge(np) == 0)
567 of_node_get(np);
568 }
569 if (strcmp(np->name, "ht") == 0) {
570 of_node_get(np);
571 ht = np;
572 }
573 }
574 of_node_put(root);
575
576 /* Now setup the HyperTransport host if we found any
577 */
578 if (ht && add_bridge(ht) != 0)
579 of_node_put(ht);
580
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +1000581 /*
582 * We need to call pci_setup_phb_io for the HT bridge first
583 * so it gets the I/O port numbers starting at 0, and we
584 * need to call it for the AGP bridge after that so it gets
585 * small positive I/O port numbers.
586 */
587 if (u3_ht)
588 pci_setup_phb_io(u3_ht, 1);
589 if (u3_agp)
590 pci_setup_phb_io(u3_agp, 0);
591 if (u4_pcie)
592 pci_setup_phb_io(u4_pcie, 0);
593
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594 /* Fixup the IO resources on our host bridges as the common code
595 * does it only for childs of the host bridges
596 */
597 maple_fixup_phb_resources();
598
599 /* Setup the linkage between OF nodes and PHBs */
600 pci_devs_phb_init();
601
602 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
603 * assume there is no P2P bridge on the AGP bus, which should be a
604 * safe assumptions hopefully.
605 */
606 if (u3_agp) {
607 struct device_node *np = u3_agp->arch_data;
Paul Mackerras16353172005-09-06 13:17:54 +1000608 PCI_DN(np)->busno = 0xf0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700609 for (np = np->child; np; np = np->sibling)
Paul Mackerras16353172005-09-06 13:17:54 +1000610 PCI_DN(np)->busno = 0xf0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611 }
612
Segher Boessenkool4558f412006-02-17 11:30:30 +0100613 /* Tell pci.c to not change any resource allocations. */
614 pci_probe_only = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700615}
616
617int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
618{
619 struct device_node *np;
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000620 unsigned int defirq = channel ? 15 : 14;
621 unsigned int irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622
623 if (pdev->vendor != PCI_VENDOR_ID_AMD ||
624 pdev->device != PCI_DEVICE_ID_AMD_8111_IDE)
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000625 return defirq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626
627 np = pci_device_to_OF_node(pdev);
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +1000628 if (np == NULL) {
629 printk("Failed to locate OF node for IDE %s\n",
630 pci_name(pdev));
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000631 return defirq;
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +1000632 }
Benjamin Herrenschmidt0ebfff12006-07-03 21:36:01 +1000633 irq = irq_of_parse_and_map(np, channel & 0x1);
634 if (irq == NO_IRQ) {
635 printk("Failed to map onboard IDE interrupt for channel %d\n",
636 channel);
637 return defirq;
638 }
639 return irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700640}
641
642/* XXX: To remove once all firmwares are ok */
643static void fixup_maple_ide(struct pci_dev* dev)
644{
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +1000645 if (!machine_is(maple))
646 return;
647
Linus Torvalds1da177e2005-04-16 15:20:36 -0700648#if 0 /* Enable this to enable IDE port 0 */
649 {
650 u8 v;
651
652 pci_read_config_byte(dev, 0x40, &v);
653 v |= 2;
654 pci_write_config_byte(dev, 0x40, v);
655 }
656#endif
657#if 0 /* fix bus master base */
658 pci_write_config_dword(dev, 0x20, 0xcc01);
659 printk("old ide resource: %lx -> %lx \n",
660 dev->resource[4].start, dev->resource[4].end);
661 dev->resource[4].start = 0xcc00;
662 dev->resource[4].end = 0xcc10;
663#endif
Benjamin Herrenschmidtc10af8c2006-10-09 13:25:15 +1000664#if 0 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665 {
666 struct pci_dev *apicdev;
667 u32 v;
668
669 apicdev = pci_get_slot (dev->bus, PCI_DEVFN(5,0));
670 if (apicdev == NULL)
671 printk("IDE Fixup IRQ: Can't find IO-APIC !\n");
672 else {
673 pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*14);
674 pci_read_config_dword(apicdev, 0xf4, &v);
675 v &= ~0x00000022;
676 pci_write_config_dword(apicdev, 0xf4, v);
677 pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*15);
678 pci_read_config_dword(apicdev, 0xf4, &v);
679 v &= ~0x00000022;
680 pci_write_config_dword(apicdev, 0xf4, v);
681 pci_dev_put(apicdev);
682 }
683 }
684#endif
685}
686DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE,
687 fixup_maple_ide);