[POWERPC] Maple U3 HT - reject inappropriate config space access
When there is a PCI-X mode 2 capable device behind the HT<->PCI-X
bridge, the pci core decides that the device has the extended 4K
config space, even though the bus is not operating in mode 2. This is
because the u3_ht pci ops silently accept offsets greater than 255 but
use only the 8 least significant bits, which means reading at offset
0x100 gets the data at offset 0x0, and causes confusion for lspci.
Reject accesses to configuration space offsets greater than 255.
Signed-off-by: Nathan Lynch <ntl@pobox.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c
index dc05af5..ec5c14f 100644
--- a/arch/powerpc/platforms/maple/pci.c
+++ b/arch/powerpc/platforms/maple/pci.c
@@ -213,6 +213,9 @@
if (hose == NULL)
return PCIBIOS_DEVICE_NOT_FOUND;
+ if (offset > 0xff)
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
if (!addr)
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -245,6 +248,9 @@
if (hose == NULL)
return PCIBIOS_DEVICE_NOT_FOUND;
+ if (offset > 0xff)
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
if (!addr)
return PCIBIOS_DEVICE_NOT_FOUND;
