Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/clock.c |
| 3 | * |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2004-2008 Nokia Corporation |
| 6 | * |
| 7 | * Contacts: |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 9 | * Paul Walmsley |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 10 | * |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, |
| 12 | * Gordon McNutt and RidgeRun, Inc. |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License version 2 as |
| 16 | * published by the Free Software Foundation. |
| 17 | */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 18 | #undef DEBUG |
| 19 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 20 | #include <linux/module.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/device.h> |
| 23 | #include <linux/list.h> |
| 24 | #include <linux/errno.h> |
| 25 | #include <linux/delay.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 26 | #include <linux/clk.h> |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 27 | #include <linux/io.h> |
| 28 | #include <linux/cpufreq.h> |
Russell King | fbd3bdb | 2008-09-06 12:13:59 +0100 | [diff] [blame] | 29 | #include <linux/bitops.h> |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 30 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 31 | #include <mach/clock.h> |
| 32 | #include <mach/sram.h> |
Tony Lindgren | 7663148 | 2006-12-12 23:02:43 -0800 | [diff] [blame] | 33 | #include <asm/div64.h> |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 34 | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 35 | #include "memory.h" |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 36 | #include "clock.h" |
Paul Walmsley | 32ab2cb | 2008-03-18 10:15:28 +0200 | [diff] [blame] | 37 | #include "clock24xx.h" |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 38 | #include "prm.h" |
| 39 | #include "prm-regbits-24xx.h" |
| 40 | #include "cm.h" |
| 41 | #include "cm-regbits-24xx.h" |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 42 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 43 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ |
| 44 | #define EN_APLL_STOPPED 0 |
| 45 | #define EN_APLL_LOCKED 3 |
Juha Yrjola | ddc32a8 | 2006-09-25 12:41:50 +0300 | [diff] [blame] | 46 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 47 | /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ |
| 48 | #define APLLS_CLKIN_19_2MHZ 0 |
| 49 | #define APLLS_CLKIN_13MHZ 2 |
| 50 | #define APLLS_CLKIN_12MHZ 3 |
| 51 | |
| 52 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 53 | |
| 54 | static struct prcm_config *curr_prcm_set; |
Tony Lindgren | ae78dcf | 2006-09-25 12:41:20 +0300 | [diff] [blame] | 55 | static struct clk *vclk; |
| 56 | static struct clk *sclk; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 57 | |
| 58 | /*------------------------------------------------------------------------- |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 59 | * Omap24xx specific clock functions |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 60 | *-------------------------------------------------------------------------*/ |
| 61 | |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 62 | /* This actually returns the rate of core_ck, not dpll_ck. */ |
| 63 | static u32 omap2_get_dpll_rate_24xx(struct clk *tclk) |
| 64 | { |
| 65 | long long dpll_clk; |
| 66 | u8 amult; |
| 67 | |
| 68 | dpll_clk = omap2_get_dpll_rate(tclk); |
| 69 | |
| 70 | amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 71 | amult &= OMAP24XX_CORE_CLK_SRC_MASK; |
| 72 | dpll_clk *= amult; |
| 73 | |
| 74 | return dpll_clk; |
| 75 | } |
| 76 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 77 | static int omap2_enable_osc_ck(struct clk *clk) |
| 78 | { |
| 79 | u32 pcc; |
| 80 | |
| 81 | pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); |
| 82 | |
| 83 | __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, |
| 84 | OMAP24XX_PRCM_CLKSRC_CTRL); |
| 85 | |
| 86 | return 0; |
| 87 | } |
| 88 | |
| 89 | static void omap2_disable_osc_ck(struct clk *clk) |
| 90 | { |
| 91 | u32 pcc; |
| 92 | |
| 93 | pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); |
| 94 | |
| 95 | __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, |
| 96 | OMAP24XX_PRCM_CLKSRC_CTRL); |
| 97 | } |
| 98 | |
| 99 | #ifdef OLD_CK |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 100 | /* Recalculate SYST_CLK */ |
| 101 | static void omap2_sys_clk_recalc(struct clk * clk) |
| 102 | { |
| 103 | u32 div = PRCM_CLKSRC_CTRL; |
| 104 | div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ |
| 105 | div >>= clk->rate_offset; |
| 106 | clk->rate = (clk->parent->rate / div); |
| 107 | propagate_rate(clk); |
| 108 | } |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 109 | #endif /* OLD_CK */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 110 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 111 | /* Enable an APLL if off */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 112 | static int omap2_clk_fixed_enable(struct clk *clk) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 113 | { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 114 | u32 cval, apll_mask; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 115 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 116 | apll_mask = EN_APLL_LOCKED << clk->enable_bit; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 117 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 118 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 119 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 120 | if ((cval & apll_mask) == apll_mask) |
| 121 | return 0; /* apll already enabled */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 122 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 123 | cval &= ~apll_mask; |
| 124 | cval |= apll_mask; |
| 125 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 126 | |
| 127 | if (clk == &apll96_ck) |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 128 | cval = OMAP24XX_ST_96M_APLL; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 129 | else if (clk == &apll54_ck) |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 130 | cval = OMAP24XX_ST_54M_APLL; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 131 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 132 | omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval, |
| 133 | clk->name); |
| 134 | |
| 135 | /* |
| 136 | * REVISIT: Should we return an error code if omap2_wait_clock_ready() |
| 137 | * fails? |
| 138 | */ |
| 139 | return 0; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 140 | } |
| 141 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 142 | /* Stop APLL */ |
| 143 | static void omap2_clk_fixed_disable(struct clk *clk) |
| 144 | { |
| 145 | u32 cval; |
| 146 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 147 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); |
| 148 | cval &= ~(EN_APLL_LOCKED << clk->enable_bit); |
| 149 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 150 | } |
| 151 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 152 | /* |
| 153 | * Uses the current prcm set to tell if a rate is valid. |
| 154 | * You can go slower, but not faster within a given rate set. |
| 155 | */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 156 | long omap2_dpllcore_round_rate(unsigned long target_rate) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 157 | { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 158 | u32 high, low, core_clk_src; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 159 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 160 | core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 161 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; |
| 162 | |
| 163 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 164 | high = curr_prcm_set->dpll_speed * 2; |
| 165 | low = curr_prcm_set->dpll_speed; |
| 166 | } else { /* DPLL clockout x 2 */ |
| 167 | high = curr_prcm_set->dpll_speed; |
| 168 | low = curr_prcm_set->dpll_speed / 2; |
| 169 | } |
| 170 | |
| 171 | #ifdef DOWN_VARIABLE_DPLL |
| 172 | if (target_rate > high) |
| 173 | return high; |
| 174 | else |
| 175 | return target_rate; |
| 176 | #else |
| 177 | if (target_rate > low) |
| 178 | return high; |
| 179 | else |
| 180 | return low; |
| 181 | #endif |
| 182 | |
| 183 | } |
| 184 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 185 | static void omap2_dpllcore_recalc(struct clk *clk) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 186 | { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 187 | clk->rate = omap2_get_dpll_rate_24xx(clk); |
| 188 | |
| 189 | propagate_rate(clk); |
| 190 | } |
| 191 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 192 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 193 | { |
| 194 | u32 cur_rate, low, mult, div, valid_rate, done_rate; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 195 | u32 bypass = 0; |
| 196 | struct prcm_config tmpset; |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 197 | const struct dpll_data *dd; |
| 198 | unsigned long flags; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 199 | int ret = -EINVAL; |
| 200 | |
| 201 | local_irq_save(flags); |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 202 | cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); |
| 203 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 204 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 205 | |
| 206 | if ((rate == (cur_rate / 2)) && (mult == 2)) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 207 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 208 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 209 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 210 | } else if (rate != cur_rate) { |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 211 | valid_rate = omap2_dpllcore_round_rate(rate); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 212 | if (valid_rate != rate) |
| 213 | goto dpll_exit; |
| 214 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 215 | if (mult == 1) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 216 | low = curr_prcm_set->dpll_speed; |
| 217 | else |
| 218 | low = curr_prcm_set->dpll_speed / 2; |
| 219 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 220 | dd = clk->dpll_data; |
| 221 | if (!dd) |
| 222 | goto dpll_exit; |
| 223 | |
| 224 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); |
| 225 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | |
| 226 | dd->div1_mask); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 227 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 228 | tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 229 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 230 | if (rate > low) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 231 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 232 | mult = ((rate / 2) / 1000000); |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 233 | done_rate = CORE_CLK_SRC_DPLL_X2; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 234 | } else { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 235 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 236 | mult = (rate / 1000000); |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 237 | done_rate = CORE_CLK_SRC_DPLL; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 238 | } |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 239 | tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); |
| 240 | tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 241 | |
| 242 | /* Worst case */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 243 | tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 244 | |
| 245 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ |
| 246 | bypass = 1; |
| 247 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 248 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */ |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 249 | |
| 250 | /* Force dll lock mode */ |
| 251 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, |
| 252 | bypass); |
| 253 | |
| 254 | /* Errata: ret dll entry state */ |
| 255 | omap2_init_memory_params(omap2_dll_force_needed()); |
| 256 | omap2_reprogram_sdrc(done_rate, 0); |
| 257 | } |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 258 | omap2_dpllcore_recalc(&dpll_ck); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 259 | ret = 0; |
| 260 | |
| 261 | dpll_exit: |
| 262 | local_irq_restore(flags); |
| 263 | return(ret); |
| 264 | } |
| 265 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 266 | /** |
| 267 | * omap2_table_mpu_recalc - just return the MPU speed |
| 268 | * @clk: virt_prcm_set struct clk |
| 269 | * |
| 270 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. |
| 271 | */ |
| 272 | static void omap2_table_mpu_recalc(struct clk *clk) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 273 | { |
| 274 | clk->rate = curr_prcm_set->mpu_speed; |
| 275 | } |
| 276 | |
| 277 | /* |
| 278 | * Look for a rate equal or less than the target rate given a configuration set. |
| 279 | * |
| 280 | * What's not entirely clear is "which" field represents the key field. |
| 281 | * Some might argue L3-DDR, others ARM, others IVA. This code is simple and |
| 282 | * just uses the ARM rates. |
| 283 | */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 284 | static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 285 | { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 286 | struct prcm_config *ptr; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 287 | long highest_rate; |
| 288 | |
| 289 | if (clk != &virt_prcm_set) |
| 290 | return -EINVAL; |
| 291 | |
| 292 | highest_rate = -EINVAL; |
| 293 | |
| 294 | for (ptr = rate_table; ptr->mpu_speed; ptr++) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 295 | if (!(ptr->flags & cpu_mask)) |
| 296 | continue; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 297 | if (ptr->xtal_speed != sys_ck.rate) |
| 298 | continue; |
| 299 | |
| 300 | highest_rate = ptr->mpu_speed; |
| 301 | |
| 302 | /* Can check only after xtal frequency check */ |
| 303 | if (ptr->mpu_speed <= rate) |
| 304 | break; |
| 305 | } |
| 306 | return highest_rate; |
| 307 | } |
| 308 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 309 | /* Sets basic clocks based on the specified rate */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 310 | static int omap2_select_table_rate(struct clk *clk, unsigned long rate) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 311 | { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 312 | u32 cur_rate, done_rate, bypass = 0, tmp; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 313 | struct prcm_config *prcm; |
| 314 | unsigned long found_speed = 0; |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 315 | unsigned long flags; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 316 | |
| 317 | if (clk != &virt_prcm_set) |
| 318 | return -EINVAL; |
| 319 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 320 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
| 321 | if (!(prcm->flags & cpu_mask)) |
| 322 | continue; |
| 323 | |
| 324 | if (prcm->xtal_speed != sys_ck.rate) |
| 325 | continue; |
| 326 | |
| 327 | if (prcm->mpu_speed <= rate) { |
| 328 | found_speed = prcm->mpu_speed; |
| 329 | break; |
| 330 | } |
| 331 | } |
| 332 | |
| 333 | if (!found_speed) { |
| 334 | printk(KERN_INFO "Could not set MPU rate to %luMHz\n", |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 335 | rate / 1000000); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 336 | return -EINVAL; |
| 337 | } |
| 338 | |
| 339 | curr_prcm_set = prcm; |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 340 | cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 341 | |
| 342 | if (prcm->dpll_speed == cur_rate / 2) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 343 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 344 | } else if (prcm->dpll_speed == cur_rate * 2) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 345 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 346 | } else if (prcm->dpll_speed != cur_rate) { |
| 347 | local_irq_save(flags); |
| 348 | |
| 349 | if (prcm->dpll_speed == prcm->xtal_speed) |
| 350 | bypass = 1; |
| 351 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 352 | if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == |
| 353 | CORE_CLK_SRC_DPLL_X2) |
| 354 | done_rate = CORE_CLK_SRC_DPLL_X2; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 355 | else |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 356 | done_rate = CORE_CLK_SRC_DPLL; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 357 | |
| 358 | /* MPU divider */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 359 | cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 360 | |
| 361 | /* dsp + iva1 div(2420), iva2.1(2430) */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 362 | cm_write_mod_reg(prcm->cm_clksel_dsp, |
| 363 | OMAP24XX_DSP_MOD, CM_CLKSEL); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 364 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 365 | cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 366 | |
| 367 | /* Major subsystem dividers */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 368 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; |
| 369 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 370 | if (cpu_is_omap2430()) |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 371 | cm_write_mod_reg(prcm->cm_clksel_mdm, |
| 372 | OMAP2430_MDM_MOD, CM_CLKSEL); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 373 | |
| 374 | /* x2 to enter init_mem */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 375 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 376 | |
| 377 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, |
| 378 | bypass); |
| 379 | |
| 380 | omap2_init_memory_params(omap2_dll_force_needed()); |
| 381 | omap2_reprogram_sdrc(done_rate, 0); |
| 382 | |
| 383 | local_irq_restore(flags); |
| 384 | } |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 385 | omap2_dpllcore_recalc(&dpll_ck); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 386 | |
| 387 | return 0; |
| 388 | } |
| 389 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 390 | static struct clk_functions omap2_clk_functions = { |
| 391 | .clk_enable = omap2_clk_enable, |
| 392 | .clk_disable = omap2_clk_disable, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 393 | .clk_round_rate = omap2_clk_round_rate, |
| 394 | .clk_set_rate = omap2_clk_set_rate, |
| 395 | .clk_set_parent = omap2_clk_set_parent, |
Tony Lindgren | 90afd5c | 2006-09-25 13:27:20 +0300 | [diff] [blame] | 396 | .clk_disable_unused = omap2_clk_disable_unused, |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 397 | }; |
| 398 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 399 | static u32 omap2_get_apll_clkin(void) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 400 | { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 401 | u32 aplls, sclk = 0; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 402 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 403 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); |
| 404 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; |
| 405 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 406 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 407 | if (aplls == APLLS_CLKIN_19_2MHZ) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 408 | sclk = 19200000; |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 409 | else if (aplls == APLLS_CLKIN_13MHZ) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 410 | sclk = 13000000; |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 411 | else if (aplls == APLLS_CLKIN_12MHZ) |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 412 | sclk = 12000000; |
| 413 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 414 | return sclk; |
| 415 | } |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 416 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 417 | static u32 omap2_get_sysclkdiv(void) |
| 418 | { |
| 419 | u32 div; |
| 420 | |
| 421 | div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL); |
| 422 | div &= OMAP_SYSCLKDIV_MASK; |
| 423 | div >>= OMAP_SYSCLKDIV_SHIFT; |
| 424 | |
| 425 | return div; |
| 426 | } |
| 427 | |
| 428 | static void omap2_osc_clk_recalc(struct clk *clk) |
| 429 | { |
| 430 | clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv(); |
| 431 | propagate_rate(clk); |
| 432 | } |
| 433 | |
| 434 | static void omap2_sys_clk_recalc(struct clk *clk) |
| 435 | { |
| 436 | clk->rate = clk->parent->rate / omap2_get_sysclkdiv(); |
| 437 | propagate_rate(clk); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 438 | } |
| 439 | |
Tony Lindgren | ae78dcf | 2006-09-25 12:41:20 +0300 | [diff] [blame] | 440 | /* |
| 441 | * Set clocks for bypass mode for reboot to work. |
| 442 | */ |
| 443 | void omap2_clk_prepare_for_reboot(void) |
| 444 | { |
| 445 | u32 rate; |
| 446 | |
| 447 | if (vclk == NULL || sclk == NULL) |
| 448 | return; |
| 449 | |
| 450 | rate = clk_get_rate(sclk); |
| 451 | clk_set_rate(vclk, rate); |
| 452 | } |
| 453 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 454 | /* |
| 455 | * Switch the MPU rate if specified on cmdline. |
| 456 | * We cannot do this early until cmdline is parsed. |
| 457 | */ |
| 458 | static int __init omap2_clk_arch_init(void) |
| 459 | { |
| 460 | if (!mpurate) |
| 461 | return -EINVAL; |
| 462 | |
| 463 | if (omap2_select_table_rate(&virt_prcm_set, mpurate)) |
| 464 | printk(KERN_ERR "Could not find matching MPU rate\n"); |
| 465 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 466 | recalculate_root_clocks(); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 467 | |
| 468 | printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): " |
| 469 | "%ld.%01ld/%ld/%ld MHz\n", |
| 470 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, |
| 471 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; |
| 472 | |
| 473 | return 0; |
| 474 | } |
| 475 | arch_initcall(omap2_clk_arch_init); |
| 476 | |
| 477 | int __init omap2_clk_init(void) |
| 478 | { |
| 479 | struct prcm_config *prcm; |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 480 | struct clk **clkp; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 481 | u32 clkrate; |
| 482 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 483 | if (cpu_is_omap242x()) |
| 484 | cpu_mask = RATE_IN_242X; |
| 485 | else if (cpu_is_omap2430()) |
| 486 | cpu_mask = RATE_IN_243X; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 487 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 488 | clk_init(&omap2_clk_functions); |
| 489 | |
| 490 | omap2_osc_clk_recalc(&osc_ck); |
| 491 | omap2_sys_clk_recalc(&sys_ck); |
| 492 | |
| 493 | for (clkp = onchip_24xx_clks; |
| 494 | clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 495 | clkp++) { |
| 496 | |
| 497 | if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { |
| 498 | clk_register(*clkp); |
| 499 | continue; |
| 500 | } |
| 501 | |
| 502 | if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) { |
| 503 | clk_register(*clkp); |
| 504 | continue; |
| 505 | } |
| 506 | } |
| 507 | |
| 508 | /* Check the MPU rate set by bootloader */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 509 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 510 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 511 | if (!(prcm->flags & cpu_mask)) |
| 512 | continue; |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 513 | if (prcm->xtal_speed != sys_ck.rate) |
| 514 | continue; |
| 515 | if (prcm->dpll_speed <= clkrate) |
| 516 | break; |
| 517 | } |
| 518 | curr_prcm_set = prcm; |
| 519 | |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 520 | recalculate_root_clocks(); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 521 | |
| 522 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " |
| 523 | "%ld.%01ld/%ld/%ld MHz\n", |
| 524 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, |
| 525 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; |
| 526 | |
| 527 | /* |
| 528 | * Only enable those clocks we will need, let the drivers |
| 529 | * enable other clocks as necessary |
| 530 | */ |
Paul Walmsley | 6b8858a | 2008-03-18 10:35:15 +0200 | [diff] [blame] | 531 | clk_enable_init_clocks(); |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 532 | |
Tony Lindgren | ae78dcf | 2006-09-25 12:41:20 +0300 | [diff] [blame] | 533 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ |
| 534 | vclk = clk_get(NULL, "virt_prcm_set"); |
| 535 | sclk = clk_get(NULL, "sys_ck"); |
| 536 | |
Tony Lindgren | 046d6b2 | 2005-11-10 14:26:52 +0000 | [diff] [blame] | 537 | return 0; |
| 538 | } |