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Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +03001/*
2 * linux/arch/arm/mach-omap3/sram.S
3 *
4 * Omap3 specific functions that need to be run in internal SRAM
5 *
Paul Walmsley4267b5d2009-06-19 19:08:27 -06006 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
7 * Copyright (C) 2008 Nokia Corporation
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +03008 *
Paul Walmsley4267b5d2009-06-19 19:08:27 -06009 * Rajendra Nayak <rnayak@ti.com>
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030010 * Richard Woodruff <r-woodruff2@ti.com>
Paul Walmsley4267b5d2009-06-19 19:08:27 -060011 * Paul Walmsley
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030012 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28#include <linux/linkage.h>
29#include <asm/assembler.h>
30#include <mach/hardware.h>
31
32#include <mach/io.h>
33
34#include "sdrc.h"
35#include "cm.h"
36
37 .text
38
Jean Pihet58cda882009-07-24 19:43:25 -060039/* r1 parameters */
Paul Walmsleydf14e472009-06-19 19:08:28 -060040#define SDRC_NO_UNLOCK_DLL 0x0
41#define SDRC_UNLOCK_DLL 0x1
42
43/* SDRC_DLLA_CTRL bit settings */
Paul Walmsley7b7bcef2009-06-19 19:08:29 -060044#define FIXEDDELAY_SHIFT 24
45#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
Paul Walmsleydf14e472009-06-19 19:08:28 -060046#define DLLIDLE_MASK 0x4
47
Paul Walmsley7b7bcef2009-06-19 19:08:29 -060048/*
49 * SDRC_DLLA_CTRL default values: TI hardware team indicates that
50 * FIXEDDELAY should be initialized to 0xf. This apparently was
51 * empirically determined during process testing, so no derivation
52 * was provided.
53 */
54#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
55
Paul Walmsleydf14e472009-06-19 19:08:28 -060056/* SDRC_DLLA_STATUS bit settings */
57#define LOCKSTATUS_MASK 0x4
58
59/* SDRC_POWER bit settings */
60#define SRFRONIDLEREQ_MASK 0x40
Paul Walmsleydf14e472009-06-19 19:08:28 -060061
62/* CM_IDLEST1_CORE bit settings */
63#define ST_SDRC_MASK 0x2
64
65/* CM_ICLKEN1_CORE bit settings */
66#define EN_SDRC_MASK 0x2
67
68/* CM_CLKSEL1_PLL bit settings */
69#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
70
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030071/*
Paul Walmsley4267b5d2009-06-19 19:08:27 -060072 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
Paul Walmsleyc9812d02009-06-19 19:08:26 -060073 *
Jean Pihet58cda882009-07-24 19:43:25 -060074 * Params passed in registers:
75 * r0 = new M2 divider setting (only 1 and 2 supported right now)
76 * r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
77 * SDRC rates < 83MHz
78 * r2 = number of MPU cycles to wait for SDRC to stabilize after
79 * reprogramming the SDRC when switching to a slower MPU speed
80 * r3 = increasing SDRC rate? (1 = yes, 0 = no)
81 *
82 * Params passed via the stack. The needed params will be copied in SRAM
83 * before use by the code in SRAM (SDRAM is not accessible during SDRC
84 * reconfiguration):
85 * new SDRC_RFR_CTRL_0 register contents
86 * new SDRC_ACTIM_CTRL_A_0 register contents
87 * new SDRC_ACTIM_CTRL_B_0 register contents
88 * new SDRC_MR_0 register value
89 * new SDRC_RFR_CTRL_1 register contents
90 * new SDRC_ACTIM_CTRL_A_1 register contents
91 * new SDRC_ACTIM_CTRL_B_1 register contents
92 * new SDRC_MR_1 register value
93 *
Paul Walmsley18862cb2009-12-08 16:33:14 -070094 * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
95 * the SDRC CS1 registers
96 *
97 * NOTE: This code no longer attempts to program the SDRC AC timing and MR
98 * registers. This is because the code currently cannot ensure that all
99 * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
100 * SDRAM when the registers are written. If the registers are changed while
101 * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
102 * may enter an unpredictable state. In the future, the intent is to
103 * re-enable this code in cases where we can ensure that no initiators are
104 * touching the SDRAM. Until that time, users who know that their use case
105 * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
106 * option.
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300107 */
108ENTRY(omap3_sram_configure_core_dpll)
109 stmfd sp!, {r1-r12, lr} @ store regs to stack
Jean Pihet58cda882009-07-24 19:43:25 -0600110
111 @ pull the extra args off the stack
112 @ and store them in SRAM
113 ldr r4, [sp, #52]
114 str r4, omap_sdrc_rfr_ctrl_0_val
115 ldr r4, [sp, #56]
116 str r4, omap_sdrc_actim_ctrl_a_0_val
117 ldr r4, [sp, #60]
118 str r4, omap_sdrc_actim_ctrl_b_0_val
119 ldr r4, [sp, #64]
120 str r4, omap_sdrc_mr_0_val
121 ldr r4, [sp, #68]
122 str r4, omap_sdrc_rfr_ctrl_1_val
123 cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
124 beq skip_cs1_params @ do not use cs1 params
125 ldr r4, [sp, #72]
126 str r4, omap_sdrc_actim_ctrl_a_1_val
127 ldr r4, [sp, #76]
128 str r4, omap_sdrc_actim_ctrl_b_1_val
129 ldr r4, [sp, #80]
130 str r4, omap_sdrc_mr_1_val
131skip_cs1_params:
Paul Walmsley69d42552009-05-12 17:27:09 -0600132 dsb @ flush buffered writes to interconnect
Jean Pihet58cda882009-07-24 19:43:25 -0600133
134 cmp r3, #1 @ if increasing SDRC clk rate,
Tero Kristo3afec632009-06-19 19:08:29 -0600135 bleq configure_sdrc @ program the SDRC regs early (for RFR)
Jean Pihet58cda882009-07-24 19:43:25 -0600136 cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
Paul Walmsley4519c2b2009-05-12 17:26:32 -0600137 bleq unlock_dll
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300138 blne lock_dll
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600139 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
140 bl configure_core_dpll @ change the DPLL3 M2 divider
Rajendra Nayakdf565562009-07-24 19:44:02 -0600141 mov r12, r2
142 bl wait_clk_stable @ wait for SDRC to stabilize
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600143 bl enable_sdrc @ take SDRC out of idle
Jean Pihet58cda882009-07-24 19:43:25 -0600144 cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
Paul Walmsley4519c2b2009-05-12 17:26:32 -0600145 bleq wait_dll_unlock
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300146 blne wait_dll_lock
Jean Pihet58cda882009-07-24 19:43:25 -0600147 cmp r3, #1 @ if increasing SDRC clk rate,
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600148 beq return_to_sdram @ return to SDRAM code, otherwise,
149 bl configure_sdrc @ reprogram SDRC regs now
Paul Walmsleyc9812d02009-06-19 19:08:26 -0600150return_to_sdram:
Paul Walmsley69d42552009-05-12 17:27:09 -0600151 isb @ prevent speculative exec past here
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300152 mov r0, #0 @ return value
153 ldmfd sp!, {r1-r12, pc} @ restore regs and return
154unlock_dll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600155 ldr r11, omap3_sdrc_dlla_ctrl
156 ldr r12, [r11]
Rajendra Nayak8ff120e2009-07-24 19:44:01 -0600157 bic r12, r12, #FIXEDDELAY_MASK
Paul Walmsley7b7bcef2009-06-19 19:08:29 -0600158 orr r12, r12, #FIXEDDELAY_DEFAULT
Paul Walmsleydf14e472009-06-19 19:08:28 -0600159 orr r12, r12, #DLLIDLE_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600160 str r12, [r11] @ (no OCP barrier needed)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300161 bx lr
162lock_dll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600163 ldr r11, omap3_sdrc_dlla_ctrl
164 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600165 bic r12, r12, #DLLIDLE_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600166 str r12, [r11] @ (no OCP barrier needed)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300167 bx lr
168sdram_in_selfrefresh:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600169 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
170 ldr r12, [r11] @ read the contents of SDRC_POWER
171 mov r9, r12 @ keep a copy of SDRC_POWER bits
Paul Walmsleydf14e472009-06-19 19:08:28 -0600172 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600173 str r12, [r11] @ write back to SDRC_POWER register
174 ldr r12, [r11] @ posted-write barrier for SDRC
Paul Walmsley4267b5d2009-06-19 19:08:27 -0600175idle_sdrc:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600176 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
177 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600178 bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600179 str r12, [r11]
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300180wait_sdrc_idle:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600181 ldr r11, omap3_cm_idlest1_core
182 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600183 and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
184 cmp r12, #ST_SDRC_MASK
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300185 bne wait_sdrc_idle
186 bx lr
187configure_core_dpll:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600188 ldr r11, omap3_cm_clksel1_pll
189 ldr r12, [r11]
190 ldr r10, core_m2_mask_val @ modify m2 for core dpll
191 and r12, r12, r10
Jean Pihet58cda882009-07-24 19:43:25 -0600192 orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600193 str r12, [r11]
194 ldr r12, [r11] @ posted-write barrier for CM
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300195 bx lr
196wait_clk_stable:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600197 subs r12, r12, #1
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300198 bne wait_clk_stable
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300199 bx lr
200enable_sdrc:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600201 ldr r11, omap3_cm_iclken1_core
202 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600203 orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600204 str r12, [r11]
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300205wait_sdrc_idle1:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600206 ldr r11, omap3_cm_idlest1_core
207 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600208 and r12, r12, #ST_SDRC_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600209 cmp r12, #0
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300210 bne wait_sdrc_idle1
Paul Walmsleyfa0406a2009-05-12 17:27:09 -0600211restore_sdrc_power_val:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600212 ldr r11, omap3_sdrc_power
213 str r9, [r11] @ restore SDRC_POWER, no barrier needed
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300214 bx lr
215wait_dll_lock:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600216 ldr r11, omap3_sdrc_dlla_status
217 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600218 and r12, r12, #LOCKSTATUS_MASK
219 cmp r12, #LOCKSTATUS_MASK
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300220 bne wait_dll_lock
221 bx lr
222wait_dll_unlock:
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600223 ldr r11, omap3_sdrc_dlla_status
224 ldr r12, [r11]
Paul Walmsleydf14e472009-06-19 19:08:28 -0600225 and r12, r12, #LOCKSTATUS_MASK
Paul Walmsleyb2abb272009-05-12 17:27:10 -0600226 cmp r12, #0x0
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300227 bne wait_dll_unlock
228 bx lr
229configure_sdrc:
Jean Pihet58cda882009-07-24 19:43:25 -0600230 ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
231 ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
232 str r12, [r11] @ store
Paul Walmsley18862cb2009-12-08 16:33:14 -0700233#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
Jean Pihet58cda882009-07-24 19:43:25 -0600234 ldr r12, omap_sdrc_actim_ctrl_a_0_val
235 ldr r11, omap3_sdrc_actim_ctrl_a_0
236 str r12, [r11]
237 ldr r12, omap_sdrc_actim_ctrl_b_0_val
238 ldr r11, omap3_sdrc_actim_ctrl_b_0
239 str r12, [r11]
240 ldr r12, omap_sdrc_mr_0_val
Paul Walmsleyd0ba3922009-06-19 19:08:27 -0600241 ldr r11, omap3_sdrc_mr_0
Jean Pihet58cda882009-07-24 19:43:25 -0600242 str r12, [r11]
Paul Walmsley18862cb2009-12-08 16:33:14 -0700243#endif
Jean Pihet58cda882009-07-24 19:43:25 -0600244 ldr r12, omap_sdrc_rfr_ctrl_1_val
245 cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
246 beq skip_cs1_prog @ do not program cs1 params
247 ldr r11, omap3_sdrc_rfr_ctrl_1
248 str r12, [r11]
Paul Walmsley18862cb2009-12-08 16:33:14 -0700249#ifdef CONFIG_OMAP3_SDRC_AC_TIMING
Jean Pihet58cda882009-07-24 19:43:25 -0600250 ldr r12, omap_sdrc_actim_ctrl_a_1_val
251 ldr r11, omap3_sdrc_actim_ctrl_a_1
252 str r12, [r11]
253 ldr r12, omap_sdrc_actim_ctrl_b_1_val
254 ldr r11, omap3_sdrc_actim_ctrl_b_1
255 str r12, [r11]
256 ldr r12, omap_sdrc_mr_1_val
257 ldr r11, omap3_sdrc_mr_1
258 str r12, [r11]
Paul Walmsley18862cb2009-12-08 16:33:14 -0700259#endif
Jean Pihet58cda882009-07-24 19:43:25 -0600260skip_cs1_prog:
261 ldr r12, [r11] @ posted-write barrier for SDRC
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300262 bx lr
263
264omap3_sdrc_power:
265 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
266omap3_cm_clksel1_pll:
267 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
268omap3_cm_idlest1_core:
269 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
270omap3_cm_iclken1_core:
271 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
Jean Pihet58cda882009-07-24 19:43:25 -0600272
273omap3_sdrc_rfr_ctrl_0:
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300274 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
Jean Pihet58cda882009-07-24 19:43:25 -0600275omap3_sdrc_rfr_ctrl_1:
276 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
277omap3_sdrc_actim_ctrl_a_0:
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300278 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
Jean Pihet58cda882009-07-24 19:43:25 -0600279omap3_sdrc_actim_ctrl_a_1:
280 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
281omap3_sdrc_actim_ctrl_b_0:
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300282 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
Jean Pihet58cda882009-07-24 19:43:25 -0600283omap3_sdrc_actim_ctrl_b_1:
284 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
Paul Walmsleyd0ba3922009-06-19 19:08:27 -0600285omap3_sdrc_mr_0:
286 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
Jean Pihet58cda882009-07-24 19:43:25 -0600287omap3_sdrc_mr_1:
288 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
289omap_sdrc_rfr_ctrl_0_val:
290 .word 0xDEADBEEF
291omap_sdrc_rfr_ctrl_1_val:
292 .word 0xDEADBEEF
293omap_sdrc_actim_ctrl_a_0_val:
294 .word 0xDEADBEEF
295omap_sdrc_actim_ctrl_a_1_val:
296 .word 0xDEADBEEF
297omap_sdrc_actim_ctrl_b_0_val:
298 .word 0xDEADBEEF
299omap_sdrc_actim_ctrl_b_1_val:
300 .word 0xDEADBEEF
301omap_sdrc_mr_0_val:
302 .word 0xDEADBEEF
303omap_sdrc_mr_1_val:
304 .word 0xDEADBEEF
305
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300306omap3_sdrc_dlla_status:
307 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
308omap3_sdrc_dlla_ctrl:
309 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
310core_m2_mask_val:
311 .word 0x07FFFFFF
312
313ENTRY(omap3_sram_configure_core_dpll_sz)
314 .word . - omap3_sram_configure_core_dpll
Jean Pihet58cda882009-07-24 19:43:25 -0600315