Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * cpu.h: Values of the PRId register used to match up |
| 3 | * various MIPS cpu types. |
| 4 | * |
| 5 | * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 6 | * Copyright (C) 2004 Maciej W. Rozycki |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | */ |
| 8 | #ifndef _ASM_CPU_H |
| 9 | #define _ASM_CPU_H |
| 10 | |
| 11 | /* Assigned Company values for bits 23:16 of the PRId Register |
| 12 | (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from |
| 13 | MTI, the PRId register is defined in this (backwards compatible) |
| 14 | way: |
| 15 | |
| 16 | +----------------+----------------+----------------+----------------+ |
| 17 | | Company Options| Company ID | Processor ID | Revision | |
| 18 | +----------------+----------------+----------------+----------------+ |
| 19 | 31 24 23 16 15 8 7 |
| 20 | |
| 21 | I don't have docs for all the previous processors, but my impression is |
| 22 | that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 |
| 23 | spec. |
| 24 | */ |
| 25 | |
Ralf Baechle | 55a6feb | 2005-02-07 21:52:35 +0000 | [diff] [blame] | 26 | #define PRID_COMP_LEGACY 0x000000 |
| 27 | #define PRID_COMP_MIPS 0x010000 |
| 28 | #define PRID_COMP_BROADCOM 0x020000 |
| 29 | #define PRID_COMP_ALCHEMY 0x030000 |
| 30 | #define PRID_COMP_SIBYTE 0x040000 |
| 31 | #define PRID_COMP_SANDCRAFT 0x050000 |
| 32 | #define PRID_COMP_PHILIPS 0x060000 |
| 33 | #define PRID_COMP_TOSHIBA 0x070000 |
| 34 | #define PRID_COMP_LSI 0x080000 |
| 35 | #define PRID_COMP_LEXRA 0x0b0000 |
| 36 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | |
| 38 | /* |
| 39 | * Assigned values for the product ID register. In order to detect a |
| 40 | * certain CPU type exactly eventually additional registers may need to |
| 41 | * be examined. These are valid when 23:16 == PRID_COMP_LEGACY |
| 42 | */ |
| 43 | #define PRID_IMP_R2000 0x0100 |
| 44 | #define PRID_IMP_AU1_REV1 0x0100 |
| 45 | #define PRID_IMP_AU1_REV2 0x0200 |
| 46 | #define PRID_IMP_R3000 0x0200 /* Same as R2000A */ |
| 47 | #define PRID_IMP_R6000 0x0300 /* Same as R3000A */ |
| 48 | #define PRID_IMP_R4000 0x0400 |
| 49 | #define PRID_IMP_R6000A 0x0600 |
| 50 | #define PRID_IMP_R10000 0x0900 |
| 51 | #define PRID_IMP_R4300 0x0b00 |
| 52 | #define PRID_IMP_VR41XX 0x0c00 |
| 53 | #define PRID_IMP_R12000 0x0e00 |
| 54 | #define PRID_IMP_R8000 0x1000 |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 55 | #define PRID_IMP_PR4450 0x1200 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 | #define PRID_IMP_R4600 0x2000 |
| 57 | #define PRID_IMP_R4700 0x2100 |
| 58 | #define PRID_IMP_TX39 0x2200 |
| 59 | #define PRID_IMP_R4640 0x2200 |
| 60 | #define PRID_IMP_R4650 0x2200 /* Same as R4640 */ |
| 61 | #define PRID_IMP_R5000 0x2300 |
| 62 | #define PRID_IMP_TX49 0x2d00 |
| 63 | #define PRID_IMP_SONIC 0x2400 |
| 64 | #define PRID_IMP_MAGIC 0x2500 |
| 65 | #define PRID_IMP_RM7000 0x2700 |
| 66 | #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ |
| 67 | #define PRID_IMP_RM9000 0x3400 |
| 68 | #define PRID_IMP_R5432 0x5400 |
| 69 | #define PRID_IMP_R5500 0x5500 |
Maciej W. Rozycki | 98e316d | 2005-09-05 10:31:27 +0000 | [diff] [blame] | 70 | |
| 71 | #define PRID_IMP_UNKNOWN 0xff00 |
| 72 | |
| 73 | /* |
| 74 | * These are the PRID's for when 23:16 == PRID_COMP_MIPS |
| 75 | */ |
| 76 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | #define PRID_IMP_4KC 0x8000 |
| 78 | #define PRID_IMP_5KC 0x8100 |
| 79 | #define PRID_IMP_20KC 0x8200 |
| 80 | #define PRID_IMP_4KEC 0x8400 |
| 81 | #define PRID_IMP_4KSC 0x8600 |
| 82 | #define PRID_IMP_25KF 0x8800 |
| 83 | #define PRID_IMP_5KE 0x8900 |
| 84 | #define PRID_IMP_4KECR2 0x9000 |
| 85 | #define PRID_IMP_4KEMPR2 0x9100 |
| 86 | #define PRID_IMP_4KSD 0x9200 |
| 87 | #define PRID_IMP_24K 0x9300 |
Ralf Baechle | bbc7f22 | 2005-07-12 16:12:05 +0000 | [diff] [blame] | 88 | #define PRID_IMP_34K 0x9500 |
Ralf Baechle | e50c0a8 | 2005-05-31 11:49:19 +0000 | [diff] [blame] | 89 | #define PRID_IMP_24KE 0x9600 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 90 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | /* |
| 92 | * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE |
| 93 | */ |
| 94 | |
| 95 | #define PRID_IMP_SB1 0x0100 |
Andrew Isaacson | 93ce2f52 | 2005-10-19 23:56:20 -0700 | [diff] [blame] | 96 | #define PRID_IMP_SB1A 0x1100 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | |
| 98 | /* |
| 99 | * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT |
| 100 | */ |
| 101 | |
| 102 | #define PRID_IMP_SR71000 0x0400 |
| 103 | |
| 104 | /* |
| 105 | * Definitions for 7:0 on legacy processors |
| 106 | */ |
| 107 | |
| 108 | |
| 109 | #define PRID_REV_TX4927 0x0022 |
| 110 | #define PRID_REV_TX4937 0x0030 |
| 111 | #define PRID_REV_R4400 0x0040 |
| 112 | #define PRID_REV_R3000A 0x0030 |
| 113 | #define PRID_REV_R3000 0x0020 |
| 114 | #define PRID_REV_R2000A 0x0010 |
| 115 | #define PRID_REV_TX3912 0x0010 |
| 116 | #define PRID_REV_TX3922 0x0030 |
| 117 | #define PRID_REV_TX3927 0x0040 |
| 118 | #define PRID_REV_VR4111 0x0050 |
| 119 | #define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ |
| 120 | #define PRID_REV_VR4121 0x0060 |
| 121 | #define PRID_REV_VR4122 0x0070 |
| 122 | #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ |
| 123 | #define PRID_REV_VR4130 0x0080 |
| 124 | |
| 125 | /* |
| 126 | * FPU implementation/revision register (CP1 control register 0). |
| 127 | * |
| 128 | * +---------------------------------+----------------+----------------+ |
| 129 | * | 0 | Implementation | Revision | |
| 130 | * +---------------------------------+----------------+----------------+ |
| 131 | * 31 16 15 8 7 0 |
| 132 | */ |
| 133 | |
| 134 | #define FPIR_IMP_NONE 0x0000 |
| 135 | |
| 136 | #define CPU_UNKNOWN 0 |
| 137 | #define CPU_R2000 1 |
| 138 | #define CPU_R3000 2 |
| 139 | #define CPU_R3000A 3 |
| 140 | #define CPU_R3041 4 |
| 141 | #define CPU_R3051 5 |
| 142 | #define CPU_R3052 6 |
| 143 | #define CPU_R3081 7 |
| 144 | #define CPU_R3081E 8 |
| 145 | #define CPU_R4000PC 9 |
| 146 | #define CPU_R4000SC 10 |
| 147 | #define CPU_R4000MC 11 |
| 148 | #define CPU_R4200 12 |
| 149 | #define CPU_R4400PC 13 |
| 150 | #define CPU_R4400SC 14 |
| 151 | #define CPU_R4400MC 15 |
| 152 | #define CPU_R4600 16 |
| 153 | #define CPU_R6000 17 |
| 154 | #define CPU_R6000A 18 |
| 155 | #define CPU_R8000 19 |
| 156 | #define CPU_R10000 20 |
| 157 | #define CPU_R12000 21 |
| 158 | #define CPU_R4300 22 |
| 159 | #define CPU_R4650 23 |
| 160 | #define CPU_R4700 24 |
| 161 | #define CPU_R5000 25 |
| 162 | #define CPU_R5000A 26 |
| 163 | #define CPU_R4640 27 |
| 164 | #define CPU_NEVADA 28 |
| 165 | #define CPU_RM7000 29 |
| 166 | #define CPU_R5432 30 |
| 167 | #define CPU_4KC 31 |
| 168 | #define CPU_5KC 32 |
| 169 | #define CPU_R4310 33 |
| 170 | #define CPU_SB1 34 |
| 171 | #define CPU_TX3912 35 |
| 172 | #define CPU_TX3922 36 |
| 173 | #define CPU_TX3927 37 |
| 174 | #define CPU_AU1000 38 |
| 175 | #define CPU_4KEC 39 |
| 176 | #define CPU_4KSC 40 |
| 177 | #define CPU_VR41XX 41 |
| 178 | #define CPU_R5500 42 |
| 179 | #define CPU_TX49XX 43 |
| 180 | #define CPU_AU1500 44 |
| 181 | #define CPU_20KC 45 |
| 182 | #define CPU_VR4111 46 |
| 183 | #define CPU_VR4121 47 |
| 184 | #define CPU_VR4122 48 |
| 185 | #define CPU_VR4131 49 |
| 186 | #define CPU_VR4181 50 |
| 187 | #define CPU_VR4181A 51 |
| 188 | #define CPU_AU1100 52 |
| 189 | #define CPU_SR71000 53 |
| 190 | #define CPU_RM9000 54 |
| 191 | #define CPU_25KF 55 |
| 192 | #define CPU_VR4133 56 |
| 193 | #define CPU_AU1550 57 |
| 194 | #define CPU_24K 58 |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame] | 195 | #define CPU_AU1200 59 |
Ralf Baechle | bbc7f22 | 2005-07-12 16:12:05 +0000 | [diff] [blame] | 196 | #define CPU_34K 60 |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 197 | #define CPU_PR4450 61 |
Andrew Isaacson | 93ce2f52 | 2005-10-19 23:56:20 -0700 | [diff] [blame] | 198 | #define CPU_SB1A 62 |
| 199 | #define CPU_LAST 62 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 200 | |
| 201 | /* |
| 202 | * ISA Level encodings |
| 203 | * |
| 204 | */ |
| 205 | #define MIPS_CPU_ISA_I 0x00000001 |
| 206 | #define MIPS_CPU_ISA_II 0x00000002 |
Maciej W. Rozycki | 9cf8ff9 | 2006-02-13 09:15:49 +0000 | [diff] [blame] | 207 | #define MIPS_CPU_ISA_III 0x00000004 |
| 208 | #define MIPS_CPU_ISA_IV 0x00000008 |
| 209 | #define MIPS_CPU_ISA_V 0x00000010 |
Ralf Baechle | e7958bb | 2005-12-08 13:00:20 +0000 | [diff] [blame] | 210 | #define MIPS_CPU_ISA_M32R1 0x00000020 |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 211 | #define MIPS_CPU_ISA_M32R2 0x00000040 |
Ralf Baechle | 0401572 | 2005-12-09 12:20:49 +0000 | [diff] [blame] | 212 | #define MIPS_CPU_ISA_M64R1 0x00000080 |
| 213 | #define MIPS_CPU_ISA_M64R2 0x00000100 |
| 214 | |
| 215 | #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ |
| 216 | MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) |
| 217 | #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ |
| 218 | MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | |
| 220 | /* |
| 221 | * CPU Option encodings |
| 222 | */ |
| 223 | #define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 224 | #define MIPS_CPU_4KEX 0x00000002 /* "R4K" exception model */ |
| 225 | #define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ |
| 226 | #define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ |
| 227 | #define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ |
| 228 | #define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */ |
| 229 | #define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */ |
| 230 | #define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */ |
| 231 | #define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */ |
| 232 | #define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */ |
| 233 | #define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */ |
| 234 | #define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */ |
| 235 | #define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */ |
| 236 | #define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */ |
| 237 | #define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */ |
| 238 | #define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ |
| 239 | #define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ |
| 240 | #define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ |
| 241 | #define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */ |
| 242 | #define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ |
| 243 | #define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ |
| 244 | #define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 246 | /* |
| 247 | * CPU ASE encodings |
| 248 | */ |
| 249 | #define MIPS_ASE_MIPS16 0x00000001 /* code compression */ |
| 250 | #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ |
| 251 | #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ |
| 252 | #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ |
Ralf Baechle | e50c0a8 | 2005-05-31 11:49:19 +0000 | [diff] [blame] | 253 | #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ |
Ralf Baechle | 8f40611 | 2005-07-14 07:34:18 +0000 | [diff] [blame] | 254 | #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ |
| 255 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 256 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | #endif /* _ASM_CPU_H */ |