Steven A. Falco | 44dab88 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * SPI_PPC4XX SPI controller driver. |
| 3 | * |
| 4 | * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de> |
| 5 | * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering |
| 6 | * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com> |
| 7 | * |
| 8 | * Based in part on drivers/spi/spi_s3c24xx.c |
| 9 | * |
| 10 | * Copyright (c) 2006 Ben Dooks |
| 11 | * Copyright (c) 2006 Simtec Electronics |
| 12 | * Ben Dooks <ben@simtec.co.uk> |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify it |
| 15 | * under the terms of the GNU General Public License version 2 as published |
| 16 | * by the Free Software Foundation. |
| 17 | */ |
| 18 | |
| 19 | /* |
| 20 | * The PPC4xx SPI controller has no FIFO so each sent/received byte will |
| 21 | * generate an interrupt to the CPU. This can cause high CPU utilization. |
| 22 | * This driver allows platforms to reduce the interrupt load on the CPU |
| 23 | * during SPI transfers by setting max_speed_hz via the device tree. |
| 24 | */ |
| 25 | |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/init.h> |
| 28 | #include <linux/sched.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Steven A. Falco | 44dab88 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 30 | #include <linux/errno.h> |
| 31 | #include <linux/wait.h> |
| 32 | #include <linux/of_platform.h> |
| 33 | #include <linux/of_spi.h> |
| 34 | #include <linux/of_gpio.h> |
| 35 | #include <linux/interrupt.h> |
| 36 | #include <linux/delay.h> |
| 37 | |
| 38 | #include <linux/gpio.h> |
| 39 | #include <linux/spi/spi.h> |
| 40 | #include <linux/spi/spi_bitbang.h> |
| 41 | |
| 42 | #include <asm/io.h> |
| 43 | #include <asm/dcr.h> |
| 44 | #include <asm/dcr-regs.h> |
| 45 | |
| 46 | /* bits in mode register - bit 0 is MSb */ |
| 47 | |
| 48 | /* |
| 49 | * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock" |
| 50 | * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock" |
| 51 | * Note: This is the inverse of CPHA. |
| 52 | */ |
| 53 | #define SPI_PPC4XX_MODE_SCP (0x80 >> 3) |
| 54 | |
| 55 | /* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */ |
| 56 | #define SPI_PPC4XX_MODE_SPE (0x80 >> 4) |
| 57 | |
| 58 | /* |
| 59 | * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode |
| 60 | * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode |
| 61 | * Note: This is identical to SPI_LSB_FIRST. |
| 62 | */ |
| 63 | #define SPI_PPC4XX_MODE_RD (0x80 >> 5) |
| 64 | |
| 65 | /* |
| 66 | * SPI_PPC4XX_MODE_CI = 0 means "clock idles low" |
| 67 | * SPI_PPC4XX_MODE_CI = 1 means "clock idles high" |
| 68 | * Note: This is identical to CPOL. |
| 69 | */ |
| 70 | #define SPI_PPC4XX_MODE_CI (0x80 >> 6) |
| 71 | |
| 72 | /* |
| 73 | * SPI_PPC4XX_MODE_IL = 0 means "loopback disable" |
| 74 | * SPI_PPC4XX_MODE_IL = 1 means "loopback enable" |
| 75 | */ |
| 76 | #define SPI_PPC4XX_MODE_IL (0x80 >> 7) |
| 77 | |
| 78 | /* bits in control register */ |
| 79 | /* starts a transfer when set */ |
| 80 | #define SPI_PPC4XX_CR_STR (0x80 >> 7) |
| 81 | |
| 82 | /* bits in status register */ |
| 83 | /* port is busy with a transfer */ |
| 84 | #define SPI_PPC4XX_SR_BSY (0x80 >> 6) |
| 85 | /* RxD ready */ |
| 86 | #define SPI_PPC4XX_SR_RBR (0x80 >> 7) |
| 87 | |
| 88 | /* clock settings (SCP and CI) for various SPI modes */ |
| 89 | #define SPI_CLK_MODE0 (SPI_PPC4XX_MODE_SCP | 0) |
| 90 | #define SPI_CLK_MODE1 (0 | 0) |
| 91 | #define SPI_CLK_MODE2 (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI) |
| 92 | #define SPI_CLK_MODE3 (0 | SPI_PPC4XX_MODE_CI) |
| 93 | |
| 94 | #define DRIVER_NAME "spi_ppc4xx_of" |
| 95 | |
| 96 | struct spi_ppc4xx_regs { |
| 97 | u8 mode; |
| 98 | u8 rxd; |
| 99 | u8 txd; |
| 100 | u8 cr; |
| 101 | u8 sr; |
| 102 | u8 dummy; |
| 103 | /* |
| 104 | * Clock divisor modulus register |
| 105 | * This uses the follwing formula: |
| 106 | * SCPClkOut = OPBCLK/(4(CDM + 1)) |
| 107 | * or |
| 108 | * CDM = (OPBCLK/4*SCPClkOut) - 1 |
| 109 | * bit 0 is the MSb! |
| 110 | */ |
| 111 | u8 cdm; |
| 112 | }; |
| 113 | |
| 114 | /* SPI Controller driver's private data. */ |
| 115 | struct ppc4xx_spi { |
| 116 | /* bitbang has to be first */ |
| 117 | struct spi_bitbang bitbang; |
| 118 | struct completion done; |
| 119 | |
| 120 | u64 mapbase; |
| 121 | u64 mapsize; |
| 122 | int irqnum; |
| 123 | /* need this to set the SPI clock */ |
| 124 | unsigned int opb_freq; |
| 125 | |
| 126 | /* for transfers */ |
| 127 | int len; |
| 128 | int count; |
| 129 | /* data buffers */ |
| 130 | const unsigned char *tx; |
| 131 | unsigned char *rx; |
| 132 | |
| 133 | int *gpios; |
| 134 | |
| 135 | struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */ |
| 136 | struct spi_master *master; |
| 137 | struct device *dev; |
| 138 | }; |
| 139 | |
| 140 | /* need this so we can set the clock in the chipselect routine */ |
| 141 | struct spi_ppc4xx_cs { |
| 142 | u8 mode; |
| 143 | }; |
| 144 | |
| 145 | static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t) |
| 146 | { |
| 147 | struct ppc4xx_spi *hw; |
| 148 | u8 data; |
| 149 | |
| 150 | dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", |
| 151 | t->tx_buf, t->rx_buf, t->len); |
| 152 | |
| 153 | hw = spi_master_get_devdata(spi->master); |
| 154 | |
| 155 | hw->tx = t->tx_buf; |
| 156 | hw->rx = t->rx_buf; |
| 157 | hw->len = t->len; |
| 158 | hw->count = 0; |
| 159 | |
| 160 | /* send the first byte */ |
| 161 | data = hw->tx ? hw->tx[0] : 0; |
| 162 | out_8(&hw->regs->txd, data); |
| 163 | out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); |
| 164 | wait_for_completion(&hw->done); |
| 165 | |
| 166 | return hw->count; |
| 167 | } |
| 168 | |
| 169 | static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t) |
| 170 | { |
| 171 | struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master); |
| 172 | struct spi_ppc4xx_cs *cs = spi->controller_state; |
| 173 | int scr; |
| 174 | u8 cdm = 0; |
| 175 | u32 speed; |
| 176 | u8 bits_per_word; |
| 177 | |
| 178 | /* Start with the generic configuration for this device. */ |
| 179 | bits_per_word = spi->bits_per_word; |
| 180 | speed = spi->max_speed_hz; |
| 181 | |
| 182 | /* |
| 183 | * Modify the configuration if the transfer overrides it. Do not allow |
| 184 | * the transfer to overwrite the generic configuration with zeros. |
| 185 | */ |
| 186 | if (t) { |
| 187 | if (t->bits_per_word) |
| 188 | bits_per_word = t->bits_per_word; |
| 189 | |
| 190 | if (t->speed_hz) |
| 191 | speed = min(t->speed_hz, spi->max_speed_hz); |
| 192 | } |
| 193 | |
| 194 | if (bits_per_word != 8) { |
| 195 | dev_err(&spi->dev, "invalid bits-per-word (%d)\n", |
| 196 | bits_per_word); |
| 197 | return -EINVAL; |
| 198 | } |
| 199 | |
| 200 | if (!speed || (speed > spi->max_speed_hz)) { |
| 201 | dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed); |
| 202 | return -EINVAL; |
| 203 | } |
| 204 | |
| 205 | /* Write new configration */ |
| 206 | out_8(&hw->regs->mode, cs->mode); |
| 207 | |
| 208 | /* Set the clock */ |
| 209 | /* opb_freq was already divided by 4 */ |
| 210 | scr = (hw->opb_freq / speed) - 1; |
| 211 | if (scr > 0) |
| 212 | cdm = min(scr, 0xff); |
| 213 | |
| 214 | dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed); |
| 215 | |
| 216 | if (in_8(&hw->regs->cdm) != cdm) |
| 217 | out_8(&hw->regs->cdm, cdm); |
| 218 | |
| 219 | spin_lock(&hw->bitbang.lock); |
| 220 | if (!hw->bitbang.busy) { |
| 221 | hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); |
| 222 | /* Need to ndelay here? */ |
| 223 | } |
| 224 | spin_unlock(&hw->bitbang.lock); |
| 225 | |
| 226 | return 0; |
| 227 | } |
| 228 | |
| 229 | static int spi_ppc4xx_setup(struct spi_device *spi) |
| 230 | { |
| 231 | struct spi_ppc4xx_cs *cs = spi->controller_state; |
| 232 | |
| 233 | if (spi->bits_per_word != 8) { |
| 234 | dev_err(&spi->dev, "invalid bits-per-word (%d)\n", |
| 235 | spi->bits_per_word); |
| 236 | return -EINVAL; |
| 237 | } |
| 238 | |
| 239 | if (!spi->max_speed_hz) { |
| 240 | dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n"); |
| 241 | return -EINVAL; |
| 242 | } |
| 243 | |
| 244 | if (cs == NULL) { |
| 245 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
| 246 | if (!cs) |
| 247 | return -ENOMEM; |
| 248 | spi->controller_state = cs; |
| 249 | } |
| 250 | |
| 251 | /* |
| 252 | * We set all bits of the SPI0_MODE register, so, |
| 253 | * no need to read-modify-write |
| 254 | */ |
| 255 | cs->mode = SPI_PPC4XX_MODE_SPE; |
| 256 | |
| 257 | switch (spi->mode & (SPI_CPHA | SPI_CPOL)) { |
| 258 | case SPI_MODE_0: |
| 259 | cs->mode |= SPI_CLK_MODE0; |
| 260 | break; |
| 261 | case SPI_MODE_1: |
| 262 | cs->mode |= SPI_CLK_MODE1; |
| 263 | break; |
| 264 | case SPI_MODE_2: |
| 265 | cs->mode |= SPI_CLK_MODE2; |
| 266 | break; |
| 267 | case SPI_MODE_3: |
| 268 | cs->mode |= SPI_CLK_MODE3; |
| 269 | break; |
| 270 | } |
| 271 | |
| 272 | if (spi->mode & SPI_LSB_FIRST) |
| 273 | cs->mode |= SPI_PPC4XX_MODE_RD; |
| 274 | |
| 275 | return 0; |
| 276 | } |
| 277 | |
| 278 | static void spi_ppc4xx_chipsel(struct spi_device *spi, int value) |
| 279 | { |
| 280 | struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master); |
| 281 | unsigned int cs = spi->chip_select; |
| 282 | unsigned int cspol; |
| 283 | |
| 284 | /* |
| 285 | * If there are no chip selects at all, or if this is the special |
| 286 | * case of a non-existent (dummy) chip select, do nothing. |
| 287 | */ |
| 288 | |
| 289 | if (!hw->master->num_chipselect || hw->gpios[cs] == -EEXIST) |
| 290 | return; |
| 291 | |
| 292 | cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; |
| 293 | if (value == BITBANG_CS_INACTIVE) |
| 294 | cspol = !cspol; |
| 295 | |
| 296 | gpio_set_value(hw->gpios[cs], cspol); |
| 297 | } |
| 298 | |
| 299 | static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id) |
| 300 | { |
| 301 | struct ppc4xx_spi *hw; |
| 302 | u8 status; |
| 303 | u8 data; |
| 304 | unsigned int count; |
| 305 | |
| 306 | hw = (struct ppc4xx_spi *)dev_id; |
| 307 | |
| 308 | status = in_8(&hw->regs->sr); |
| 309 | if (!status) |
| 310 | return IRQ_NONE; |
| 311 | |
| 312 | /* |
| 313 | * BSY de-asserts one cycle after the transfer is complete. The |
| 314 | * interrupt is asserted after the transfer is complete. The exact |
| 315 | * relationship is not documented, hence this code. |
| 316 | */ |
| 317 | |
| 318 | if (unlikely(status & SPI_PPC4XX_SR_BSY)) { |
| 319 | u8 lstatus; |
| 320 | int cnt = 0; |
| 321 | |
| 322 | dev_dbg(hw->dev, "got interrupt but spi still busy?\n"); |
| 323 | do { |
| 324 | ndelay(10); |
| 325 | lstatus = in_8(&hw->regs->sr); |
| 326 | } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY); |
| 327 | |
| 328 | if (cnt >= 100) { |
| 329 | dev_err(hw->dev, "busywait: too many loops!\n"); |
| 330 | complete(&hw->done); |
| 331 | return IRQ_HANDLED; |
| 332 | } else { |
| 333 | /* status is always 1 (RBR) here */ |
| 334 | status = in_8(&hw->regs->sr); |
| 335 | dev_dbg(hw->dev, "loops %d status %x\n", cnt, status); |
| 336 | } |
| 337 | } |
| 338 | |
| 339 | count = hw->count; |
| 340 | hw->count++; |
| 341 | |
| 342 | /* RBR triggered this interrupt. Therefore, data must be ready. */ |
| 343 | data = in_8(&hw->regs->rxd); |
| 344 | if (hw->rx) |
| 345 | hw->rx[count] = data; |
| 346 | |
| 347 | count++; |
| 348 | |
| 349 | if (count < hw->len) { |
| 350 | data = hw->tx ? hw->tx[count] : 0; |
| 351 | out_8(&hw->regs->txd, data); |
| 352 | out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR); |
| 353 | } else { |
| 354 | complete(&hw->done); |
| 355 | } |
| 356 | |
| 357 | return IRQ_HANDLED; |
| 358 | } |
| 359 | |
| 360 | static void spi_ppc4xx_cleanup(struct spi_device *spi) |
| 361 | { |
| 362 | kfree(spi->controller_state); |
| 363 | } |
| 364 | |
| 365 | static void spi_ppc4xx_enable(struct ppc4xx_spi *hw) |
| 366 | { |
| 367 | /* |
| 368 | * On all 4xx PPC's the SPI bus is shared/multiplexed with |
| 369 | * the 2nd I2C bus. We need to enable the the SPI bus before |
| 370 | * using it. |
| 371 | */ |
| 372 | |
| 373 | /* need to clear bit 14 to enable SPC */ |
| 374 | dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0); |
| 375 | } |
| 376 | |
| 377 | static void free_gpios(struct ppc4xx_spi *hw) |
| 378 | { |
| 379 | if (hw->master->num_chipselect) { |
| 380 | int i; |
| 381 | for (i = 0; i < hw->master->num_chipselect; i++) |
| 382 | if (gpio_is_valid(hw->gpios[i])) |
| 383 | gpio_free(hw->gpios[i]); |
| 384 | |
| 385 | kfree(hw->gpios); |
| 386 | hw->gpios = NULL; |
| 387 | } |
| 388 | } |
| 389 | |
| 390 | /* |
Grant Likely | 2dc1158 | 2010-08-06 09:25:50 -0600 | [diff] [blame] | 391 | * platform_device layer stuff... |
Steven A. Falco | 44dab88 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 392 | */ |
Grant Likely | 18d306d | 2011-02-22 21:02:43 -0700 | [diff] [blame] | 393 | static int __init spi_ppc4xx_of_probe(struct platform_device *op) |
Steven A. Falco | 44dab88 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 394 | { |
| 395 | struct ppc4xx_spi *hw; |
| 396 | struct spi_master *master; |
| 397 | struct spi_bitbang *bbp; |
| 398 | struct resource resource; |
Grant Likely | b535507 | 2010-05-25 23:24:02 -0600 | [diff] [blame] | 399 | struct device_node *np = op->dev.of_node; |
Steven A. Falco | 44dab88 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 400 | struct device *dev = &op->dev; |
| 401 | struct device_node *opbnp; |
| 402 | int ret; |
| 403 | int num_gpios; |
| 404 | const unsigned int *clk; |
| 405 | |
| 406 | master = spi_alloc_master(dev, sizeof *hw); |
| 407 | if (master == NULL) |
| 408 | return -ENOMEM; |
Anatolij Gustschin | 12b15e8 | 2010-07-27 22:35:58 +0200 | [diff] [blame] | 409 | master->dev.of_node = np; |
Steven A. Falco | 44dab88 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 410 | dev_set_drvdata(dev, master); |
| 411 | hw = spi_master_get_devdata(master); |
| 412 | hw->master = spi_master_get(master); |
| 413 | hw->dev = dev; |
| 414 | |
| 415 | init_completion(&hw->done); |
| 416 | |
| 417 | /* |
| 418 | * A count of zero implies a single SPI device without any chip-select. |
| 419 | * Note that of_gpio_count counts all gpios assigned to this spi master. |
| 420 | * This includes both "null" gpio's and real ones. |
| 421 | */ |
| 422 | num_gpios = of_gpio_count(np); |
| 423 | if (num_gpios) { |
| 424 | int i; |
| 425 | |
| 426 | hw->gpios = kzalloc(sizeof(int) * num_gpios, GFP_KERNEL); |
| 427 | if (!hw->gpios) { |
| 428 | ret = -ENOMEM; |
| 429 | goto free_master; |
| 430 | } |
| 431 | |
| 432 | for (i = 0; i < num_gpios; i++) { |
| 433 | int gpio; |
| 434 | enum of_gpio_flags flags; |
| 435 | |
| 436 | gpio = of_get_gpio_flags(np, i, &flags); |
| 437 | hw->gpios[i] = gpio; |
| 438 | |
| 439 | if (gpio_is_valid(gpio)) { |
| 440 | /* Real CS - set the initial state. */ |
| 441 | ret = gpio_request(gpio, np->name); |
| 442 | if (ret < 0) { |
| 443 | dev_err(dev, "can't request gpio " |
| 444 | "#%d: %d\n", i, ret); |
| 445 | goto free_gpios; |
| 446 | } |
| 447 | |
| 448 | gpio_direction_output(gpio, |
| 449 | !!(flags & OF_GPIO_ACTIVE_LOW)); |
| 450 | } else if (gpio == -EEXIST) { |
| 451 | ; /* No CS, but that's OK. */ |
| 452 | } else { |
| 453 | dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); |
| 454 | ret = -EINVAL; |
| 455 | goto free_gpios; |
| 456 | } |
| 457 | } |
| 458 | } |
| 459 | |
| 460 | /* Setup the state for the bitbang driver */ |
| 461 | bbp = &hw->bitbang; |
| 462 | bbp->master = hw->master; |
| 463 | bbp->setup_transfer = spi_ppc4xx_setupxfer; |
| 464 | bbp->chipselect = spi_ppc4xx_chipsel; |
| 465 | bbp->txrx_bufs = spi_ppc4xx_txrx; |
| 466 | bbp->use_dma = 0; |
| 467 | bbp->master->setup = spi_ppc4xx_setup; |
| 468 | bbp->master->cleanup = spi_ppc4xx_cleanup; |
| 469 | |
| 470 | /* Allocate bus num dynamically. */ |
| 471 | bbp->master->bus_num = -1; |
| 472 | |
| 473 | /* the spi->mode bits understood by this driver: */ |
| 474 | bbp->master->mode_bits = |
| 475 | SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST; |
| 476 | |
| 477 | /* this many pins in all GPIO controllers */ |
| 478 | bbp->master->num_chipselect = num_gpios; |
| 479 | |
| 480 | /* Get the clock for the OPB */ |
| 481 | opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb"); |
| 482 | if (opbnp == NULL) { |
| 483 | dev_err(dev, "OPB: cannot find node\n"); |
| 484 | ret = -ENODEV; |
| 485 | goto free_gpios; |
| 486 | } |
| 487 | /* Get the clock (Hz) for the OPB */ |
| 488 | clk = of_get_property(opbnp, "clock-frequency", NULL); |
| 489 | if (clk == NULL) { |
| 490 | dev_err(dev, "OPB: no clock-frequency property set\n"); |
| 491 | of_node_put(opbnp); |
| 492 | ret = -ENODEV; |
| 493 | goto free_gpios; |
| 494 | } |
| 495 | hw->opb_freq = *clk; |
| 496 | hw->opb_freq >>= 2; |
| 497 | of_node_put(opbnp); |
| 498 | |
| 499 | ret = of_address_to_resource(np, 0, &resource); |
| 500 | if (ret) { |
| 501 | dev_err(dev, "error while parsing device node resource\n"); |
| 502 | goto free_gpios; |
| 503 | } |
| 504 | hw->mapbase = resource.start; |
| 505 | hw->mapsize = resource.end - resource.start + 1; |
| 506 | |
| 507 | /* Sanity check */ |
| 508 | if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) { |
| 509 | dev_err(dev, "too small to map registers\n"); |
| 510 | ret = -EINVAL; |
| 511 | goto free_gpios; |
| 512 | } |
| 513 | |
| 514 | /* Request IRQ */ |
| 515 | hw->irqnum = irq_of_parse_and_map(np, 0); |
| 516 | ret = request_irq(hw->irqnum, spi_ppc4xx_int, |
| 517 | IRQF_DISABLED, "spi_ppc4xx_of", (void *)hw); |
| 518 | if (ret) { |
| 519 | dev_err(dev, "unable to allocate interrupt\n"); |
| 520 | goto free_gpios; |
| 521 | } |
| 522 | |
| 523 | if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) { |
| 524 | dev_err(dev, "resource unavailable\n"); |
| 525 | ret = -EBUSY; |
| 526 | goto request_mem_error; |
| 527 | } |
| 528 | |
| 529 | hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs)); |
| 530 | |
| 531 | if (!hw->regs) { |
| 532 | dev_err(dev, "unable to memory map registers\n"); |
| 533 | ret = -ENXIO; |
| 534 | goto map_io_error; |
| 535 | } |
| 536 | |
| 537 | spi_ppc4xx_enable(hw); |
| 538 | |
| 539 | /* Finally register our spi controller */ |
| 540 | dev->dma_mask = 0; |
| 541 | ret = spi_bitbang_start(bbp); |
| 542 | if (ret) { |
| 543 | dev_err(dev, "failed to register SPI master\n"); |
| 544 | goto unmap_regs; |
| 545 | } |
| 546 | |
| 547 | dev_info(dev, "driver initialized\n"); |
Steven A. Falco | 44dab88 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 548 | |
| 549 | return 0; |
| 550 | |
| 551 | unmap_regs: |
| 552 | iounmap(hw->regs); |
| 553 | map_io_error: |
| 554 | release_mem_region(hw->mapbase, hw->mapsize); |
| 555 | request_mem_error: |
| 556 | free_irq(hw->irqnum, hw); |
| 557 | free_gpios: |
| 558 | free_gpios(hw); |
| 559 | free_master: |
| 560 | dev_set_drvdata(dev, NULL); |
| 561 | spi_master_put(master); |
| 562 | |
| 563 | dev_err(dev, "initialization failed\n"); |
| 564 | return ret; |
| 565 | } |
| 566 | |
Grant Likely | 2dc1158 | 2010-08-06 09:25:50 -0600 | [diff] [blame] | 567 | static int __exit spi_ppc4xx_of_remove(struct platform_device *op) |
Steven A. Falco | 44dab88 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 568 | { |
| 569 | struct spi_master *master = dev_get_drvdata(&op->dev); |
| 570 | struct ppc4xx_spi *hw = spi_master_get_devdata(master); |
| 571 | |
| 572 | spi_bitbang_stop(&hw->bitbang); |
| 573 | dev_set_drvdata(&op->dev, NULL); |
| 574 | release_mem_region(hw->mapbase, hw->mapsize); |
| 575 | free_irq(hw->irqnum, hw); |
| 576 | iounmap(hw->regs); |
| 577 | free_gpios(hw); |
| 578 | return 0; |
| 579 | } |
| 580 | |
Márton Németh | 631e61b | 2010-01-20 13:49:44 -0700 | [diff] [blame] | 581 | static const struct of_device_id spi_ppc4xx_of_match[] = { |
Steven A. Falco | 44dab88 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 582 | { .compatible = "ibm,ppc4xx-spi", }, |
| 583 | {}, |
| 584 | }; |
| 585 | |
| 586 | MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match); |
| 587 | |
Grant Likely | 18d306d | 2011-02-22 21:02:43 -0700 | [diff] [blame] | 588 | static struct platform_driver spi_ppc4xx_of_driver = { |
Steven A. Falco | 44dab88 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 589 | .probe = spi_ppc4xx_of_probe, |
| 590 | .remove = __exit_p(spi_ppc4xx_of_remove), |
| 591 | .driver = { |
| 592 | .name = DRIVER_NAME, |
| 593 | .owner = THIS_MODULE, |
Grant Likely | 4018294 | 2010-04-13 16:13:02 -0700 | [diff] [blame] | 594 | .of_match_table = spi_ppc4xx_of_match, |
Steven A. Falco | 44dab88 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 595 | }, |
| 596 | }; |
| 597 | |
| 598 | static int __init spi_ppc4xx_init(void) |
| 599 | { |
Grant Likely | 18d306d | 2011-02-22 21:02:43 -0700 | [diff] [blame] | 600 | return platform_driver_register(&spi_ppc4xx_of_driver); |
Steven A. Falco | 44dab88 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 601 | } |
| 602 | module_init(spi_ppc4xx_init); |
| 603 | |
| 604 | static void __exit spi_ppc4xx_exit(void) |
| 605 | { |
Grant Likely | 18d306d | 2011-02-22 21:02:43 -0700 | [diff] [blame] | 606 | platform_driver_unregister(&spi_ppc4xx_of_driver); |
Steven A. Falco | 44dab88 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 607 | } |
| 608 | module_exit(spi_ppc4xx_exit); |
| 609 | |
| 610 | MODULE_AUTHOR("Gary Jennejohn & Stefan Roese"); |
| 611 | MODULE_DESCRIPTION("Simple PPC4xx SPI Driver"); |
| 612 | MODULE_LICENSE("GPL"); |