Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * This program is free software; you can redistribute it and/or modify it |
| 3 | * under the terms of the GNU General Public License as published by the |
| 4 | * Free Software Foundation; either version 2 of the License, or (at your |
| 5 | * option) any later version. |
Ralf Baechle | 27f7681 | 2006-10-09 00:03:05 +0100 | [diff] [blame] | 6 | * |
| 7 | * Copyright (c) 2004 MIPS Inc |
| 8 | * Author: chris@mips.com |
| 9 | * |
| 10 | * Copyright (C) 2004, 06 Ralf Baechle <ralf@linux-mips.org> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | */ |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/kernel.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | #include <linux/sched.h> |
| 16 | #include <linux/kernel_stat.h> |
| 17 | #include <asm/io.h> |
| 18 | #include <asm/irq.h> |
| 19 | #include <asm/msc01_ic.h> |
Atsushi Nemoto | 411ba7f | 2008-04-26 01:55:30 +0900 | [diff] [blame] | 20 | #include <asm/traps.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | |
| 22 | static unsigned long _icctrl_msc; |
| 23 | #define MSC01_IC_REG_BASE _icctrl_msc |
| 24 | |
| 25 | #define MSCIC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0) |
| 26 | #define MSCIC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0) |
| 27 | |
| 28 | static unsigned int irq_base; |
| 29 | |
| 30 | /* mask off an interrupt */ |
| 31 | static inline void mask_msc_irq(unsigned int irq) |
| 32 | { |
| 33 | if (irq < (irq_base + 32)) |
| 34 | MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base)); |
| 35 | else |
| 36 | MSCIC_WRITE(MSC01_IC_DISH, 1<<(irq - irq_base - 32)); |
| 37 | } |
| 38 | |
| 39 | /* unmask an interrupt */ |
| 40 | static inline void unmask_msc_irq(unsigned int irq) |
| 41 | { |
| 42 | if (irq < (irq_base + 32)) |
| 43 | MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base)); |
| 44 | else |
| 45 | MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32)); |
| 46 | } |
| 47 | |
| 48 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | * Masks and ACKs an IRQ |
| 50 | */ |
| 51 | static void level_mask_and_ack_msc_irq(unsigned int irq) |
| 52 | { |
| 53 | mask_msc_irq(irq); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 54 | if (!cpu_has_veic) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | MSCIC_WRITE(MSC01_IC_EOI, 0); |
Ralf Baechle | 41c594a | 2006-04-05 09:45:45 +0100 | [diff] [blame] | 56 | /* This actually needs to be a call into platform code */ |
Ralf Baechle | 1146fe3 | 2007-09-21 17:13:55 +0100 | [diff] [blame] | 57 | smtc_im_ack_irq(irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 58 | } |
| 59 | |
| 60 | /* |
| 61 | * Masks and ACKs an IRQ |
| 62 | */ |
| 63 | static void edge_mask_and_ack_msc_irq(unsigned int irq) |
| 64 | { |
| 65 | mask_msc_irq(irq); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 66 | if (!cpu_has_veic) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 67 | MSCIC_WRITE(MSC01_IC_EOI, 0); |
| 68 | else { |
| 69 | u32 r; |
| 70 | MSCIC_READ(MSC01_IC_SUP+irq*8, r); |
| 71 | MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT); |
| 72 | MSCIC_WRITE(MSC01_IC_SUP+irq*8, r); |
| 73 | } |
Ralf Baechle | 1146fe3 | 2007-09-21 17:13:55 +0100 | [diff] [blame] | 74 | smtc_im_ack_irq(irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | /* |
| 78 | * End IRQ processing |
| 79 | */ |
| 80 | static void end_msc_irq(unsigned int irq) |
| 81 | { |
| 82 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) |
| 83 | unmask_msc_irq(irq); |
| 84 | } |
| 85 | |
| 86 | /* |
| 87 | * Interrupt handler for interrupts coming from SOC-it. |
| 88 | */ |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 89 | void ll_msc_irq(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 90 | { |
| 91 | unsigned int irq; |
| 92 | |
| 93 | /* read the interrupt vector register */ |
| 94 | MSCIC_READ(MSC01_IC_VEC, irq); |
| 95 | if (irq < 64) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 96 | do_IRQ(irq + irq_base); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | else { |
| 98 | /* Ignore spurious interrupt */ |
| 99 | } |
| 100 | } |
| 101 | |
Atsushi Nemoto | 411ba7f | 2008-04-26 01:55:30 +0900 | [diff] [blame] | 102 | static void msc_bind_eic_interrupt(int irq, int set) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | { |
| 104 | MSCIC_WRITE(MSC01_IC_RAMW, |
| 105 | (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); |
| 106 | } |
| 107 | |
Atsushi Nemoto | 411ba7f | 2008-04-26 01:55:30 +0900 | [diff] [blame] | 108 | static struct irq_chip msc_levelirq_type = { |
Atsushi Nemoto | 70d21cd | 2007-01-15 00:07:25 +0900 | [diff] [blame] | 109 | .name = "SOC-it-Level", |
Ralf Baechle | 8ab00b9 | 2005-02-28 13:39:57 +0000 | [diff] [blame] | 110 | .ack = level_mask_and_ack_msc_irq, |
Atsushi Nemoto | 1603b5a | 2006-11-02 02:08:36 +0900 | [diff] [blame] | 111 | .mask = mask_msc_irq, |
| 112 | .mask_ack = level_mask_and_ack_msc_irq, |
| 113 | .unmask = unmask_msc_irq, |
Atsushi Nemoto | 1417836 | 2006-11-14 01:13:18 +0900 | [diff] [blame] | 114 | .eoi = unmask_msc_irq, |
Ralf Baechle | 8ab00b9 | 2005-02-28 13:39:57 +0000 | [diff] [blame] | 115 | .end = end_msc_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | }; |
| 117 | |
Atsushi Nemoto | 411ba7f | 2008-04-26 01:55:30 +0900 | [diff] [blame] | 118 | static struct irq_chip msc_edgeirq_type = { |
Atsushi Nemoto | 70d21cd | 2007-01-15 00:07:25 +0900 | [diff] [blame] | 119 | .name = "SOC-it-Edge", |
Ralf Baechle | 8ab00b9 | 2005-02-28 13:39:57 +0000 | [diff] [blame] | 120 | .ack = edge_mask_and_ack_msc_irq, |
Atsushi Nemoto | 1603b5a | 2006-11-02 02:08:36 +0900 | [diff] [blame] | 121 | .mask = mask_msc_irq, |
| 122 | .mask_ack = edge_mask_and_ack_msc_irq, |
| 123 | .unmask = unmask_msc_irq, |
Atsushi Nemoto | 1417836 | 2006-11-14 01:13:18 +0900 | [diff] [blame] | 124 | .eoi = unmask_msc_irq, |
Ralf Baechle | 8ab00b9 | 2005-02-28 13:39:57 +0000 | [diff] [blame] | 125 | .end = end_msc_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 126 | }; |
| 127 | |
| 128 | |
Chris Dearman | d725cf3 | 2007-05-08 14:05:39 +0100 | [diff] [blame] | 129 | void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqmap_t *imp, int nirq) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | { |
Ralf Baechle | 49a89ef | 2007-10-11 23:46:15 +0100 | [diff] [blame] | 131 | _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | |
| 133 | /* Reset interrupt controller - initialises all registers to 0 */ |
| 134 | MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); |
| 135 | |
| 136 | board_bind_eic_interrupt = &msc_bind_eic_interrupt; |
| 137 | |
| 138 | for (; nirq >= 0; nirq--, imp++) { |
| 139 | int n = imp->im_irq; |
| 140 | |
| 141 | switch (imp->im_type) { |
| 142 | case MSC01_IRQ_EDGE: |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 143 | set_irq_chip_and_handler_name(irqbase + n, |
| 144 | &msc_edgeirq_type, handle_edge_irq, "edge"); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 145 | if (cpu_has_veic) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); |
| 147 | else |
| 148 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); |
| 149 | break; |
| 150 | case MSC01_IRQ_LEVEL: |
Ralf Baechle | c87e090 | 2009-03-30 14:49:44 +0200 | [diff] [blame] | 151 | set_irq_chip_and_handler_name(irqbase+n, |
| 152 | &msc_levelirq_type, handle_level_irq, "level"); |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 153 | if (cpu_has_veic) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 154 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); |
| 155 | else |
| 156 | MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl); |
| 157 | } |
| 158 | } |
| 159 | |
Chris Dearman | d725cf3 | 2007-05-08 14:05:39 +0100 | [diff] [blame] | 160 | irq_base = irqbase; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 161 | |
| 162 | MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */ |
| 163 | |
| 164 | } |