blob: e8d88567680718167cf2fe389dbe4af3e0155887 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
Hyok S. Choiafeb90c2006-01-13 21:05:25 +00006 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
Nicolas Pitre70b6f2b2007-12-04 14:33:33 +010014 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
Linus Torvalds1da177e2005-04-16 15:20:36 -070016 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070017
Nicolas Pitref09b9972005-10-29 21:44:55 +010018#include <asm/memory.h>
Russell King753790e2011-02-06 15:32:24 +000019#include <asm/glue-df.h>
20#include <asm/glue-pf.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <asm/vfpmacros.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010022#include <mach/entry-macro.S>
Russell Kingd6551e82006-06-21 13:31:52 +010023#include <asm/thread_notify.h>
Catalin Marinasc4c57162009-02-16 11:42:09 +010024#include <asm/unwind.h>
Russell Kingcc20d422009-11-09 23:53:29 +000025#include <asm/unistd.h>
Tony Lindgrenf159f4e2010-07-05 14:53:10 +010026#include <asm/tls.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
28#include "entry-header.S"
Magnus Dammcd544ce2010-12-22 13:20:08 +010029#include <asm/entry-macro-multi.S>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
31/*
Russell King187a51a2005-05-21 18:14:44 +010032 * Interrupt handling. Preserves r7, r8, r9
33 */
34 .macro irq_handler
eric miao52108642010-12-13 09:42:34 +010035#ifdef CONFIG_MULTI_IRQ_HANDLER
36 ldr r5, =handle_arch_irq
37 mov r0, sp
38 ldr r5, [r5]
39 adr lr, BSYM(9997f)
40 teq r5, #0
41 movne pc, r5
Russell King37ee16a2005-11-08 19:08:05 +000042#endif
Magnus Dammcd544ce2010-12-22 13:20:08 +010043 arch_irq_handler_default
Russell Kingf00ec482010-09-04 10:47:48 +0100449997:
Russell King187a51a2005-05-21 18:14:44 +010045 .endm
46
Nicolas Pitre785d3cd2007-12-03 15:27:56 -050047#ifdef CONFIG_KPROBES
48 .section .kprobes.text,"ax",%progbits
49#else
50 .text
51#endif
52
Russell King187a51a2005-05-21 18:14:44 +010053/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070054 * Invalid mode handlers
55 */
Russell Kingccea7a12005-05-31 22:22:32 +010056 .macro inv_entry, reason
57 sub sp, sp, #S_FRAME_SIZE
Catalin Marinasb86040a2009-07-24 12:32:54 +010058 ARM( stmib sp, {r1 - lr} )
59 THUMB( stmia sp, {r0 - r12} )
60 THUMB( str sp, [sp, #S_SP] )
61 THUMB( str lr, [sp, #S_LR] )
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 mov r1, #\reason
63 .endm
64
65__pabt_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +010066 inv_entry BAD_PREFETCH
67 b common_invalid
Catalin Marinas93ed3972008-08-28 11:22:32 +010068ENDPROC(__pabt_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -070069
70__dabt_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +010071 inv_entry BAD_DATA
72 b common_invalid
Catalin Marinas93ed3972008-08-28 11:22:32 +010073ENDPROC(__dabt_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -070074
75__irq_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +010076 inv_entry BAD_IRQ
77 b common_invalid
Catalin Marinas93ed3972008-08-28 11:22:32 +010078ENDPROC(__irq_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -070079
80__und_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +010081 inv_entry BAD_UNDEFINSTR
Linus Torvalds1da177e2005-04-16 15:20:36 -070082
Russell Kingccea7a12005-05-31 22:22:32 +010083 @
84 @ XXX fall through to common_invalid
85 @
86
87@
88@ common_invalid - generic code for failed exception (re-entrant version of handlers)
89@
90common_invalid:
91 zero_fp
92
93 ldmia r0, {r4 - r6}
94 add r0, sp, #S_PC @ here for interlock avoidance
95 mov r7, #-1 @ "" "" "" ""
96 str r4, [sp] @ save preserved r0
97 stmia r0, {r5 - r7} @ lr_<exception>,
98 @ cpsr_<exception>, "old_r0"
99
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100 mov r0, sp
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101 b bad_mode
Catalin Marinas93ed3972008-08-28 11:22:32 +0100102ENDPROC(__und_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103
104/*
105 * SVC mode handlers
106 */
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000107
108#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
109#define SPFIX(code...) code
110#else
111#define SPFIX(code...)
112#endif
113
Nicolas Pitred30a0c82007-12-14 15:56:01 -0500114 .macro svc_entry, stack_hole=0
Catalin Marinasc4c57162009-02-16 11:42:09 +0100115 UNWIND(.fnstart )
116 UNWIND(.save {r0 - pc} )
Catalin Marinasb86040a2009-07-24 12:32:54 +0100117 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
118#ifdef CONFIG_THUMB2_KERNEL
119 SPFIX( str r0, [sp] ) @ temporarily saved
120 SPFIX( mov r0, sp )
121 SPFIX( tst r0, #4 ) @ test original stack alignment
122 SPFIX( ldr r0, [sp] ) @ restored
123#else
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000124 SPFIX( tst sp, #4 )
Catalin Marinasb86040a2009-07-24 12:32:54 +0100125#endif
126 SPFIX( subeq sp, sp, #4 )
127 stmia sp, {r1 - r12}
Russell Kingccea7a12005-05-31 22:22:32 +0100128
129 ldmia r0, {r1 - r3}
Catalin Marinasb86040a2009-07-24 12:32:54 +0100130 add r5, sp, #S_SP - 4 @ here for interlock avoidance
Russell Kingccea7a12005-05-31 22:22:32 +0100131 mov r4, #-1 @ "" "" "" ""
Catalin Marinasb86040a2009-07-24 12:32:54 +0100132 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
133 SPFIX( addeq r0, r0, #4 )
134 str r1, [sp, #-4]! @ save the "real" r0 copied
Russell Kingccea7a12005-05-31 22:22:32 +0100135 @ from the exception stack
136
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137 mov r1, lr
138
139 @
140 @ We are now ready to fill in the remaining blanks on the stack:
141 @
142 @ r0 - sp_svc
143 @ r1 - lr_svc
144 @ r2 - lr_<exception>, already fixed up for correct return/restart
145 @ r3 - spsr_<exception>
146 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
147 @
148 stmia r5, {r0 - r4}
149 .endm
150
151 .align 5
152__dabt_svc:
Russell Kingccea7a12005-05-31 22:22:32 +0100153 svc_entry
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154
155 @
156 @ get ready to re-enable interrupts if appropriate
157 @
158 mrs r9, cpsr
159 tst r3, #PSR_I_BIT
160 biceq r9, r9, #PSR_I_BIT
161
162 @
163 @ Call the processor-specific abort handler:
164 @
165 @ r2 - aborted context pc
166 @ r3 - aborted context cpsr
167 @
168 @ The abort handler must return the aborted address in r0, and
169 @ the fault status register in r1. r9 must be preserved.
170 @
Paul Brook48d79272008-04-18 22:43:07 +0100171#ifdef MULTI_DABORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172 ldr r4, .LCprocfns
173 mov lr, pc
Paul Brook48d79272008-04-18 22:43:07 +0100174 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175#else
Paul Brook48d79272008-04-18 22:43:07 +0100176 bl CPU_DABORT_HANDLER
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177#endif
178
179 @
180 @ set desired IRQ state, then call main handler
181 @
Will Deacon7e202692010-11-28 14:57:24 +0000182 debug_entry r1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700183 msr cpsr_c, r9
184 mov r2, sp
185 bl do_DataAbort
186
187 @
188 @ IRQs off again before pulling preserved data off the stack
189 @
Russell Kingac788842010-07-10 10:10:18 +0100190 disable_irq_notrace
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
192 @
193 @ restore SPSR and restart the instruction
194 @
Catalin Marinasb86040a2009-07-24 12:32:54 +0100195 ldr r2, [sp, #S_PSR]
196 svc_exit r2 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100197 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100198ENDPROC(__dabt_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199
200 .align 5
201__irq_svc:
Russell Kingccea7a12005-05-31 22:22:32 +0100202 svc_entry
203
Russell Kingac788842010-07-10 10:10:18 +0100204#ifdef CONFIG_TRACE_IRQFLAGS
205 bl trace_hardirqs_off
206#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207#ifdef CONFIG_PREEMPT
Russell King706fdd92005-05-21 18:15:45 +0100208 get_thread_info tsk
209 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
210 add r7, r8, #1 @ increment it
211 str r7, [tsk, #TI_PREEMPT]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212#endif
Russell Kingccea7a12005-05-31 22:22:32 +0100213
Russell King187a51a2005-05-21 18:14:44 +0100214 irq_handler
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215#ifdef CONFIG_PREEMPT
Russell King28fab1a2008-04-13 17:47:35 +0100216 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
Russell King706fdd92005-05-21 18:15:45 +0100217 ldr r0, [tsk, #TI_FLAGS] @ get flags
Russell King28fab1a2008-04-13 17:47:35 +0100218 teq r8, #0 @ if preempt count != 0
219 movne r0, #0 @ force flags to 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 tst r0, #_TIF_NEED_RESCHED
221 blne svc_preempt
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100223 ldr r4, [sp, #S_PSR] @ irqs are already disabled
Russell King7ad1bcb2006-08-27 12:07:02 +0100224#ifdef CONFIG_TRACE_IRQFLAGS
Catalin Marinasb86040a2009-07-24 12:32:54 +0100225 tst r4, #PSR_I_BIT
Russell King7ad1bcb2006-08-27 12:07:02 +0100226 bleq trace_hardirqs_on
227#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100228 svc_exit r4 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100229 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100230ENDPROC(__irq_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231
232 .ltorg
233
234#ifdef CONFIG_PREEMPT
235svc_preempt:
Russell King28fab1a2008-04-13 17:47:35 +0100236 mov r8, lr
Linus Torvalds1da177e2005-04-16 15:20:36 -07002371: bl preempt_schedule_irq @ irq en/disable is done inside
Russell King706fdd92005-05-21 18:15:45 +0100238 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239 tst r0, #_TIF_NEED_RESCHED
Russell King28fab1a2008-04-13 17:47:35 +0100240 moveq pc, r8 @ go again
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 b 1b
242#endif
243
244 .align 5
245__und_svc:
Nicolas Pitred30a0c82007-12-14 15:56:01 -0500246#ifdef CONFIG_KPROBES
247 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
248 @ it obviously needs free stack space which then will belong to
249 @ the saved context.
250 svc_entry 64
251#else
Russell Kingccea7a12005-05-31 22:22:32 +0100252 svc_entry
Nicolas Pitred30a0c82007-12-14 15:56:01 -0500253#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254
255 @
256 @ call emulation code, which returns using r9 if it has emulated
257 @ the instruction, or the more conventional lr if we are to treat
258 @ this as a real undefined instruction
259 @
260 @ r0 - instruction
261 @
Catalin Marinas83e686e2009-09-18 23:27:07 +0100262#ifndef CONFIG_THUMB2_KERNEL
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263 ldr r0, [r2, #-4]
Catalin Marinas83e686e2009-09-18 23:27:07 +0100264#else
265 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
266 and r9, r0, #0xf800
267 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
268 ldrhhs r9, [r2] @ bottom 16 bits
269 orrhs r0, r9, r0, lsl #16
270#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100271 adr r9, BSYM(1f)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 bl call_fpe
273
274 mov r0, sp @ struct pt_regs *regs
275 bl do_undefinstr
276
277 @
278 @ IRQs off again before pulling preserved data off the stack
279 @
Russell Kingac788842010-07-10 10:10:18 +01002801: disable_irq_notrace
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281
282 @
283 @ restore SPSR and restart the instruction
284 @
Catalin Marinasb86040a2009-07-24 12:32:54 +0100285 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
286 svc_exit r2 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100287 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100288ENDPROC(__und_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289
290 .align 5
291__pabt_svc:
Russell Kingccea7a12005-05-31 22:22:32 +0100292 svc_entry
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293
294 @
295 @ re-enable interrupts if appropriate
296 @
297 mrs r9, cpsr
298 tst r3, #PSR_I_BIT
299 biceq r9, r9, #PSR_I_BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300
Paul Brook48d79272008-04-18 22:43:07 +0100301 mov r0, r2 @ pass address of aborted instruction.
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100302#ifdef MULTI_PABORT
Paul Brook48d79272008-04-18 22:43:07 +0100303 ldr r4, .LCprocfns
304 mov lr, pc
305 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
306#else
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100307 bl CPU_PABORT_HANDLER
Paul Brook48d79272008-04-18 22:43:07 +0100308#endif
Will Deacon7e202692010-11-28 14:57:24 +0000309 debug_entry r1
Paul Brook48d79272008-04-18 22:43:07 +0100310 msr cpsr_c, r9 @ Maybe enable interrupts
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100311 mov r2, sp @ regs
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 bl do_PrefetchAbort @ call abort handler
313
314 @
315 @ IRQs off again before pulling preserved data off the stack
316 @
Russell Kingac788842010-07-10 10:10:18 +0100317 disable_irq_notrace
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318
319 @
320 @ restore SPSR and restart the instruction
321 @
Catalin Marinasb86040a2009-07-24 12:32:54 +0100322 ldr r2, [sp, #S_PSR]
323 svc_exit r2 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100324 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100325ENDPROC(__pabt_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326
327 .align 5
Russell King49f680e2005-05-31 18:02:00 +0100328.LCcralign:
329 .word cr_alignment
Paul Brook48d79272008-04-18 22:43:07 +0100330#ifdef MULTI_DABORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331.LCprocfns:
332 .word processor
333#endif
334.LCfp:
335 .word fp_enter
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336
337/*
338 * User mode handlers
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000339 *
340 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341 */
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000342
343#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
344#error "sizeof(struct pt_regs) must be a multiple of 8"
345#endif
346
Russell Kingccea7a12005-05-31 22:22:32 +0100347 .macro usr_entry
Catalin Marinasc4c57162009-02-16 11:42:09 +0100348 UNWIND(.fnstart )
349 UNWIND(.cantunwind ) @ don't unwind the user space
Russell Kingccea7a12005-05-31 22:22:32 +0100350 sub sp, sp, #S_FRAME_SIZE
Catalin Marinasb86040a2009-07-24 12:32:54 +0100351 ARM( stmib sp, {r1 - r12} )
352 THUMB( stmia sp, {r0 - r12} )
Russell Kingccea7a12005-05-31 22:22:32 +0100353
354 ldmia r0, {r1 - r3}
355 add r0, sp, #S_PC @ here for interlock avoidance
356 mov r4, #-1 @ "" "" "" ""
357
358 str r1, [sp] @ save the "real" r0 copied
359 @ from the exception stack
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360
361 @
362 @ We are now ready to fill in the remaining blanks on the stack:
363 @
364 @ r2 - lr_<exception>, already fixed up for correct return/restart
365 @ r3 - spsr_<exception>
366 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
367 @
368 @ Also, separately save sp_usr and lr_usr
369 @
Russell Kingccea7a12005-05-31 22:22:32 +0100370 stmia r0, {r2 - r4}
Catalin Marinasb86040a2009-07-24 12:32:54 +0100371 ARM( stmdb r0, {sp, lr}^ )
372 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373
374 @
375 @ Enable the alignment trap while in kernel mode
376 @
Russell King49f680e2005-05-31 18:02:00 +0100377 alignment_trap r0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378
379 @
380 @ Clear FP to mark the first stack frame
381 @
382 zero_fp
383 .endm
384
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100385 .macro kuser_cmpxchg_check
386#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
387#ifndef CONFIG_MMU
388#warning "NPTL on non MMU needs fixing"
389#else
390 @ Make sure our user space atomic helper is restarted
391 @ if it was interrupted in a critical region. Here we
392 @ perform a quick test inline since it should be false
393 @ 99.9999% of the time. The rest is done out of line.
394 cmp r2, #TASK_SIZE
395 blhs kuser_cmpxchg_fixup
396#endif
397#endif
398 .endm
399
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400 .align 5
401__dabt_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100402 usr_entry
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100403 kuser_cmpxchg_check
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404
405 @
406 @ Call the processor-specific abort handler:
407 @
408 @ r2 - aborted context pc
409 @ r3 - aborted context cpsr
410 @
411 @ The abort handler must return the aborted address in r0, and
412 @ the fault status register in r1.
413 @
Paul Brook48d79272008-04-18 22:43:07 +0100414#ifdef MULTI_DABORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415 ldr r4, .LCprocfns
416 mov lr, pc
Paul Brook48d79272008-04-18 22:43:07 +0100417 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418#else
Paul Brook48d79272008-04-18 22:43:07 +0100419 bl CPU_DABORT_HANDLER
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420#endif
421
422 @
423 @ IRQs on, then call the main handler
424 @
Will Deacon7e202692010-11-28 14:57:24 +0000425 debug_entry r1
Russell King1ec42c02005-04-26 15:18:26 +0100426 enable_irq
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427 mov r2, sp
Catalin Marinasb86040a2009-07-24 12:32:54 +0100428 adr lr, BSYM(ret_from_exception)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429 b do_DataAbort
Catalin Marinasc4c57162009-02-16 11:42:09 +0100430 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100431ENDPROC(__dabt_usr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432
433 .align 5
434__irq_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100435 usr_entry
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100436 kuser_cmpxchg_check
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438 get_thread_info tsk
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439#ifdef CONFIG_PREEMPT
Russell King706fdd92005-05-21 18:15:45 +0100440 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
441 add r7, r8, #1 @ increment it
442 str r7, [tsk, #TI_PREEMPT]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443#endif
Russell Kingccea7a12005-05-31 22:22:32 +0100444
Russell King187a51a2005-05-21 18:14:44 +0100445 irq_handler
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446#ifdef CONFIG_PREEMPT
Russell King706fdd92005-05-21 18:15:45 +0100447 ldr r0, [tsk, #TI_PREEMPT]
448 str r8, [tsk, #TI_PREEMPT]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449 teq r0, r7
Catalin Marinasb86040a2009-07-24 12:32:54 +0100450 ARM( strne r0, [r0, -r0] )
451 THUMB( movne r0, #0 )
452 THUMB( strne r0, [r0] )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453#endif
Russell Kingccea7a12005-05-31 22:22:32 +0100454
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455 mov why, #0
456 b ret_to_user
Catalin Marinasc4c57162009-02-16 11:42:09 +0100457 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100458ENDPROC(__irq_usr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459
460 .ltorg
461
462 .align 5
463__und_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100464 usr_entry
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466 @
467 @ fall through to the emulation code, which returns using r9 if
468 @ it has emulated the instruction, or the more conventional lr
469 @ if we are to treat this as a real undefined instruction
470 @
471 @ r0 - instruction
472 @
Catalin Marinasb86040a2009-07-24 12:32:54 +0100473 adr r9, BSYM(ret_from_exception)
474 adr lr, BSYM(__und_usr_unknown)
Paul Brookcb170a42008-04-18 22:43:08 +0100475 tst r3, #PSR_T_BIT @ Thumb mode?
Catalin Marinasb86040a2009-07-24 12:32:54 +0100476 itet eq @ explicit IT needed for the 1f label
Paul Brookcb170a42008-04-18 22:43:08 +0100477 subeq r4, r2, #4 @ ARM instr at LR - 4
478 subne r4, r2, #2 @ Thumb instr at LR - 2
4791: ldreqt r0, [r4]
Catalin Marinas26584852009-05-30 14:00:18 +0100480#ifdef CONFIG_CPU_ENDIAN_BE8
481 reveq r0, r0 @ little endian instruction
482#endif
Paul Brookcb170a42008-04-18 22:43:08 +0100483 beq call_fpe
484 @ Thumb instruction
485#if __LINUX_ARM_ARCH__ >= 7
Catalin Marinasb86040a2009-07-24 12:32:54 +01004862:
487 ARM( ldrht r5, [r4], #2 )
488 THUMB( ldrht r5, [r4] )
489 THUMB( add r4, r4, #2 )
Paul Brookcb170a42008-04-18 22:43:08 +0100490 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
491 cmp r0, #0xe800 @ 32bit instruction if xx != 0
492 blo __und_usr_unknown
4933: ldrht r0, [r4]
494 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
495 orr r0, r0, r5, lsl #16
496#else
497 b __und_usr_unknown
498#endif
Catalin Marinasc4c57162009-02-16 11:42:09 +0100499 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100500ENDPROC(__und_usr)
Paul Brookcb170a42008-04-18 22:43:08 +0100501
Linus Torvalds1da177e2005-04-16 15:20:36 -0700502 @
503 @ fallthrough to call_fpe
504 @
505
506/*
507 * The out of line fixup for the ldrt above.
508 */
Russell King42604152010-04-19 10:15:03 +0100509 .pushsection .fixup, "ax"
Paul Brookcb170a42008-04-18 22:43:08 +01005104: mov pc, r9
Russell King42604152010-04-19 10:15:03 +0100511 .popsection
512 .pushsection __ex_table,"a"
Paul Brookcb170a42008-04-18 22:43:08 +0100513 .long 1b, 4b
514#if __LINUX_ARM_ARCH__ >= 7
515 .long 2b, 4b
516 .long 3b, 4b
517#endif
Russell King42604152010-04-19 10:15:03 +0100518 .popsection
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519
520/*
521 * Check whether the instruction is a co-processor instruction.
522 * If yes, we need to call the relevant co-processor handler.
523 *
524 * Note that we don't do a full check here for the co-processor
525 * instructions; all instructions with bit 27 set are well
526 * defined. The only instructions that should fault are the
527 * co-processor instructions. However, we have to watch out
528 * for the ARM6/ARM7 SWI bug.
529 *
Catalin Marinasb5872db2008-01-10 19:16:17 +0100530 * NEON is a special case that has to be handled here. Not all
531 * NEON instructions are co-processor instructions, so we have
532 * to make a special case of checking for them. Plus, there's
533 * five groups of them, so we have a table of mask/opcode pairs
534 * to check against, and if any match then we branch off into the
535 * NEON handler code.
536 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 * Emulators may wish to make use of the following registers:
538 * r0 = instruction opcode.
539 * r2 = PC+4
Russell Kingdb6ccbb2007-01-06 22:53:48 +0000540 * r9 = normal "successful" return address
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541 * r10 = this threads thread_info structure.
Russell Kingdb6ccbb2007-01-06 22:53:48 +0000542 * lr = unrecognised instruction return address
Linus Torvalds1da177e2005-04-16 15:20:36 -0700543 */
Paul Brookcb170a42008-04-18 22:43:08 +0100544 @
545 @ Fall-through from Thumb-2 __und_usr
546 @
547#ifdef CONFIG_NEON
548 adr r6, .LCneon_thumb_opcodes
549 b 2f
550#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551call_fpe:
Catalin Marinasb5872db2008-01-10 19:16:17 +0100552#ifdef CONFIG_NEON
Paul Brookcb170a42008-04-18 22:43:08 +0100553 adr r6, .LCneon_arm_opcodes
Catalin Marinasb5872db2008-01-10 19:16:17 +01005542:
555 ldr r7, [r6], #4 @ mask value
556 cmp r7, #0 @ end mask?
557 beq 1f
558 and r8, r0, r7
559 ldr r7, [r6], #4 @ opcode bits matching in mask
560 cmp r8, r7 @ NEON instruction?
561 bne 2b
562 get_thread_info r10
563 mov r7, #1
564 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
565 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
566 b do_vfp @ let VFP handler handle this
5671:
568#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700569 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
Paul Brookcb170a42008-04-18 22:43:08 +0100570 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700571#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
572 and r8, r0, #0x0f000000 @ mask out op-code bits
573 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
574#endif
575 moveq pc, lr
576 get_thread_info r10 @ get current thread
577 and r8, r0, #0x00000f00 @ mask out CP number
Catalin Marinasb86040a2009-07-24 12:32:54 +0100578 THUMB( lsr r8, r8, #8 )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700579 mov r7, #1
580 add r6, r10, #TI_USED_CP
Catalin Marinasb86040a2009-07-24 12:32:54 +0100581 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
582 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583#ifdef CONFIG_IWMMXT
584 @ Test if we need to give access to iWMMXt coprocessors
585 ldr r5, [r10, #TI_FLAGS]
586 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
587 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
588 bcs iwmmxt_task_enable
589#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100590 ARM( add pc, pc, r8, lsr #6 )
591 THUMB( lsl r8, r8, #2 )
592 THUMB( add pc, r8 )
593 nop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594
Catalin Marinasa771fe62009-10-12 17:31:20 +0100595 movw_pc lr @ CP#0
Catalin Marinasb86040a2009-07-24 12:32:54 +0100596 W(b) do_fpe @ CP#1 (FPE)
597 W(b) do_fpe @ CP#2 (FPE)
Catalin Marinasa771fe62009-10-12 17:31:20 +0100598 movw_pc lr @ CP#3
Lennert Buytenhekc17fad12006-06-27 23:03:03 +0100599#ifdef CONFIG_CRUNCH
600 b crunch_task_enable @ CP#4 (MaverickCrunch)
601 b crunch_task_enable @ CP#5 (MaverickCrunch)
602 b crunch_task_enable @ CP#6 (MaverickCrunch)
603#else
Catalin Marinasa771fe62009-10-12 17:31:20 +0100604 movw_pc lr @ CP#4
605 movw_pc lr @ CP#5
606 movw_pc lr @ CP#6
Lennert Buytenhekc17fad12006-06-27 23:03:03 +0100607#endif
Catalin Marinasa771fe62009-10-12 17:31:20 +0100608 movw_pc lr @ CP#7
609 movw_pc lr @ CP#8
610 movw_pc lr @ CP#9
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611#ifdef CONFIG_VFP
Catalin Marinasb86040a2009-07-24 12:32:54 +0100612 W(b) do_vfp @ CP#10 (VFP)
613 W(b) do_vfp @ CP#11 (VFP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614#else
Catalin Marinasa771fe62009-10-12 17:31:20 +0100615 movw_pc lr @ CP#10 (VFP)
616 movw_pc lr @ CP#11 (VFP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700617#endif
Catalin Marinasa771fe62009-10-12 17:31:20 +0100618 movw_pc lr @ CP#12
619 movw_pc lr @ CP#13
620 movw_pc lr @ CP#14 (Debug)
621 movw_pc lr @ CP#15 (Control)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700622
Catalin Marinasb5872db2008-01-10 19:16:17 +0100623#ifdef CONFIG_NEON
624 .align 6
625
Paul Brookcb170a42008-04-18 22:43:08 +0100626.LCneon_arm_opcodes:
Catalin Marinasb5872db2008-01-10 19:16:17 +0100627 .word 0xfe000000 @ mask
628 .word 0xf2000000 @ opcode
629
630 .word 0xff100000 @ mask
631 .word 0xf4000000 @ opcode
632
633 .word 0x00000000 @ mask
634 .word 0x00000000 @ opcode
Paul Brookcb170a42008-04-18 22:43:08 +0100635
636.LCneon_thumb_opcodes:
637 .word 0xef000000 @ mask
638 .word 0xef000000 @ opcode
639
640 .word 0xff100000 @ mask
641 .word 0xf9000000 @ opcode
642
643 .word 0x00000000 @ mask
644 .word 0x00000000 @ opcode
Catalin Marinasb5872db2008-01-10 19:16:17 +0100645#endif
646
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647do_fpe:
Russell King5d25ac02006-03-15 12:33:43 +0000648 enable_irq
Linus Torvalds1da177e2005-04-16 15:20:36 -0700649 ldr r4, .LCfp
650 add r10, r10, #TI_FPSTATE @ r10 = workspace
651 ldr pc, [r4] @ Call FP module USR entry point
652
653/*
654 * The FP module is called with these registers set:
655 * r0 = instruction
656 * r2 = PC+4
657 * r9 = normal "successful" return address
658 * r10 = FP workspace
659 * lr = unrecognised FP instruction return address
660 */
661
Santosh Shilimkar124efc22010-04-30 10:45:46 +0100662 .pushsection .data
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663ENTRY(fp_enter)
Russell Kingdb6ccbb2007-01-06 22:53:48 +0000664 .word no_fp
Santosh Shilimkar124efc22010-04-30 10:45:46 +0100665 .popsection
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666
Catalin Marinas83e686e2009-09-18 23:27:07 +0100667ENTRY(no_fp)
668 mov pc, lr
669ENDPROC(no_fp)
Russell Kingdb6ccbb2007-01-06 22:53:48 +0000670
671__und_usr_unknown:
Russell Kingecbab712009-01-27 23:20:00 +0000672 enable_irq
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673 mov r0, sp
Catalin Marinasb86040a2009-07-24 12:32:54 +0100674 adr lr, BSYM(ret_from_exception)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675 b do_undefinstr
Catalin Marinas93ed3972008-08-28 11:22:32 +0100676ENDPROC(__und_usr_unknown)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677
678 .align 5
679__pabt_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100680 usr_entry
Linus Torvalds1da177e2005-04-16 15:20:36 -0700681
Paul Brook48d79272008-04-18 22:43:07 +0100682 mov r0, r2 @ pass address of aborted instruction.
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100683#ifdef MULTI_PABORT
Paul Brook48d79272008-04-18 22:43:07 +0100684 ldr r4, .LCprocfns
685 mov lr, pc
686 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
687#else
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100688 bl CPU_PABORT_HANDLER
Paul Brook48d79272008-04-18 22:43:07 +0100689#endif
Will Deacon7e202692010-11-28 14:57:24 +0000690 debug_entry r1
Russell King1ec42c02005-04-26 15:18:26 +0100691 enable_irq @ Enable interrupts
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100692 mov r2, sp @ regs
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693 bl do_PrefetchAbort @ call abort handler
Catalin Marinasc4c57162009-02-16 11:42:09 +0100694 UNWIND(.fnend )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700695 /* fall through */
696/*
697 * This is the return code to user mode for abort handlers
698 */
699ENTRY(ret_from_exception)
Catalin Marinasc4c57162009-02-16 11:42:09 +0100700 UNWIND(.fnstart )
701 UNWIND(.cantunwind )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702 get_thread_info tsk
703 mov why, #0
704 b ret_to_user
Catalin Marinasc4c57162009-02-16 11:42:09 +0100705 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100706ENDPROC(__pabt_usr)
707ENDPROC(ret_from_exception)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700708
709/*
710 * Register switch for ARMv3 and ARMv4 processors
711 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
712 * previous and next are guaranteed not to be the same.
713 */
714ENTRY(__switch_to)
Catalin Marinasc4c57162009-02-16 11:42:09 +0100715 UNWIND(.fnstart )
716 UNWIND(.cantunwind )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717 add ip, r1, #TI_CPU_SAVE
718 ldr r3, [r2, #TI_TP_VALUE]
Catalin Marinasb86040a2009-07-24 12:32:54 +0100719 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
720 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
721 THUMB( str sp, [ip], #4 )
722 THUMB( str lr, [ip], #4 )
Catalin Marinas247055a2010-09-13 16:03:21 +0100723#ifdef CONFIG_CPU_USE_DOMAINS
Russell Kingd6551e82006-06-21 13:31:52 +0100724 ldr r6, [r2, #TI_CPU_DOMAIN]
Hyok S. Choiafeb90c2006-01-13 21:05:25 +0000725#endif
Tony Lindgrenf159f4e2010-07-05 14:53:10 +0100726 set_tls r3, r4, r5
Nicolas Pitredf0698b2010-06-07 21:50:33 -0400727#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
728 ldr r7, [r2, #TI_TASK]
729 ldr r8, =__stack_chk_guard
730 ldr r7, [r7, #TSK_STACK_CANARY]
731#endif
Catalin Marinas247055a2010-09-13 16:03:21 +0100732#ifdef CONFIG_CPU_USE_DOMAINS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
Hyok S. Choiafeb90c2006-01-13 21:05:25 +0000734#endif
Russell Kingd6551e82006-06-21 13:31:52 +0100735 mov r5, r0
736 add r4, r2, #TI_CPU_SAVE
737 ldr r0, =thread_notify_head
738 mov r1, #THREAD_NOTIFY_SWITCH
739 bl atomic_notifier_call_chain
Nicolas Pitredf0698b2010-06-07 21:50:33 -0400740#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
741 str r7, [r8]
742#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100743 THUMB( mov ip, r4 )
Russell Kingd6551e82006-06-21 13:31:52 +0100744 mov r0, r5
Catalin Marinasb86040a2009-07-24 12:32:54 +0100745 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
746 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
747 THUMB( ldr sp, [ip], #4 )
748 THUMB( ldr pc, [ip] )
Catalin Marinasc4c57162009-02-16 11:42:09 +0100749 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100750ENDPROC(__switch_to)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751
752 __INIT
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100753
754/*
755 * User helpers.
756 *
757 * These are segment of kernel provided user code reachable from user space
758 * at a fixed address in kernel memory. This is used to provide user space
759 * with some operations which require kernel help because of unimplemented
760 * native feature and/or instructions in many ARM CPUs. The idea is for
761 * this code to be executed directly in user mode for best efficiency but
762 * which is too intimate with the kernel counter part to be left to user
763 * libraries. In fact this code might even differ from one CPU to another
764 * depending on the available instruction set and restrictions like on
765 * SMP systems. In other words, the kernel reserves the right to change
766 * this code as needed without warning. Only the entry points and their
767 * results are guaranteed to be stable.
768 *
769 * Each segment is 32-byte aligned and will be moved to the top of the high
770 * vector page. New segments (if ever needed) must be added in front of
771 * existing ones. This mechanism should be used only for things that are
772 * really small and justified, and not be abused freely.
773 *
774 * User space is expected to implement those things inline when optimizing
775 * for a processor that has the necessary native support, but only if such
776 * resulting binaries are already to be incompatible with earlier ARM
777 * processors due to the use of unsupported instructions other than what
778 * is provided here. In other words don't make binaries unable to run on
779 * earlier processors just for the sake of not using these kernel helpers
780 * if your compiled code is not going to use the new instructions for other
781 * purpose.
782 */
Catalin Marinasb86040a2009-07-24 12:32:54 +0100783 THUMB( .arm )
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100784
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100785 .macro usr_ret, reg
786#ifdef CONFIG_ARM_THUMB
787 bx \reg
788#else
789 mov pc, \reg
790#endif
791 .endm
792
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100793 .align 5
794 .globl __kuser_helper_start
795__kuser_helper_start:
796
797/*
798 * Reference prototype:
799 *
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000800 * void __kernel_memory_barrier(void)
801 *
802 * Input:
803 *
804 * lr = return address
805 *
806 * Output:
807 *
808 * none
809 *
810 * Clobbered:
811 *
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100812 * none
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000813 *
814 * Definition and user space usage example:
815 *
816 * typedef void (__kernel_dmb_t)(void);
817 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
818 *
819 * Apply any needed memory barrier to preserve consistency with data modified
820 * manually and __kuser_cmpxchg usage.
821 *
822 * This could be used as follows:
823 *
824 * #define __kernel_dmb() \
825 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
Paul Brook6896eec2006-03-28 22:19:29 +0100826 * : : : "r0", "lr","cc" )
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000827 */
828
829__kuser_memory_barrier: @ 0xffff0fa0
Dave Martined3768a2010-12-01 15:39:23 +0100830 smp_dmb arm
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100831 usr_ret lr
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000832
833 .align 5
834
835/*
836 * Reference prototype:
837 *
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100838 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
839 *
840 * Input:
841 *
842 * r0 = oldval
843 * r1 = newval
844 * r2 = ptr
845 * lr = return address
846 *
847 * Output:
848 *
849 * r0 = returned value (zero or non-zero)
850 * C flag = set if r0 == 0, clear if r0 != 0
851 *
852 * Clobbered:
853 *
854 * r3, ip, flags
855 *
856 * Definition and user space usage example:
857 *
858 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
859 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
860 *
861 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
862 * Return zero if *ptr was changed or non-zero if no exchange happened.
863 * The C flag is also set if *ptr was changed to allow for assembly
864 * optimization in the calling code.
865 *
Nicolas Pitre5964eae2006-02-08 21:19:37 +0000866 * Notes:
867 *
868 * - This routine already includes memory barriers as needed.
869 *
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100870 * For example, a user space atomic_add implementation could look like this:
871 *
872 * #define atomic_add(ptr, val) \
873 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
874 * register unsigned int __result asm("r1"); \
875 * asm volatile ( \
876 * "1: @ atomic_add\n\t" \
877 * "ldr r0, [r2]\n\t" \
878 * "mov r3, #0xffff0fff\n\t" \
879 * "add lr, pc, #4\n\t" \
880 * "add r1, r0, %2\n\t" \
881 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
882 * "bcc 1b" \
883 * : "=&r" (__result) \
884 * : "r" (__ptr), "rIL" (val) \
885 * : "r0","r3","ip","lr","cc","memory" ); \
886 * __result; })
887 */
888
889__kuser_cmpxchg: @ 0xffff0fc0
890
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100891#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100892
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100893 /*
894 * Poor you. No fast solution possible...
895 * The kernel itself must perform the operation.
896 * A special ghost syscall is used for that (see traps.c).
897 */
Nicolas Pitre5e097442006-01-18 22:38:49 +0000898 stmfd sp!, {r7, lr}
Dave Martin55afd262010-12-01 18:12:43 +0100899 ldr r7, 1f @ it's 20 bits
Russell Kingcc20d422009-11-09 23:53:29 +0000900 swi __ARM_NR_cmpxchg
Nicolas Pitre5e097442006-01-18 22:38:49 +0000901 ldmfd sp!, {r7, pc}
Russell Kingcc20d422009-11-09 23:53:29 +00009021: .word __ARM_NR_cmpxchg
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100903
904#elif __LINUX_ARM_ARCH__ < 6
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100905
Nicolas Pitre49bca4c2006-02-08 21:19:37 +0000906#ifdef CONFIG_MMU
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100907
908 /*
909 * The only thing that can break atomicity in this cmpxchg
910 * implementation is either an IRQ or a data abort exception
911 * causing another process/thread to be scheduled in the middle
912 * of the critical sequence. To prevent this, code is added to
913 * the IRQ and data abort exception handlers to set the pc back
914 * to the beginning of the critical section if it is found to be
915 * within that critical section (see kuser_cmpxchg_fixup).
916 */
9171: ldr r3, [r2] @ load current val
918 subs r3, r3, r0 @ compare with oldval
9192: streq r1, [r2] @ store newval if eq
920 rsbs r0, r3, #0 @ set return val and C flag
921 usr_ret lr
922
923 .text
924kuser_cmpxchg_fixup:
925 @ Called from kuser_cmpxchg_check macro.
926 @ r2 = address of interrupted insn (must be preserved).
927 @ sp = saved regs. r7 and r8 are clobbered.
928 @ 1b = first critical insn, 2b = last critical insn.
929 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
930 mov r7, #0xffff0fff
931 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
932 subs r8, r2, r7
933 rsbcss r8, r8, #(2b - 1b)
934 strcs r7, [sp, #S_PC]
935 mov pc, lr
936 .previous
937
Nicolas Pitre49bca4c2006-02-08 21:19:37 +0000938#else
939#warning "NPTL on non MMU needs fixing"
940 mov r0, #-1
941 adds r0, r0, #0
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100942 usr_ret lr
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100943#endif
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100944
945#else
946
Dave Martined3768a2010-12-01 15:39:23 +0100947 smp_dmb arm
Nicolas Pitreb49c0f22007-11-20 17:20:29 +01009481: ldrex r3, [r2]
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100949 subs r3, r3, r0
950 strexeq r3, r1, [r2]
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100951 teqeq r3, #1
952 beq 1b
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100953 rsbs r0, r3, #0
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100954 /* beware -- each __kuser slot must be 8 instructions max */
Russell Kingf00ec482010-09-04 10:47:48 +0100955 ALT_SMP(b __kuser_memory_barrier)
956 ALT_UP(usr_ret lr)
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100957
958#endif
959
960 .align 5
961
962/*
963 * Reference prototype:
964 *
965 * int __kernel_get_tls(void)
966 *
967 * Input:
968 *
969 * lr = return address
970 *
971 * Output:
972 *
973 * r0 = TLS value
974 *
975 * Clobbered:
976 *
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100977 * none
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100978 *
979 * Definition and user space usage example:
980 *
981 * typedef int (__kernel_get_tls_t)(void);
982 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
983 *
984 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
985 *
986 * This could be used as follows:
987 *
988 * #define __kernel_get_tls() \
989 * ({ register unsigned int __val asm("r0"); \
990 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
991 * : "=r" (__val) : : "lr","cc" ); \
992 * __val; })
993 */
994
995__kuser_get_tls: @ 0xffff0fe0
Tony Lindgrenf159f4e2010-07-05 14:53:10 +0100996 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100997 usr_ret lr
Tony Lindgrenf159f4e2010-07-05 14:53:10 +0100998 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
999 .rep 4
1000 .word 0 @ 0xffff0ff0 software TLS value, then
1001 .endr @ pad up to __kuser_helper_version
Nicolas Pitre2d2669b2005-04-29 22:08:33 +01001002
1003/*
1004 * Reference declaration:
1005 *
1006 * extern unsigned int __kernel_helper_version;
1007 *
1008 * Definition and user space usage example:
1009 *
1010 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1011 *
1012 * User space may read this to determine the curent number of helpers
1013 * available.
1014 */
1015
1016__kuser_helper_version: @ 0xffff0ffc
1017 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1018
1019 .globl __kuser_helper_end
1020__kuser_helper_end:
1021
Catalin Marinasb86040a2009-07-24 12:32:54 +01001022 THUMB( .thumb )
Nicolas Pitre2d2669b2005-04-29 22:08:33 +01001023
Linus Torvalds1da177e2005-04-16 15:20:36 -07001024/*
1025 * Vector stubs.
1026 *
Russell King79335232005-04-26 15:17:42 +01001027 * This code is copied to 0xffff0200 so we can use branches in the
1028 * vectors, rather than ldr's. Note that this code must not
1029 * exceed 0x300 bytes.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030 *
1031 * Common stub entry macro:
1032 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
Russell Kingccea7a12005-05-31 22:22:32 +01001033 *
1034 * SP points to a minimal amount of processor-private memory, the address
1035 * of which is copied into r0 for the mode specific abort handler.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001036 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001037 .macro vector_stub, name, mode, correction=0
Linus Torvalds1da177e2005-04-16 15:20:36 -07001038 .align 5
1039
1040vector_\name:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001041 .if \correction
1042 sub lr, lr, #\correction
1043 .endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044
Russell Kingccea7a12005-05-31 22:22:32 +01001045 @
1046 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1047 @ (parent CPSR)
1048 @
1049 stmia sp, {r0, lr} @ save r0, lr
1050 mrs lr, spsr
1051 str lr, [sp, #8] @ save spsr
1052
1053 @
1054 @ Prepare for SVC32 mode. IRQs remain disabled.
1055 @
1056 mrs r0, cpsr
Catalin Marinasb86040a2009-07-24 12:32:54 +01001057 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
Russell Kingccea7a12005-05-31 22:22:32 +01001058 msr spsr_cxsf, r0
1059
1060 @
1061 @ the branch table must immediately follow this code
1062 @
Russell Kingccea7a12005-05-31 22:22:32 +01001063 and lr, lr, #0x0f
Catalin Marinasb86040a2009-07-24 12:32:54 +01001064 THUMB( adr r0, 1f )
1065 THUMB( ldr lr, [r0, lr, lsl #2] )
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001066 mov r0, sp
Catalin Marinasb86040a2009-07-24 12:32:54 +01001067 ARM( ldr lr, [pc, lr, lsl #2] )
Russell Kingccea7a12005-05-31 22:22:32 +01001068 movs pc, lr @ branch to handler in SVC mode
Catalin Marinas93ed3972008-08-28 11:22:32 +01001069ENDPROC(vector_\name)
Catalin Marinas88987ef2009-07-24 12:32:52 +01001070
1071 .align 2
1072 @ handler addresses follow this label
10731:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001074 .endm
1075
Russell King79335232005-04-26 15:17:42 +01001076 .globl __stubs_start
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077__stubs_start:
1078/*
1079 * Interrupt dispatcher
1080 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001081 vector_stub irq, IRQ_MODE, 4
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082
1083 .long __irq_usr @ 0 (USR_26 / USR_32)
1084 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1085 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1086 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1087 .long __irq_invalid @ 4
1088 .long __irq_invalid @ 5
1089 .long __irq_invalid @ 6
1090 .long __irq_invalid @ 7
1091 .long __irq_invalid @ 8
1092 .long __irq_invalid @ 9
1093 .long __irq_invalid @ a
1094 .long __irq_invalid @ b
1095 .long __irq_invalid @ c
1096 .long __irq_invalid @ d
1097 .long __irq_invalid @ e
1098 .long __irq_invalid @ f
1099
1100/*
1101 * Data abort dispatcher
1102 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1103 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001104 vector_stub dabt, ABT_MODE, 8
Linus Torvalds1da177e2005-04-16 15:20:36 -07001105
1106 .long __dabt_usr @ 0 (USR_26 / USR_32)
1107 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1108 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1109 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1110 .long __dabt_invalid @ 4
1111 .long __dabt_invalid @ 5
1112 .long __dabt_invalid @ 6
1113 .long __dabt_invalid @ 7
1114 .long __dabt_invalid @ 8
1115 .long __dabt_invalid @ 9
1116 .long __dabt_invalid @ a
1117 .long __dabt_invalid @ b
1118 .long __dabt_invalid @ c
1119 .long __dabt_invalid @ d
1120 .long __dabt_invalid @ e
1121 .long __dabt_invalid @ f
1122
1123/*
1124 * Prefetch abort dispatcher
1125 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1126 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001127 vector_stub pabt, ABT_MODE, 4
Linus Torvalds1da177e2005-04-16 15:20:36 -07001128
1129 .long __pabt_usr @ 0 (USR_26 / USR_32)
1130 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1131 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1132 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1133 .long __pabt_invalid @ 4
1134 .long __pabt_invalid @ 5
1135 .long __pabt_invalid @ 6
1136 .long __pabt_invalid @ 7
1137 .long __pabt_invalid @ 8
1138 .long __pabt_invalid @ 9
1139 .long __pabt_invalid @ a
1140 .long __pabt_invalid @ b
1141 .long __pabt_invalid @ c
1142 .long __pabt_invalid @ d
1143 .long __pabt_invalid @ e
1144 .long __pabt_invalid @ f
1145
1146/*
1147 * Undef instr entry dispatcher
1148 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1149 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001150 vector_stub und, UND_MODE
Linus Torvalds1da177e2005-04-16 15:20:36 -07001151
1152 .long __und_usr @ 0 (USR_26 / USR_32)
1153 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1154 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1155 .long __und_svc @ 3 (SVC_26 / SVC_32)
1156 .long __und_invalid @ 4
1157 .long __und_invalid @ 5
1158 .long __und_invalid @ 6
1159 .long __und_invalid @ 7
1160 .long __und_invalid @ 8
1161 .long __und_invalid @ 9
1162 .long __und_invalid @ a
1163 .long __und_invalid @ b
1164 .long __und_invalid @ c
1165 .long __und_invalid @ d
1166 .long __und_invalid @ e
1167 .long __und_invalid @ f
1168
1169 .align 5
1170
1171/*=============================================================================
1172 * Undefined FIQs
1173 *-----------------------------------------------------------------------------
1174 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1175 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1176 * Basically to switch modes, we *HAVE* to clobber one register... brain
1177 * damage alert! I don't think that we can execute any code in here in any
1178 * other mode than FIQ... Ok you can switch to another mode, but you can't
1179 * get out of that mode without clobbering one register.
1180 */
1181vector_fiq:
1182 disable_fiq
1183 subs pc, lr, #4
1184
1185/*=============================================================================
1186 * Address exception handler
1187 *-----------------------------------------------------------------------------
1188 * These aren't too critical.
1189 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1190 */
1191
1192vector_addrexcptn:
1193 b vector_addrexcptn
1194
1195/*
1196 * We group all the following data together to optimise
1197 * for CPUs with separate I & D caches.
1198 */
1199 .align 5
1200
1201.LCvswi:
1202 .word vector_swi
1203
Russell King79335232005-04-26 15:17:42 +01001204 .globl __stubs_end
Linus Torvalds1da177e2005-04-16 15:20:36 -07001205__stubs_end:
1206
Russell King79335232005-04-26 15:17:42 +01001207 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
Linus Torvalds1da177e2005-04-16 15:20:36 -07001208
Russell King79335232005-04-26 15:17:42 +01001209 .globl __vectors_start
1210__vectors_start:
Catalin Marinasb86040a2009-07-24 12:32:54 +01001211 ARM( swi SYS_ERROR0 )
1212 THUMB( svc #0 )
1213 THUMB( nop )
1214 W(b) vector_und + stubs_offset
1215 W(ldr) pc, .LCvswi + stubs_offset
1216 W(b) vector_pabt + stubs_offset
1217 W(b) vector_dabt + stubs_offset
1218 W(b) vector_addrexcptn + stubs_offset
1219 W(b) vector_irq + stubs_offset
1220 W(b) vector_fiq + stubs_offset
Linus Torvalds1da177e2005-04-16 15:20:36 -07001221
Russell King79335232005-04-26 15:17:42 +01001222 .globl __vectors_end
1223__vectors_end:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001224
1225 .data
1226
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227 .globl cr_alignment
1228 .globl cr_no_alignment
1229cr_alignment:
1230 .space 4
1231cr_no_alignment:
1232 .space 4
eric miao52108642010-12-13 09:42:34 +01001233
1234#ifdef CONFIG_MULTI_IRQ_HANDLER
1235 .globl handle_arch_irq
1236handle_arch_irq:
1237 .space 4
1238#endif