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googlers / maze / linux / d70b1e06eb331afe1576ac23bb9523708026ba1f / . / drivers / media / platform / s5p-mfc / s5p_mfc_cmd_v6.c
blob: 5708fc3d9b4d01959861a0421fdff26d305327c2 [file] [log] [blame]
Jeongtae Parkf96f3cf2012-10-03 22:19:11 -0300[diff] [blame]1/*
2 * linux/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include "s5p_mfc_common.h"
14
15#include "s5p_mfc_cmd.h"
16#include "s5p_mfc_debug.h"
17#include "s5p_mfc_intr.h"
18#include "s5p_mfc_opr.h"
19
Sachin Kamat95a75542013-03-02 06:41:02 -0300[diff] [blame]20static int s5p_mfc_cmd_host2risc_v6(struct s5p_mfc_dev *dev, int cmd,
Jeongtae Parkf96f3cf2012-10-03 22:19:11 -0300[diff] [blame]21 struct s5p_mfc_cmd_args *args)
22{
23 mfc_debug(2, "Issue the command: %d\n", cmd);
24
25 /* Reset RISC2HOST command */
26 mfc_write(dev, 0x0, S5P_FIMV_RISC2HOST_CMD_V6);
27
28 /* Issue the command */
29 mfc_write(dev, cmd, S5P_FIMV_HOST2RISC_CMD_V6);
30 mfc_write(dev, 0x1, S5P_FIMV_HOST2RISC_INT_V6);
31
32 return 0;
33}
34
Sachin Kamat95a75542013-03-02 06:41:02 -0300[diff] [blame]35static int s5p_mfc_sys_init_cmd_v6(struct s5p_mfc_dev *dev)
Jeongtae Parkf96f3cf2012-10-03 22:19:11 -0300[diff] [blame]36{
37 struct s5p_mfc_cmd_args h2r_args;
38 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
39
40 s5p_mfc_hw_call(dev->mfc_ops, alloc_dev_context_buffer, dev);
41 mfc_write(dev, dev->ctx_buf.dma, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
42 mfc_write(dev, buf_size->dev_ctx, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
43 return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_SYS_INIT_V6,
44 &h2r_args);
45}
46
Sachin Kamat95a75542013-03-02 06:41:02 -0300[diff] [blame]47static int s5p_mfc_sleep_cmd_v6(struct s5p_mfc_dev *dev)
Jeongtae Parkf96f3cf2012-10-03 22:19:11 -0300[diff] [blame]48{
49 struct s5p_mfc_cmd_args h2r_args;
50
51 memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
52 return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_SLEEP_V6,
53 &h2r_args);
54}
55
Sachin Kamat95a75542013-03-02 06:41:02 -0300[diff] [blame]56static int s5p_mfc_wakeup_cmd_v6(struct s5p_mfc_dev *dev)
Jeongtae Parkf96f3cf2012-10-03 22:19:11 -0300[diff] [blame]57{
58 struct s5p_mfc_cmd_args h2r_args;
59
60 memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
61 return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_WAKEUP_V6,
62 &h2r_args);
63}
64
65/* Open a new instance and get its number */
Sachin Kamat95a75542013-03-02 06:41:02 -0300[diff] [blame]66static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
Jeongtae Parkf96f3cf2012-10-03 22:19:11 -0300[diff] [blame]67{
68 struct s5p_mfc_dev *dev = ctx->dev;
69 struct s5p_mfc_cmd_args h2r_args;
70 int codec_type;
71
72 mfc_debug(2, "Requested codec mode: %d\n", ctx->codec_mode);
73 dev->curr_ctx = ctx->num;
74 switch (ctx->codec_mode) {
75 case S5P_MFC_CODEC_H264_DEC:
76 codec_type = S5P_FIMV_CODEC_H264_DEC_V6;
77 break;
78 case S5P_MFC_CODEC_H264_MVC_DEC:
79 codec_type = S5P_FIMV_CODEC_H264_MVC_DEC_V6;
80 break;
81 case S5P_MFC_CODEC_VC1_DEC:
82 codec_type = S5P_FIMV_CODEC_VC1_DEC_V6;
83 break;
84 case S5P_MFC_CODEC_MPEG4_DEC:
85 codec_type = S5P_FIMV_CODEC_MPEG4_DEC_V6;
86 break;
87 case S5P_MFC_CODEC_MPEG2_DEC:
88 codec_type = S5P_FIMV_CODEC_MPEG2_DEC_V6;
89 break;
90 case S5P_MFC_CODEC_H263_DEC:
91 codec_type = S5P_FIMV_CODEC_H263_DEC_V6;
92 break;
93 case S5P_MFC_CODEC_VC1RCV_DEC:
94 codec_type = S5P_FIMV_CODEC_VC1RCV_DEC_V6;
95 break;
96 case S5P_MFC_CODEC_VP8_DEC:
97 codec_type = S5P_FIMV_CODEC_VP8_DEC_V6;
98 break;
99 case S5P_MFC_CODEC_H264_ENC:
100 codec_type = S5P_FIMV_CODEC_H264_ENC_V6;
101 break;
102 case S5P_MFC_CODEC_H264_MVC_ENC:
103 codec_type = S5P_FIMV_CODEC_H264_MVC_ENC_V6;
104 break;
105 case S5P_MFC_CODEC_MPEG4_ENC:
106 codec_type = S5P_FIMV_CODEC_MPEG4_ENC_V6;
107 break;
108 case S5P_MFC_CODEC_H263_ENC:
109 codec_type = S5P_FIMV_CODEC_H263_ENC_V6;
110 break;
111 default:
112 codec_type = S5P_FIMV_CODEC_NONE_V6;
113 };
114 mfc_write(dev, codec_type, S5P_FIMV_CODEC_TYPE_V6);
115 mfc_write(dev, ctx->ctx.dma, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
116 mfc_write(dev, ctx->ctx.size, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
117 mfc_write(dev, 0, S5P_FIMV_D_CRC_CTRL_V6); /* no crc */
118
119 return s5p_mfc_cmd_host2risc_v6(dev, S5P_FIMV_H2R_CMD_OPEN_INSTANCE_V6,
120 &h2r_args);
121}
122
123/* Close instance */
Sachin Kamat95a75542013-03-02 06:41:02 -0300[diff] [blame]124static int s5p_mfc_close_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
Jeongtae Parkf96f3cf2012-10-03 22:19:11 -0300[diff] [blame]125{
126 struct s5p_mfc_dev *dev = ctx->dev;
127 struct s5p_mfc_cmd_args h2r_args;
128 int ret = 0;
129
130 dev->curr_ctx = ctx->num;
131 if (ctx->state != MFCINST_FREE) {
132 mfc_write(dev, ctx->inst_no, S5P_FIMV_INSTANCE_ID_V6);
133 ret = s5p_mfc_cmd_host2risc_v6(dev,
134 S5P_FIMV_H2R_CMD_CLOSE_INSTANCE_V6,
135 &h2r_args);
136 } else {
137 ret = -EINVAL;
138 }
139
140 return ret;
141}
142
143/* Initialize cmd function pointers for MFC v6 */
144static struct s5p_mfc_hw_cmds s5p_mfc_cmds_v6 = {
145 .cmd_host2risc = s5p_mfc_cmd_host2risc_v6,
146 .sys_init_cmd = s5p_mfc_sys_init_cmd_v6,
147 .sleep_cmd = s5p_mfc_sleep_cmd_v6,
148 .wakeup_cmd = s5p_mfc_wakeup_cmd_v6,
149 .open_inst_cmd = s5p_mfc_open_inst_cmd_v6,
150 .close_inst_cmd = s5p_mfc_close_inst_cmd_v6,
151};
152
153struct s5p_mfc_hw_cmds *s5p_mfc_init_hw_cmds_v6(void)
154{
155 return &s5p_mfc_cmds_v6;
156}