blob: 560ddb6bc8a79dd6e480255bb0aefdc45d7ac7f7 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/sh/mm/cache-sh4.c
3 *
4 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
Paul Mundtdeaef202009-09-09 16:06:39 +09005 * Copyright (C) 2001 - 2009 Paul Mundt
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 * Copyright (C) 2003 Richard Curnow
Chris Smith09b5a102008-07-02 15:17:11 +09007 * Copyright (c) 2007 STMicroelectronics (R&D) Ltd.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/mm.h>
Paul Mundt52e27782006-11-21 11:09:41 +090015#include <linux/io.h>
16#include <linux/mutex.h>
Paul Mundt2277ab42009-07-22 19:20:49 +090017#include <linux/fs.h>
Paul Mundtdeaef202009-09-09 16:06:39 +090018#include <linux/highmem.h>
19#include <asm/pgtable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <asm/mmu_context.h>
21#include <asm/cacheflush.h>
22
Paul Mundt28ccf7f2006-09-27 18:30:07 +090023/*
24 * The maximum number of pages we support up to when doing ranged dcache
25 * flushing. Anything exceeding this will simply flush the dcache in its
26 * entirety.
27 */
Chris Smith09b5a102008-07-02 15:17:11 +090028#define MAX_ICACHE_PAGES 32
Paul Mundt28ccf7f2006-09-27 18:30:07 +090029
Valentin Sitdikova7a7c0e2009-10-16 14:15:38 +090030static void __flush_cache_one(unsigned long addr, unsigned long phys,
Paul Mundta2527102006-09-27 11:29:55 +090031 unsigned long exec_offset);
Richard Curnowb638d0b2006-09-27 14:09:26 +090032
33/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070034 * Write back the range of D-cache, and purge the I-cache.
35 *
Chris Smith09b5a102008-07-02 15:17:11 +090036 * Called from kernel/module.c:sys_init_module and routine for a.out format,
37 * signal handler code and kprobes code
Linus Torvalds1da177e2005-04-16 15:20:36 -070038 */
Matt Fleminga6325242009-10-06 21:22:21 +000039static void __uses_jump_to_uncached sh4_flush_icache_range(void *args)
Linus Torvalds1da177e2005-04-16 15:20:36 -070040{
Paul Mundtf26b2a52009-08-21 17:23:14 +090041 struct flusher_data *data = args;
Paul Mundtf26b2a52009-08-21 17:23:14 +090042 unsigned long start, end;
Paul Mundt983f4c52009-09-01 21:12:55 +090043 unsigned long flags, v;
Linus Torvalds1da177e2005-04-16 15:20:36 -070044 int i;
45
Paul Mundtf26b2a52009-08-21 17:23:14 +090046 start = data->addr1;
47 end = data->addr2;
48
Paul Mundt682f88a2009-09-09 13:19:46 +090049 /* If there are too many pages then just blow away the caches */
50 if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) {
51 local_flush_cache_all(NULL);
52 return;
Chris Smith09b5a102008-07-02 15:17:11 +090053 }
Paul Mundt682f88a2009-09-09 13:19:46 +090054
55 /*
56 * Selectively flush d-cache then invalidate the i-cache.
57 * This is inefficient, so only use this for small ranges.
58 */
59 start &= ~(L1_CACHE_BYTES-1);
60 end += L1_CACHE_BYTES-1;
61 end &= ~(L1_CACHE_BYTES-1);
62
63 local_irq_save(flags);
64 jump_to_uncached();
65
66 for (v = start; v < end; v += L1_CACHE_BYTES) {
67 unsigned long icacheaddr;
Matt Fleminga9d244a2009-11-05 23:14:39 +000068 int j, n;
Paul Mundt682f88a2009-09-09 13:19:46 +090069
70 __ocbwb(v);
71
72 icacheaddr = CACHE_IC_ADDRESS_ARRAY | (v &
73 cpu_data->icache.entry_mask);
74
75 /* Clear i-cache line valid-bit */
Matt Fleminga9d244a2009-11-05 23:14:39 +000076 n = boot_cpu_data.icache.n_aliases;
Paul Mundt682f88a2009-09-09 13:19:46 +090077 for (i = 0; i < cpu_data->icache.ways; i++) {
Matt Fleminga9d244a2009-11-05 23:14:39 +000078 for (j = 0; j < n; j++)
79 __raw_writel(0, icacheaddr + (j * PAGE_SIZE));
Paul Mundt682f88a2009-09-09 13:19:46 +090080 icacheaddr += cpu_data->icache.way_incr;
81 }
82 }
83
84 back_to_cached();
85 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -070086}
87
Valentin Sitdikova7a7c0e2009-10-16 14:15:38 +090088static inline void flush_cache_one(unsigned long start, unsigned long phys)
Linus Torvalds1da177e2005-04-16 15:20:36 -070089{
Paul Mundt983f4c52009-09-01 21:12:55 +090090 unsigned long flags, exec_offset = 0;
Paul Mundt33573c02006-09-27 18:37:30 +090091
Linus Torvalds1da177e2005-04-16 15:20:36 -070092 /*
Matt Fleming1f69b6a2009-10-06 21:22:25 +000093 * All types of SH-4 require PC to be uncached to operate on the I-cache.
94 * Some types of SH-4 require PC to be uncached to operate on the D-cache.
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 */
Paul Mundt7ec9d6f2007-09-21 18:05:20 +090096 if ((boot_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) ||
Paul Mundt33573c02006-09-27 18:37:30 +090097 (start < CACHE_OC_ADDRESS_ARRAY))
Matt Fleming1f69b6a2009-10-06 21:22:25 +000098 exec_offset = cached_to_uncached;
Paul Mundt28ccf7f2006-09-27 18:30:07 +090099
Paul Mundt983f4c52009-09-01 21:12:55 +0900100 local_irq_save(flags);
Matt Fleminga781d1e2009-12-04 16:18:11 +0900101 __flush_cache_one(start, phys, exec_offset);
Paul Mundt983f4c52009-09-01 21:12:55 +0900102 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103}
104
105/*
106 * Write back & invalidate the D-cache of the page.
107 * (To avoid "alias" issues)
108 */
Paul Mundte76a0132009-08-27 11:31:16 +0900109static void sh4_flush_dcache_page(void *arg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110{
Paul Mundte76a0132009-08-27 11:31:16 +0900111 struct page *page = arg;
Paul Mundtc139a592009-08-20 15:24:41 +0900112#ifndef CONFIG_SMP
Paul Mundt2277ab42009-07-22 19:20:49 +0900113 struct address_space *mapping = page_mapping(page);
114
Paul Mundt2277ab42009-07-22 19:20:49 +0900115 if (mapping && !mapping_mapped(mapping))
116 set_bit(PG_dcache_dirty, &page->flags);
117 else
118#endif
119 {
Paul Mundt31c9efd2009-09-09 14:10:28 +0900120 unsigned long phys = page_to_phys(page);
Richard Curnowb638d0b2006-09-27 14:09:26 +0900121 unsigned long addr = CACHE_OC_ADDRESS_ARRAY;
122 int i, n;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123
124 /* Loop all the D-cache */
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900125 n = boot_cpu_data.dcache.n_aliases;
Matt Fleminga781d1e2009-12-04 16:18:11 +0900126 for (i = 0; i < n; i++, addr += PAGE_SIZE)
Valentin Sitdikova7a7c0e2009-10-16 14:15:38 +0900127 flush_cache_one(addr, phys);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128 }
Paul Mundtfdfc74f2006-09-27 14:05:52 +0900129
130 wmb();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131}
132
Paul Mundt28ccf7f2006-09-27 18:30:07 +0900133/* TODO: Selective icache invalidation through IC address array.. */
Paul Mundt205a3b42008-09-05 18:00:29 +0900134static void __uses_jump_to_uncached flush_icache_all(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135{
Paul Mundt983f4c52009-09-01 21:12:55 +0900136 unsigned long flags, ccr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137
Paul Mundt983f4c52009-09-01 21:12:55 +0900138 local_irq_save(flags);
Stuart Menefycbaa1182007-11-30 17:06:36 +0900139 jump_to_uncached();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140
141 /* Flush I-cache */
142 ccr = ctrl_inl(CCR);
143 ccr |= CCR_CACHE_ICI;
144 ctrl_outl(ccr, CCR);
145
Paul Mundt29847622006-09-27 14:57:44 +0900146 /*
Stuart Menefycbaa1182007-11-30 17:06:36 +0900147 * back_to_cached() will take care of the barrier for us, don't add
Paul Mundt29847622006-09-27 14:57:44 +0900148 * another one!
149 */
Paul Mundt983f4c52009-09-01 21:12:55 +0900150
Stuart Menefycbaa1182007-11-30 17:06:36 +0900151 back_to_cached();
Paul Mundt983f4c52009-09-01 21:12:55 +0900152 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153}
154
Paul Mundtbd6df572009-09-09 14:22:15 +0900155static void flush_dcache_all(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156{
Paul Mundtbd6df572009-09-09 14:22:15 +0900157 unsigned long addr, end_addr, entry_offset;
158
159 end_addr = CACHE_OC_ADDRESS_ARRAY +
160 (current_cpu_data.dcache.sets <<
161 current_cpu_data.dcache.entry_shift) *
162 current_cpu_data.dcache.ways;
163
164 entry_offset = 1 << current_cpu_data.dcache.entry_shift;
165
166 for (addr = CACHE_OC_ADDRESS_ARRAY; addr < end_addr; ) {
167 __raw_writel(0, addr); addr += entry_offset;
168 __raw_writel(0, addr); addr += entry_offset;
169 __raw_writel(0, addr); addr += entry_offset;
170 __raw_writel(0, addr); addr += entry_offset;
171 __raw_writel(0, addr); addr += entry_offset;
172 __raw_writel(0, addr); addr += entry_offset;
173 __raw_writel(0, addr); addr += entry_offset;
174 __raw_writel(0, addr); addr += entry_offset;
175 }
Paul Mundta2527102006-09-27 11:29:55 +0900176}
177
Paul Mundtf26b2a52009-08-21 17:23:14 +0900178static void sh4_flush_cache_all(void *unused)
Paul Mundta2527102006-09-27 11:29:55 +0900179{
180 flush_dcache_all();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 flush_icache_all();
182}
183
Paul Mundt28ccf7f2006-09-27 18:30:07 +0900184/*
185 * Note : (RPC) since the caches are physically tagged, the only point
186 * of flush_cache_mm for SH-4 is to get rid of aliases from the
187 * D-cache. The assumption elsewhere, e.g. flush_cache_range, is that
188 * lines can stay resident so long as the virtual address they were
189 * accessed with (hence cache set) is in accord with the physical
Paul Mundt654d3642009-09-09 14:04:06 +0900190 * address (i.e. tag). It's no different here.
Paul Mundt28ccf7f2006-09-27 18:30:07 +0900191 *
192 * Caller takes mm->mmap_sem.
193 */
Paul Mundtf26b2a52009-08-21 17:23:14 +0900194static void sh4_flush_cache_mm(void *arg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195{
Paul Mundtf26b2a52009-08-21 17:23:14 +0900196 struct mm_struct *mm = arg;
197
Paul Mundte7b8b7f2009-08-15 02:21:16 +0900198 if (cpu_context(smp_processor_id(), mm) == NO_CONTEXT)
199 return;
200
Paul Mundt654d3642009-09-09 14:04:06 +0900201 flush_dcache_all();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202}
203
204/*
205 * Write back and invalidate I/D-caches for the page.
206 *
207 * ADDR: Virtual Address (U0 address)
208 * PFN: Physical page number
209 */
Paul Mundtf26b2a52009-08-21 17:23:14 +0900210static void sh4_flush_cache_page(void *args)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211{
Paul Mundtf26b2a52009-08-21 17:23:14 +0900212 struct flusher_data *data = args;
213 struct vm_area_struct *vma;
Paul Mundtdeaef202009-09-09 16:06:39 +0900214 struct page *page;
Paul Mundtf26b2a52009-08-21 17:23:14 +0900215 unsigned long address, pfn, phys;
Paul Mundtdeaef202009-09-09 16:06:39 +0900216 int map_coherent = 0;
217 pgd_t *pgd;
218 pud_t *pud;
219 pmd_t *pmd;
220 pte_t *pte;
221 void *vaddr;
Richard Curnowb638d0b2006-09-27 14:09:26 +0900222
Paul Mundtf26b2a52009-08-21 17:23:14 +0900223 vma = data->vma;
Paul Mundtabeaf332009-10-16 15:14:50 +0900224 address = data->addr1 & PAGE_MASK;
Paul Mundtf26b2a52009-08-21 17:23:14 +0900225 pfn = data->addr2;
226 phys = pfn << PAGE_SHIFT;
Paul Mundtdeaef202009-09-09 16:06:39 +0900227 page = pfn_to_page(pfn);
Paul Mundtf26b2a52009-08-21 17:23:14 +0900228
Paul Mundte7b8b7f2009-08-15 02:21:16 +0900229 if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT)
230 return;
231
Paul Mundtdeaef202009-09-09 16:06:39 +0900232 pgd = pgd_offset(vma->vm_mm, address);
233 pud = pud_offset(pgd, address);
234 pmd = pmd_offset(pud, address);
235 pte = pte_offset_kernel(pmd, address);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236
Paul Mundtdeaef202009-09-09 16:06:39 +0900237 /* If the page isn't present, there is nothing to do here. */
238 if (!(pte_val(*pte) & _PAGE_PRESENT))
239 return;
240
241 if ((vma->vm_mm == current->active_mm))
242 vaddr = NULL;
243 else {
244 /*
245 * Use kmap_coherent or kmap_atomic to do flushes for
246 * another ASID than the current one.
247 */
248 map_coherent = (current_cpu_data.dcache.n_aliases &&
249 !test_bit(PG_dcache_dirty, &page->flags) &&
250 page_mapped(page));
251 if (map_coherent)
252 vaddr = kmap_coherent(page, address);
253 else
254 vaddr = kmap_atomic(page, KM_USER0);
255
256 address = (unsigned long)vaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257 }
258
Matt Fleminge717cc62009-12-08 14:23:11 +0000259 flush_cache_one(CACHE_OC_ADDRESS_ARRAY |
Paul Mundtdeaef202009-09-09 16:06:39 +0900260 (address & shm_align_mask), phys);
261
262 if (vma->vm_flags & VM_EXEC)
263 flush_icache_all();
264
265 if (vaddr) {
266 if (map_coherent)
267 kunmap_coherent(vaddr);
268 else
269 kunmap_atomic(vaddr, KM_USER0);
Richard Curnowb638d0b2006-09-27 14:09:26 +0900270 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271}
272
273/*
274 * Write back and invalidate D-caches.
275 *
276 * START, END: Virtual Address (U0 address)
277 *
278 * NOTE: We need to flush the _physical_ page entry.
279 * Flushing the cache lines for U0 only isn't enough.
280 * We need to flush for P1 too, which may contain aliases.
281 */
Paul Mundtf26b2a52009-08-21 17:23:14 +0900282static void sh4_flush_cache_range(void *args)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283{
Paul Mundtf26b2a52009-08-21 17:23:14 +0900284 struct flusher_data *data = args;
285 struct vm_area_struct *vma;
286 unsigned long start, end;
287
288 vma = data->vma;
289 start = data->addr1;
290 end = data->addr2;
291
Paul Mundte7b8b7f2009-08-15 02:21:16 +0900292 if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT)
293 return;
294
Richard Curnowb638d0b2006-09-27 14:09:26 +0900295 /*
296 * If cache is only 4k-per-way, there are never any 'aliases'. Since
297 * the cache is physically tagged, the data can just be left in there.
298 */
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900299 if (boot_cpu_data.dcache.n_aliases == 0)
Richard Curnowb638d0b2006-09-27 14:09:26 +0900300 return;
301
Paul Mundt654d3642009-09-09 14:04:06 +0900302 flush_dcache_all();
Richard Curnowb638d0b2006-09-27 14:09:26 +0900303
Paul Mundt654d3642009-09-09 14:04:06 +0900304 if (vma->vm_flags & VM_EXEC)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305 flush_icache_all();
306}
307
Richard Curnowb638d0b2006-09-27 14:09:26 +0900308/**
Valentin Sitdikova7a7c0e2009-10-16 14:15:38 +0900309 * __flush_cache_one
Richard Curnowb638d0b2006-09-27 14:09:26 +0900310 *
311 * @addr: address in memory mapped cache array
312 * @phys: P1 address to flush (has to match tags if addr has 'A' bit
313 * set i.e. associative write)
314 * @exec_offset: set to 0x20000000 if flush has to be executed from P2
315 * region else 0x0
316 *
317 * The offset into the cache array implied by 'addr' selects the
318 * 'colour' of the virtual address range that will be flushed. The
319 * operation (purge/write-back) is selected by the lower 2 bits of
320 * 'phys'.
321 */
Valentin Sitdikova7a7c0e2009-10-16 14:15:38 +0900322static void __flush_cache_one(unsigned long addr, unsigned long phys,
Richard Curnowb638d0b2006-09-27 14:09:26 +0900323 unsigned long exec_offset)
324{
325 int way_count;
326 unsigned long base_addr = addr;
327 struct cache_info *dcache;
328 unsigned long way_incr;
329 unsigned long a, ea, p;
330 unsigned long temp_pc;
331
Paul Mundt7ec9d6f2007-09-21 18:05:20 +0900332 dcache = &boot_cpu_data.dcache;
Richard Curnowb638d0b2006-09-27 14:09:26 +0900333 /* Write this way for better assembly. */
334 way_count = dcache->ways;
335 way_incr = dcache->way_incr;
336
337 /*
338 * Apply exec_offset (i.e. branch to P2 if required.).
339 *
340 * FIXME:
341 *
342 * If I write "=r" for the (temp_pc), it puts this in r6 hence
343 * trashing exec_offset before it's been added on - why? Hence
344 * "=&r" as a 'workaround'
345 */
346 asm volatile("mov.l 1f, %0\n\t"
347 "add %1, %0\n\t"
348 "jmp @%0\n\t"
349 "nop\n\t"
350 ".balign 4\n\t"
351 "1: .long 2f\n\t"
352 "2:\n" : "=&r" (temp_pc) : "r" (exec_offset));
353
354 /*
355 * We know there will be >=1 iteration, so write as do-while to avoid
356 * pointless nead-of-loop check for 0 iterations.
357 */
358 do {
359 ea = base_addr + PAGE_SIZE;
360 a = base_addr;
361 p = phys;
362
363 do {
364 *(volatile unsigned long *)a = p;
365 /*
366 * Next line: intentionally not p+32, saves an add, p
367 * will do since only the cache tag bits need to
368 * match.
369 */
370 *(volatile unsigned long *)(a+32) = p;
371 a += 64;
372 p += 64;
373 } while (a < ea);
374
375 base_addr += way_incr;
376 } while (--way_count != 0);
377}
378
Paul Mundt37443ef2009-08-15 12:29:49 +0900379extern void __weak sh4__flush_region_init(void);
380
381/*
382 * SH-4 has virtually indexed and physically tagged cache.
383 */
384void __init sh4_cache_init(void)
385{
386 printk("PVR=%08x CVR=%08x PRR=%08x\n",
387 ctrl_inl(CCN_PVR),
388 ctrl_inl(CCN_CVR),
389 ctrl_inl(CCN_PRR));
390
Paul Mundtf26b2a52009-08-21 17:23:14 +0900391 local_flush_icache_range = sh4_flush_icache_range;
392 local_flush_dcache_page = sh4_flush_dcache_page;
393 local_flush_cache_all = sh4_flush_cache_all;
394 local_flush_cache_mm = sh4_flush_cache_mm;
395 local_flush_cache_dup_mm = sh4_flush_cache_mm;
396 local_flush_cache_page = sh4_flush_cache_page;
397 local_flush_cache_range = sh4_flush_cache_range;
Paul Mundt37443ef2009-08-15 12:29:49 +0900398
399 sh4__flush_region_init();
400}