Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/sh/mm/cache-sh4.c |
| 3 | * |
| 4 | * Copyright (C) 1999, 2000, 2002 Niibe Yutaka |
Paul Mundt | deaef20 | 2009-09-09 16:06:39 +0900 | [diff] [blame] | 5 | * Copyright (C) 2001 - 2009 Paul Mundt |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * Copyright (C) 2003 Richard Curnow |
Chris Smith | 09b5a10 | 2008-07-02 15:17:11 +0900 | [diff] [blame] | 7 | * Copyright (c) 2007 STMicroelectronics (R&D) Ltd. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * |
| 9 | * This file is subject to the terms and conditions of the GNU General Public |
| 10 | * License. See the file "COPYING" in the main directory of this archive |
| 11 | * for more details. |
| 12 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <linux/init.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/mm.h> |
Paul Mundt | 52e2778 | 2006-11-21 11:09:41 +0900 | [diff] [blame] | 15 | #include <linux/io.h> |
| 16 | #include <linux/mutex.h> |
Paul Mundt | 2277ab4 | 2009-07-22 19:20:49 +0900 | [diff] [blame] | 17 | #include <linux/fs.h> |
Paul Mundt | deaef20 | 2009-09-09 16:06:39 +0900 | [diff] [blame] | 18 | #include <linux/highmem.h> |
| 19 | #include <asm/pgtable.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | #include <asm/mmu_context.h> |
| 21 | #include <asm/cacheflush.h> |
| 22 | |
Paul Mundt | 28ccf7f | 2006-09-27 18:30:07 +0900 | [diff] [blame] | 23 | /* |
| 24 | * The maximum number of pages we support up to when doing ranged dcache |
| 25 | * flushing. Anything exceeding this will simply flush the dcache in its |
| 26 | * entirety. |
| 27 | */ |
Chris Smith | 09b5a10 | 2008-07-02 15:17:11 +0900 | [diff] [blame] | 28 | #define MAX_ICACHE_PAGES 32 |
Paul Mundt | 28ccf7f | 2006-09-27 18:30:07 +0900 | [diff] [blame] | 29 | |
Valentin Sitdikov | a7a7c0e | 2009-10-16 14:15:38 +0900 | [diff] [blame] | 30 | static void __flush_cache_one(unsigned long addr, unsigned long phys, |
Paul Mundt | a252710 | 2006-09-27 11:29:55 +0900 | [diff] [blame] | 31 | unsigned long exec_offset); |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 32 | |
| 33 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | * Write back the range of D-cache, and purge the I-cache. |
| 35 | * |
Chris Smith | 09b5a10 | 2008-07-02 15:17:11 +0900 | [diff] [blame] | 36 | * Called from kernel/module.c:sys_init_module and routine for a.out format, |
| 37 | * signal handler code and kprobes code |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 38 | */ |
Matt Fleming | a632524 | 2009-10-06 21:22:21 +0000 | [diff] [blame] | 39 | static void __uses_jump_to_uncached sh4_flush_icache_range(void *args) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | { |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 41 | struct flusher_data *data = args; |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 42 | unsigned long start, end; |
Paul Mundt | 983f4c5 | 2009-09-01 21:12:55 +0900 | [diff] [blame] | 43 | unsigned long flags, v; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | int i; |
| 45 | |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 46 | start = data->addr1; |
| 47 | end = data->addr2; |
| 48 | |
Paul Mundt | 682f88a | 2009-09-09 13:19:46 +0900 | [diff] [blame] | 49 | /* If there are too many pages then just blow away the caches */ |
| 50 | if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) { |
| 51 | local_flush_cache_all(NULL); |
| 52 | return; |
Chris Smith | 09b5a10 | 2008-07-02 15:17:11 +0900 | [diff] [blame] | 53 | } |
Paul Mundt | 682f88a | 2009-09-09 13:19:46 +0900 | [diff] [blame] | 54 | |
| 55 | /* |
| 56 | * Selectively flush d-cache then invalidate the i-cache. |
| 57 | * This is inefficient, so only use this for small ranges. |
| 58 | */ |
| 59 | start &= ~(L1_CACHE_BYTES-1); |
| 60 | end += L1_CACHE_BYTES-1; |
| 61 | end &= ~(L1_CACHE_BYTES-1); |
| 62 | |
| 63 | local_irq_save(flags); |
| 64 | jump_to_uncached(); |
| 65 | |
| 66 | for (v = start; v < end; v += L1_CACHE_BYTES) { |
| 67 | unsigned long icacheaddr; |
Matt Fleming | a9d244a | 2009-11-05 23:14:39 +0000 | [diff] [blame] | 68 | int j, n; |
Paul Mundt | 682f88a | 2009-09-09 13:19:46 +0900 | [diff] [blame] | 69 | |
| 70 | __ocbwb(v); |
| 71 | |
| 72 | icacheaddr = CACHE_IC_ADDRESS_ARRAY | (v & |
| 73 | cpu_data->icache.entry_mask); |
| 74 | |
| 75 | /* Clear i-cache line valid-bit */ |
Matt Fleming | a9d244a | 2009-11-05 23:14:39 +0000 | [diff] [blame] | 76 | n = boot_cpu_data.icache.n_aliases; |
Paul Mundt | 682f88a | 2009-09-09 13:19:46 +0900 | [diff] [blame] | 77 | for (i = 0; i < cpu_data->icache.ways; i++) { |
Matt Fleming | a9d244a | 2009-11-05 23:14:39 +0000 | [diff] [blame] | 78 | for (j = 0; j < n; j++) |
| 79 | __raw_writel(0, icacheaddr + (j * PAGE_SIZE)); |
Paul Mundt | 682f88a | 2009-09-09 13:19:46 +0900 | [diff] [blame] | 80 | icacheaddr += cpu_data->icache.way_incr; |
| 81 | } |
| 82 | } |
| 83 | |
| 84 | back_to_cached(); |
| 85 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | } |
| 87 | |
Valentin Sitdikov | a7a7c0e | 2009-10-16 14:15:38 +0900 | [diff] [blame] | 88 | static inline void flush_cache_one(unsigned long start, unsigned long phys) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | { |
Paul Mundt | 983f4c5 | 2009-09-01 21:12:55 +0900 | [diff] [blame] | 90 | unsigned long flags, exec_offset = 0; |
Paul Mundt | 33573c0 | 2006-09-27 18:37:30 +0900 | [diff] [blame] | 91 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | /* |
Matt Fleming | 1f69b6a | 2009-10-06 21:22:25 +0000 | [diff] [blame] | 93 | * All types of SH-4 require PC to be uncached to operate on the I-cache. |
| 94 | * Some types of SH-4 require PC to be uncached to operate on the D-cache. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | */ |
Paul Mundt | 7ec9d6f | 2007-09-21 18:05:20 +0900 | [diff] [blame] | 96 | if ((boot_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) || |
Paul Mundt | 33573c0 | 2006-09-27 18:37:30 +0900 | [diff] [blame] | 97 | (start < CACHE_OC_ADDRESS_ARRAY)) |
Matt Fleming | 1f69b6a | 2009-10-06 21:22:25 +0000 | [diff] [blame] | 98 | exec_offset = cached_to_uncached; |
Paul Mundt | 28ccf7f | 2006-09-27 18:30:07 +0900 | [diff] [blame] | 99 | |
Paul Mundt | 983f4c5 | 2009-09-01 21:12:55 +0900 | [diff] [blame] | 100 | local_irq_save(flags); |
Matt Fleming | a781d1e | 2009-12-04 16:18:11 +0900 | [diff] [blame] | 101 | __flush_cache_one(start, phys, exec_offset); |
Paul Mundt | 983f4c5 | 2009-09-01 21:12:55 +0900 | [diff] [blame] | 102 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | /* |
| 106 | * Write back & invalidate the D-cache of the page. |
| 107 | * (To avoid "alias" issues) |
| 108 | */ |
Paul Mundt | e76a013 | 2009-08-27 11:31:16 +0900 | [diff] [blame] | 109 | static void sh4_flush_dcache_page(void *arg) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | { |
Paul Mundt | e76a013 | 2009-08-27 11:31:16 +0900 | [diff] [blame] | 111 | struct page *page = arg; |
Paul Mundt | c139a59 | 2009-08-20 15:24:41 +0900 | [diff] [blame] | 112 | #ifndef CONFIG_SMP |
Paul Mundt | 2277ab4 | 2009-07-22 19:20:49 +0900 | [diff] [blame] | 113 | struct address_space *mapping = page_mapping(page); |
| 114 | |
Paul Mundt | 2277ab4 | 2009-07-22 19:20:49 +0900 | [diff] [blame] | 115 | if (mapping && !mapping_mapped(mapping)) |
| 116 | set_bit(PG_dcache_dirty, &page->flags); |
| 117 | else |
| 118 | #endif |
| 119 | { |
Paul Mundt | 31c9efd | 2009-09-09 14:10:28 +0900 | [diff] [blame] | 120 | unsigned long phys = page_to_phys(page); |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 121 | unsigned long addr = CACHE_OC_ADDRESS_ARRAY; |
| 122 | int i, n; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 123 | |
| 124 | /* Loop all the D-cache */ |
Paul Mundt | 7ec9d6f | 2007-09-21 18:05:20 +0900 | [diff] [blame] | 125 | n = boot_cpu_data.dcache.n_aliases; |
Matt Fleming | a781d1e | 2009-12-04 16:18:11 +0900 | [diff] [blame] | 126 | for (i = 0; i < n; i++, addr += PAGE_SIZE) |
Valentin Sitdikov | a7a7c0e | 2009-10-16 14:15:38 +0900 | [diff] [blame] | 127 | flush_cache_one(addr, phys); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 128 | } |
Paul Mundt | fdfc74f | 2006-09-27 14:05:52 +0900 | [diff] [blame] | 129 | |
| 130 | wmb(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 131 | } |
| 132 | |
Paul Mundt | 28ccf7f | 2006-09-27 18:30:07 +0900 | [diff] [blame] | 133 | /* TODO: Selective icache invalidation through IC address array.. */ |
Paul Mundt | 205a3b4 | 2008-09-05 18:00:29 +0900 | [diff] [blame] | 134 | static void __uses_jump_to_uncached flush_icache_all(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 135 | { |
Paul Mundt | 983f4c5 | 2009-09-01 21:12:55 +0900 | [diff] [blame] | 136 | unsigned long flags, ccr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | |
Paul Mundt | 983f4c5 | 2009-09-01 21:12:55 +0900 | [diff] [blame] | 138 | local_irq_save(flags); |
Stuart Menefy | cbaa118 | 2007-11-30 17:06:36 +0900 | [diff] [blame] | 139 | jump_to_uncached(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 140 | |
| 141 | /* Flush I-cache */ |
| 142 | ccr = ctrl_inl(CCR); |
| 143 | ccr |= CCR_CACHE_ICI; |
| 144 | ctrl_outl(ccr, CCR); |
| 145 | |
Paul Mundt | 2984762 | 2006-09-27 14:57:44 +0900 | [diff] [blame] | 146 | /* |
Stuart Menefy | cbaa118 | 2007-11-30 17:06:36 +0900 | [diff] [blame] | 147 | * back_to_cached() will take care of the barrier for us, don't add |
Paul Mundt | 2984762 | 2006-09-27 14:57:44 +0900 | [diff] [blame] | 148 | * another one! |
| 149 | */ |
Paul Mundt | 983f4c5 | 2009-09-01 21:12:55 +0900 | [diff] [blame] | 150 | |
Stuart Menefy | cbaa118 | 2007-11-30 17:06:36 +0900 | [diff] [blame] | 151 | back_to_cached(); |
Paul Mundt | 983f4c5 | 2009-09-01 21:12:55 +0900 | [diff] [blame] | 152 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 153 | } |
| 154 | |
Paul Mundt | bd6df57 | 2009-09-09 14:22:15 +0900 | [diff] [blame] | 155 | static void flush_dcache_all(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | { |
Paul Mundt | bd6df57 | 2009-09-09 14:22:15 +0900 | [diff] [blame] | 157 | unsigned long addr, end_addr, entry_offset; |
| 158 | |
| 159 | end_addr = CACHE_OC_ADDRESS_ARRAY + |
| 160 | (current_cpu_data.dcache.sets << |
| 161 | current_cpu_data.dcache.entry_shift) * |
| 162 | current_cpu_data.dcache.ways; |
| 163 | |
| 164 | entry_offset = 1 << current_cpu_data.dcache.entry_shift; |
| 165 | |
| 166 | for (addr = CACHE_OC_ADDRESS_ARRAY; addr < end_addr; ) { |
| 167 | __raw_writel(0, addr); addr += entry_offset; |
| 168 | __raw_writel(0, addr); addr += entry_offset; |
| 169 | __raw_writel(0, addr); addr += entry_offset; |
| 170 | __raw_writel(0, addr); addr += entry_offset; |
| 171 | __raw_writel(0, addr); addr += entry_offset; |
| 172 | __raw_writel(0, addr); addr += entry_offset; |
| 173 | __raw_writel(0, addr); addr += entry_offset; |
| 174 | __raw_writel(0, addr); addr += entry_offset; |
| 175 | } |
Paul Mundt | a252710 | 2006-09-27 11:29:55 +0900 | [diff] [blame] | 176 | } |
| 177 | |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 178 | static void sh4_flush_cache_all(void *unused) |
Paul Mundt | a252710 | 2006-09-27 11:29:55 +0900 | [diff] [blame] | 179 | { |
| 180 | flush_dcache_all(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | flush_icache_all(); |
| 182 | } |
| 183 | |
Paul Mundt | 28ccf7f | 2006-09-27 18:30:07 +0900 | [diff] [blame] | 184 | /* |
| 185 | * Note : (RPC) since the caches are physically tagged, the only point |
| 186 | * of flush_cache_mm for SH-4 is to get rid of aliases from the |
| 187 | * D-cache. The assumption elsewhere, e.g. flush_cache_range, is that |
| 188 | * lines can stay resident so long as the virtual address they were |
| 189 | * accessed with (hence cache set) is in accord with the physical |
Paul Mundt | 654d364 | 2009-09-09 14:04:06 +0900 | [diff] [blame] | 190 | * address (i.e. tag). It's no different here. |
Paul Mundt | 28ccf7f | 2006-09-27 18:30:07 +0900 | [diff] [blame] | 191 | * |
| 192 | * Caller takes mm->mmap_sem. |
| 193 | */ |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 194 | static void sh4_flush_cache_mm(void *arg) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | { |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 196 | struct mm_struct *mm = arg; |
| 197 | |
Paul Mundt | e7b8b7f | 2009-08-15 02:21:16 +0900 | [diff] [blame] | 198 | if (cpu_context(smp_processor_id(), mm) == NO_CONTEXT) |
| 199 | return; |
| 200 | |
Paul Mundt | 654d364 | 2009-09-09 14:04:06 +0900 | [diff] [blame] | 201 | flush_dcache_all(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 202 | } |
| 203 | |
| 204 | /* |
| 205 | * Write back and invalidate I/D-caches for the page. |
| 206 | * |
| 207 | * ADDR: Virtual Address (U0 address) |
| 208 | * PFN: Physical page number |
| 209 | */ |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 210 | static void sh4_flush_cache_page(void *args) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 211 | { |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 212 | struct flusher_data *data = args; |
| 213 | struct vm_area_struct *vma; |
Paul Mundt | deaef20 | 2009-09-09 16:06:39 +0900 | [diff] [blame] | 214 | struct page *page; |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 215 | unsigned long address, pfn, phys; |
Paul Mundt | deaef20 | 2009-09-09 16:06:39 +0900 | [diff] [blame] | 216 | int map_coherent = 0; |
| 217 | pgd_t *pgd; |
| 218 | pud_t *pud; |
| 219 | pmd_t *pmd; |
| 220 | pte_t *pte; |
| 221 | void *vaddr; |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 222 | |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 223 | vma = data->vma; |
Paul Mundt | abeaf33 | 2009-10-16 15:14:50 +0900 | [diff] [blame] | 224 | address = data->addr1 & PAGE_MASK; |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 225 | pfn = data->addr2; |
| 226 | phys = pfn << PAGE_SHIFT; |
Paul Mundt | deaef20 | 2009-09-09 16:06:39 +0900 | [diff] [blame] | 227 | page = pfn_to_page(pfn); |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 228 | |
Paul Mundt | e7b8b7f | 2009-08-15 02:21:16 +0900 | [diff] [blame] | 229 | if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT) |
| 230 | return; |
| 231 | |
Paul Mundt | deaef20 | 2009-09-09 16:06:39 +0900 | [diff] [blame] | 232 | pgd = pgd_offset(vma->vm_mm, address); |
| 233 | pud = pud_offset(pgd, address); |
| 234 | pmd = pmd_offset(pud, address); |
| 235 | pte = pte_offset_kernel(pmd, address); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | |
Paul Mundt | deaef20 | 2009-09-09 16:06:39 +0900 | [diff] [blame] | 237 | /* If the page isn't present, there is nothing to do here. */ |
| 238 | if (!(pte_val(*pte) & _PAGE_PRESENT)) |
| 239 | return; |
| 240 | |
| 241 | if ((vma->vm_mm == current->active_mm)) |
| 242 | vaddr = NULL; |
| 243 | else { |
| 244 | /* |
| 245 | * Use kmap_coherent or kmap_atomic to do flushes for |
| 246 | * another ASID than the current one. |
| 247 | */ |
| 248 | map_coherent = (current_cpu_data.dcache.n_aliases && |
| 249 | !test_bit(PG_dcache_dirty, &page->flags) && |
| 250 | page_mapped(page)); |
| 251 | if (map_coherent) |
| 252 | vaddr = kmap_coherent(page, address); |
| 253 | else |
| 254 | vaddr = kmap_atomic(page, KM_USER0); |
| 255 | |
| 256 | address = (unsigned long)vaddr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | } |
| 258 | |
Matt Fleming | e717cc6 | 2009-12-08 14:23:11 +0000 | [diff] [blame] | 259 | flush_cache_one(CACHE_OC_ADDRESS_ARRAY | |
Paul Mundt | deaef20 | 2009-09-09 16:06:39 +0900 | [diff] [blame] | 260 | (address & shm_align_mask), phys); |
| 261 | |
| 262 | if (vma->vm_flags & VM_EXEC) |
| 263 | flush_icache_all(); |
| 264 | |
| 265 | if (vaddr) { |
| 266 | if (map_coherent) |
| 267 | kunmap_coherent(vaddr); |
| 268 | else |
| 269 | kunmap_atomic(vaddr, KM_USER0); |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 270 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 271 | } |
| 272 | |
| 273 | /* |
| 274 | * Write back and invalidate D-caches. |
| 275 | * |
| 276 | * START, END: Virtual Address (U0 address) |
| 277 | * |
| 278 | * NOTE: We need to flush the _physical_ page entry. |
| 279 | * Flushing the cache lines for U0 only isn't enough. |
| 280 | * We need to flush for P1 too, which may contain aliases. |
| 281 | */ |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 282 | static void sh4_flush_cache_range(void *args) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | { |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 284 | struct flusher_data *data = args; |
| 285 | struct vm_area_struct *vma; |
| 286 | unsigned long start, end; |
| 287 | |
| 288 | vma = data->vma; |
| 289 | start = data->addr1; |
| 290 | end = data->addr2; |
| 291 | |
Paul Mundt | e7b8b7f | 2009-08-15 02:21:16 +0900 | [diff] [blame] | 292 | if (cpu_context(smp_processor_id(), vma->vm_mm) == NO_CONTEXT) |
| 293 | return; |
| 294 | |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 295 | /* |
| 296 | * If cache is only 4k-per-way, there are never any 'aliases'. Since |
| 297 | * the cache is physically tagged, the data can just be left in there. |
| 298 | */ |
Paul Mundt | 7ec9d6f | 2007-09-21 18:05:20 +0900 | [diff] [blame] | 299 | if (boot_cpu_data.dcache.n_aliases == 0) |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 300 | return; |
| 301 | |
Paul Mundt | 654d364 | 2009-09-09 14:04:06 +0900 | [diff] [blame] | 302 | flush_dcache_all(); |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 303 | |
Paul Mundt | 654d364 | 2009-09-09 14:04:06 +0900 | [diff] [blame] | 304 | if (vma->vm_flags & VM_EXEC) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 305 | flush_icache_all(); |
| 306 | } |
| 307 | |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 308 | /** |
Valentin Sitdikov | a7a7c0e | 2009-10-16 14:15:38 +0900 | [diff] [blame] | 309 | * __flush_cache_one |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 310 | * |
| 311 | * @addr: address in memory mapped cache array |
| 312 | * @phys: P1 address to flush (has to match tags if addr has 'A' bit |
| 313 | * set i.e. associative write) |
| 314 | * @exec_offset: set to 0x20000000 if flush has to be executed from P2 |
| 315 | * region else 0x0 |
| 316 | * |
| 317 | * The offset into the cache array implied by 'addr' selects the |
| 318 | * 'colour' of the virtual address range that will be flushed. The |
| 319 | * operation (purge/write-back) is selected by the lower 2 bits of |
| 320 | * 'phys'. |
| 321 | */ |
Valentin Sitdikov | a7a7c0e | 2009-10-16 14:15:38 +0900 | [diff] [blame] | 322 | static void __flush_cache_one(unsigned long addr, unsigned long phys, |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 323 | unsigned long exec_offset) |
| 324 | { |
| 325 | int way_count; |
| 326 | unsigned long base_addr = addr; |
| 327 | struct cache_info *dcache; |
| 328 | unsigned long way_incr; |
| 329 | unsigned long a, ea, p; |
| 330 | unsigned long temp_pc; |
| 331 | |
Paul Mundt | 7ec9d6f | 2007-09-21 18:05:20 +0900 | [diff] [blame] | 332 | dcache = &boot_cpu_data.dcache; |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 333 | /* Write this way for better assembly. */ |
| 334 | way_count = dcache->ways; |
| 335 | way_incr = dcache->way_incr; |
| 336 | |
| 337 | /* |
| 338 | * Apply exec_offset (i.e. branch to P2 if required.). |
| 339 | * |
| 340 | * FIXME: |
| 341 | * |
| 342 | * If I write "=r" for the (temp_pc), it puts this in r6 hence |
| 343 | * trashing exec_offset before it's been added on - why? Hence |
| 344 | * "=&r" as a 'workaround' |
| 345 | */ |
| 346 | asm volatile("mov.l 1f, %0\n\t" |
| 347 | "add %1, %0\n\t" |
| 348 | "jmp @%0\n\t" |
| 349 | "nop\n\t" |
| 350 | ".balign 4\n\t" |
| 351 | "1: .long 2f\n\t" |
| 352 | "2:\n" : "=&r" (temp_pc) : "r" (exec_offset)); |
| 353 | |
| 354 | /* |
| 355 | * We know there will be >=1 iteration, so write as do-while to avoid |
| 356 | * pointless nead-of-loop check for 0 iterations. |
| 357 | */ |
| 358 | do { |
| 359 | ea = base_addr + PAGE_SIZE; |
| 360 | a = base_addr; |
| 361 | p = phys; |
| 362 | |
| 363 | do { |
| 364 | *(volatile unsigned long *)a = p; |
| 365 | /* |
| 366 | * Next line: intentionally not p+32, saves an add, p |
| 367 | * will do since only the cache tag bits need to |
| 368 | * match. |
| 369 | */ |
| 370 | *(volatile unsigned long *)(a+32) = p; |
| 371 | a += 64; |
| 372 | p += 64; |
| 373 | } while (a < ea); |
| 374 | |
| 375 | base_addr += way_incr; |
| 376 | } while (--way_count != 0); |
| 377 | } |
| 378 | |
Paul Mundt | 37443ef | 2009-08-15 12:29:49 +0900 | [diff] [blame] | 379 | extern void __weak sh4__flush_region_init(void); |
| 380 | |
| 381 | /* |
| 382 | * SH-4 has virtually indexed and physically tagged cache. |
| 383 | */ |
| 384 | void __init sh4_cache_init(void) |
| 385 | { |
| 386 | printk("PVR=%08x CVR=%08x PRR=%08x\n", |
| 387 | ctrl_inl(CCN_PVR), |
| 388 | ctrl_inl(CCN_CVR), |
| 389 | ctrl_inl(CCN_PRR)); |
| 390 | |
Paul Mundt | f26b2a5 | 2009-08-21 17:23:14 +0900 | [diff] [blame] | 391 | local_flush_icache_range = sh4_flush_icache_range; |
| 392 | local_flush_dcache_page = sh4_flush_dcache_page; |
| 393 | local_flush_cache_all = sh4_flush_cache_all; |
| 394 | local_flush_cache_mm = sh4_flush_cache_mm; |
| 395 | local_flush_cache_dup_mm = sh4_flush_cache_mm; |
| 396 | local_flush_cache_page = sh4_flush_cache_page; |
| 397 | local_flush_cache_range = sh4_flush_cache_range; |
Paul Mundt | 37443ef | 2009-08-15 12:29:49 +0900 | [diff] [blame] | 398 | |
| 399 | sh4__flush_region_init(); |
| 400 | } |