SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 1 | /* |
Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * linux/arch/arm/mach-at91/clock.c |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2005 David Brownell |
| 5 | * Copyright (C) 2005 Ivan Kokshaysky |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/fs.h> |
| 17 | #include <linux/debugfs.h> |
| 18 | #include <linux/seq_file.h> |
| 19 | #include <linux/list.h> |
| 20 | #include <linux/errno.h> |
| 21 | #include <linux/err.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/clk.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 25 | #include <linux/io.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 26 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 27 | #include <mach/hardware.h> |
| 28 | #include <mach/at91_pmc.h> |
| 29 | #include <mach/cpu.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 30 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 31 | #include "clock.h" |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 32 | |
Andrew Victor | 55c20c0 | 2006-06-20 19:31:39 +0100 | [diff] [blame] | 33 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 34 | /* |
| 35 | * There's a lot more which can be done with clocks, including cpufreq |
| 36 | * integration, slow clock mode support (for system suspend), letting |
| 37 | * PLLB be used at other rates (on boards that don't need USB), etc. |
| 38 | */ |
| 39 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 40 | #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) |
| 41 | #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) |
| 42 | #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL) |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 43 | #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 44 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 45 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 46 | /* |
| 47 | * Chips have some kind of clocks : group them by functionality |
| 48 | */ |
| 49 | #define cpu_has_utmi() ( cpu_is_at91cap9() \ |
| 50 | || cpu_is_at91sam9rl()) |
| 51 | |
| 52 | #define cpu_has_800M_plla() (cpu_is_at91sam9g20()) |
| 53 | |
| 54 | #define cpu_has_pllb() (!cpu_is_at91sam9rl()) |
| 55 | |
| 56 | #define cpu_has_upll() (0) |
| 57 | |
| 58 | /* USB host HS & FS */ |
| 59 | #define cpu_has_uhp() (!cpu_is_at91sam9rl()) |
| 60 | |
| 61 | /* USB device FS only */ |
| 62 | #define cpu_has_udpfs() (!cpu_is_at91sam9rl()) |
| 63 | |
| 64 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 65 | static LIST_HEAD(clocks); |
| 66 | static DEFINE_SPINLOCK(clk_lock); |
| 67 | |
| 68 | static u32 at91_pllb_usb_init; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 69 | |
| 70 | /* |
| 71 | * Four primary clock sources: two crystal oscillators (32K, main), and |
| 72 | * two PLLs. PLLA usually runs the master clock; and PLLB must run at |
| 73 | * 48 MHz (unless no USB function clocks are needed). The main clock and |
| 74 | * both PLLs are turned off to run in "slow clock mode" (system suspend). |
| 75 | */ |
| 76 | static struct clk clk32k = { |
| 77 | .name = "clk32k", |
| 78 | .rate_hz = AT91_SLOW_CLOCK, |
| 79 | .users = 1, /* always on */ |
| 80 | .id = 0, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 81 | .type = CLK_TYPE_PRIMARY, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 82 | }; |
| 83 | static struct clk main_clk = { |
| 84 | .name = "main", |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 85 | .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 86 | .id = 1, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 87 | .type = CLK_TYPE_PRIMARY, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 88 | }; |
| 89 | static struct clk plla = { |
| 90 | .name = "plla", |
| 91 | .parent = &main_clk, |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 92 | .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 93 | .id = 2, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 94 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 95 | }; |
| 96 | |
| 97 | static void pllb_mode(struct clk *clk, int is_on) |
| 98 | { |
| 99 | u32 value; |
| 100 | |
| 101 | if (is_on) { |
| 102 | is_on = AT91_PMC_LOCKB; |
| 103 | value = at91_pllb_usb_init; |
| 104 | } else |
| 105 | value = 0; |
| 106 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 107 | // REVISIT: Add work-around for AT91RM9200 Errata #26 ? |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 108 | at91_sys_write(AT91_CKGR_PLLBR, value); |
| 109 | |
| 110 | do { |
| 111 | cpu_relax(); |
| 112 | } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); |
| 113 | } |
| 114 | |
| 115 | static struct clk pllb = { |
| 116 | .name = "pllb", |
| 117 | .parent = &main_clk, |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 118 | .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 119 | .mode = pllb_mode, |
| 120 | .id = 3, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 121 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 122 | }; |
| 123 | |
| 124 | static void pmc_sys_mode(struct clk *clk, int is_on) |
| 125 | { |
| 126 | if (is_on) |
| 127 | at91_sys_write(AT91_PMC_SCER, clk->pmc_mask); |
| 128 | else |
| 129 | at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); |
| 130 | } |
| 131 | |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 132 | static void pmc_uckr_mode(struct clk *clk, int is_on) |
| 133 | { |
| 134 | unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR); |
| 135 | |
| 136 | if (is_on) { |
| 137 | is_on = AT91_PMC_LOCKU; |
| 138 | at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); |
| 139 | } else |
| 140 | at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask)); |
| 141 | |
| 142 | do { |
| 143 | cpu_relax(); |
| 144 | } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); |
| 145 | } |
| 146 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 147 | /* USB function clocks (PLLB must be 48 MHz) */ |
| 148 | static struct clk udpck = { |
| 149 | .name = "udpck", |
| 150 | .parent = &pllb, |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 151 | .mode = pmc_sys_mode, |
| 152 | }; |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 153 | static struct clk utmi_clk = { |
| 154 | .name = "utmi_clk", |
| 155 | .parent = &main_clk, |
| 156 | .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */ |
| 157 | .mode = pmc_uckr_mode, |
| 158 | .type = CLK_TYPE_PLL, |
| 159 | }; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 160 | static struct clk uhpck = { |
| 161 | .name = "uhpck", |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 162 | /*.parent = ... we choose parent at runtime */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 163 | .mode = pmc_sys_mode, |
| 164 | }; |
| 165 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 166 | |
| 167 | /* |
| 168 | * The master clock is divided from the CPU clock (by 1-4). It's used for |
| 169 | * memory, interfaces to on-chip peripherals, the AIC, and sometimes more |
| 170 | * (e.g baud rate generation). It's sourced from one of the primary clocks. |
| 171 | */ |
| 172 | static struct clk mck = { |
| 173 | .name = "mck", |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 174 | .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 175 | }; |
| 176 | |
| 177 | static void pmc_periph_mode(struct clk *clk, int is_on) |
| 178 | { |
| 179 | if (is_on) |
| 180 | at91_sys_write(AT91_PMC_PCER, clk->pmc_mask); |
| 181 | else |
| 182 | at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask); |
| 183 | } |
| 184 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 185 | static struct clk __init *at91_css_to_clk(unsigned long css) |
| 186 | { |
| 187 | switch (css) { |
| 188 | case AT91_PMC_CSS_SLOW: |
| 189 | return &clk32k; |
| 190 | case AT91_PMC_CSS_MAIN: |
| 191 | return &main_clk; |
| 192 | case AT91_PMC_CSS_PLLA: |
| 193 | return &plla; |
| 194 | case AT91_PMC_CSS_PLLB: |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 195 | if (cpu_has_upll()) |
| 196 | /* CSS_PLLB == CSS_UPLL */ |
| 197 | return &utmi_clk; |
| 198 | else if (cpu_has_pllb()) |
| 199 | return &pllb; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 200 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 201 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 202 | return NULL; |
| 203 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 204 | |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 205 | /* |
| 206 | * Associate a particular clock with a function (eg, "uart") and device. |
| 207 | * The drivers can then request the same 'function' with several different |
| 208 | * devices and not care about which clock name to use. |
| 209 | */ |
| 210 | void __init at91_clock_associate(const char *id, struct device *dev, const char *func) |
| 211 | { |
| 212 | struct clk *clk = clk_get(NULL, id); |
| 213 | |
| 214 | if (!dev || !clk || !IS_ERR(clk_get(dev, func))) |
| 215 | return; |
| 216 | |
| 217 | clk->function = func; |
| 218 | clk->dev = dev; |
| 219 | } |
| 220 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 221 | /* clocks cannot be de-registered no refcounting necessary */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 222 | struct clk *clk_get(struct device *dev, const char *id) |
| 223 | { |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 224 | struct clk *clk; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 225 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 226 | list_for_each_entry(clk, &clocks, node) { |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 227 | if (strcmp(id, clk->name) == 0) |
| 228 | return clk; |
| 229 | if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0) |
| 230 | return clk; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 231 | } |
| 232 | |
| 233 | return ERR_PTR(-ENOENT); |
| 234 | } |
| 235 | EXPORT_SYMBOL(clk_get); |
| 236 | |
| 237 | void clk_put(struct clk *clk) |
| 238 | { |
| 239 | } |
| 240 | EXPORT_SYMBOL(clk_put); |
| 241 | |
| 242 | static void __clk_enable(struct clk *clk) |
| 243 | { |
| 244 | if (clk->parent) |
| 245 | __clk_enable(clk->parent); |
| 246 | if (clk->users++ == 0 && clk->mode) |
| 247 | clk->mode(clk, 1); |
| 248 | } |
| 249 | |
| 250 | int clk_enable(struct clk *clk) |
| 251 | { |
| 252 | unsigned long flags; |
| 253 | |
| 254 | spin_lock_irqsave(&clk_lock, flags); |
| 255 | __clk_enable(clk); |
| 256 | spin_unlock_irqrestore(&clk_lock, flags); |
| 257 | return 0; |
| 258 | } |
| 259 | EXPORT_SYMBOL(clk_enable); |
| 260 | |
| 261 | static void __clk_disable(struct clk *clk) |
| 262 | { |
| 263 | BUG_ON(clk->users == 0); |
| 264 | if (--clk->users == 0 && clk->mode) |
| 265 | clk->mode(clk, 0); |
| 266 | if (clk->parent) |
| 267 | __clk_disable(clk->parent); |
| 268 | } |
| 269 | |
| 270 | void clk_disable(struct clk *clk) |
| 271 | { |
| 272 | unsigned long flags; |
| 273 | |
| 274 | spin_lock_irqsave(&clk_lock, flags); |
| 275 | __clk_disable(clk); |
| 276 | spin_unlock_irqrestore(&clk_lock, flags); |
| 277 | } |
| 278 | EXPORT_SYMBOL(clk_disable); |
| 279 | |
| 280 | unsigned long clk_get_rate(struct clk *clk) |
| 281 | { |
| 282 | unsigned long flags; |
| 283 | unsigned long rate; |
| 284 | |
| 285 | spin_lock_irqsave(&clk_lock, flags); |
| 286 | for (;;) { |
| 287 | rate = clk->rate_hz; |
| 288 | if (rate || !clk->parent) |
| 289 | break; |
| 290 | clk = clk->parent; |
| 291 | } |
| 292 | spin_unlock_irqrestore(&clk_lock, flags); |
| 293 | return rate; |
| 294 | } |
| 295 | EXPORT_SYMBOL(clk_get_rate); |
| 296 | |
| 297 | /*------------------------------------------------------------------------*/ |
| 298 | |
| 299 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS |
| 300 | |
| 301 | /* |
| 302 | * For now, only the programmable clocks support reparenting (MCK could |
| 303 | * do this too, with care) or rate changing (the PLLs could do this too, |
| 304 | * ditto MCK but that's more for cpufreq). Drivers may reparent to get |
| 305 | * a better rate match; we don't. |
| 306 | */ |
| 307 | |
| 308 | long clk_round_rate(struct clk *clk, unsigned long rate) |
| 309 | { |
| 310 | unsigned long flags; |
| 311 | unsigned prescale; |
| 312 | unsigned long actual; |
| 313 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 314 | if (!clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 315 | return -EINVAL; |
| 316 | spin_lock_irqsave(&clk_lock, flags); |
| 317 | |
| 318 | actual = clk->parent->rate_hz; |
| 319 | for (prescale = 0; prescale < 7; prescale++) { |
| 320 | if (actual && actual <= rate) |
| 321 | break; |
| 322 | actual >>= 1; |
| 323 | } |
| 324 | |
| 325 | spin_unlock_irqrestore(&clk_lock, flags); |
| 326 | return (prescale < 7) ? actual : -ENOENT; |
| 327 | } |
| 328 | EXPORT_SYMBOL(clk_round_rate); |
| 329 | |
| 330 | int clk_set_rate(struct clk *clk, unsigned long rate) |
| 331 | { |
| 332 | unsigned long flags; |
| 333 | unsigned prescale; |
| 334 | unsigned long actual; |
| 335 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 336 | if (!clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 337 | return -EINVAL; |
| 338 | if (clk->users) |
| 339 | return -EBUSY; |
| 340 | spin_lock_irqsave(&clk_lock, flags); |
| 341 | |
| 342 | actual = clk->parent->rate_hz; |
| 343 | for (prescale = 0; prescale < 7; prescale++) { |
| 344 | if (actual && actual <= rate) { |
| 345 | u32 pckr; |
| 346 | |
| 347 | pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 348 | pckr &= AT91_PMC_CSS; /* clock selection */ |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 349 | pckr |= prescale << 2; |
| 350 | at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); |
| 351 | clk->rate_hz = actual; |
| 352 | break; |
| 353 | } |
| 354 | actual >>= 1; |
| 355 | } |
| 356 | |
| 357 | spin_unlock_irqrestore(&clk_lock, flags); |
| 358 | return (prescale < 7) ? actual : -ENOENT; |
| 359 | } |
| 360 | EXPORT_SYMBOL(clk_set_rate); |
| 361 | |
| 362 | struct clk *clk_get_parent(struct clk *clk) |
| 363 | { |
| 364 | return clk->parent; |
| 365 | } |
| 366 | EXPORT_SYMBOL(clk_get_parent); |
| 367 | |
| 368 | int clk_set_parent(struct clk *clk, struct clk *parent) |
| 369 | { |
| 370 | unsigned long flags; |
| 371 | |
| 372 | if (clk->users) |
| 373 | return -EBUSY; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 374 | if (!clk_is_primary(parent) || !clk_is_programmable(clk)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 375 | return -EINVAL; |
| 376 | spin_lock_irqsave(&clk_lock, flags); |
| 377 | |
| 378 | clk->rate_hz = parent->rate_hz; |
| 379 | clk->parent = parent; |
| 380 | at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id); |
| 381 | |
| 382 | spin_unlock_irqrestore(&clk_lock, flags); |
| 383 | return 0; |
| 384 | } |
| 385 | EXPORT_SYMBOL(clk_set_parent); |
| 386 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 387 | /* establish PCK0..PCKN parentage and rate */ |
David Brownell | 72e7ae8 | 2008-02-06 22:03:42 +0100 | [diff] [blame] | 388 | static void __init init_programmable_clock(struct clk *clk) |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 389 | { |
| 390 | struct clk *parent; |
| 391 | u32 pckr; |
| 392 | |
| 393 | pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); |
| 394 | parent = at91_css_to_clk(pckr & AT91_PMC_CSS); |
| 395 | clk->parent = parent; |
Andrew Victor | a95c729 | 2007-11-19 11:52:09 +0100 | [diff] [blame] | 396 | clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2)); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 397 | } |
| 398 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 399 | #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ |
| 400 | |
| 401 | /*------------------------------------------------------------------------*/ |
| 402 | |
| 403 | #ifdef CONFIG_DEBUG_FS |
| 404 | |
| 405 | static int at91_clk_show(struct seq_file *s, void *unused) |
| 406 | { |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 407 | u32 scsr, pcsr, uckr = 0, sr; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 408 | struct clk *clk; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 409 | |
| 410 | seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR)); |
| 411 | seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR)); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 412 | seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); |
| 413 | seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); |
| 414 | seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 415 | if (cpu_has_pllb()) |
Nicolas Ferre | ba45ca4 | 2008-04-08 13:59:18 +0100 | [diff] [blame] | 416 | seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 417 | if (cpu_has_utmi()) |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 418 | seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR)); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 419 | seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 420 | if (cpu_has_upll()) |
| 421 | seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB)); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 422 | seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); |
| 423 | |
| 424 | seq_printf(s, "\n"); |
| 425 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 426 | list_for_each_entry(clk, &clocks, node) { |
| 427 | char *state; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 428 | |
| 429 | if (clk->mode == pmc_sys_mode) |
| 430 | state = (scsr & clk->pmc_mask) ? "on" : "off"; |
| 431 | else if (clk->mode == pmc_periph_mode) |
| 432 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 433 | else if (clk->mode == pmc_uckr_mode) |
| 434 | state = (uckr & clk->pmc_mask) ? "on" : "off"; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 435 | else if (clk->pmc_mask) |
| 436 | state = (sr & clk->pmc_mask) ? "on" : "off"; |
| 437 | else if (clk == &clk32k || clk == &main_clk) |
| 438 | state = "on"; |
| 439 | else |
| 440 | state = ""; |
| 441 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 442 | seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n", |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 443 | clk->name, clk->users, state, clk_get_rate(clk), |
| 444 | clk->parent ? clk->parent->name : ""); |
| 445 | } |
| 446 | return 0; |
| 447 | } |
| 448 | |
| 449 | static int at91_clk_open(struct inode *inode, struct file *file) |
| 450 | { |
| 451 | return single_open(file, at91_clk_show, NULL); |
| 452 | } |
| 453 | |
Arjan van de Ven | 5dfe4c9 | 2007-02-12 00:55:31 -0800 | [diff] [blame] | 454 | static const struct file_operations at91_clk_operations = { |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 455 | .open = at91_clk_open, |
| 456 | .read = seq_read, |
| 457 | .llseek = seq_lseek, |
| 458 | .release = single_release, |
| 459 | }; |
| 460 | |
| 461 | static int __init at91_clk_debugfs_init(void) |
| 462 | { |
| 463 | /* /sys/kernel/debug/at91_clk */ |
| 464 | (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations); |
| 465 | |
| 466 | return 0; |
| 467 | } |
| 468 | postcore_initcall(at91_clk_debugfs_init); |
| 469 | |
| 470 | #endif |
| 471 | |
| 472 | /*------------------------------------------------------------------------*/ |
| 473 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 474 | /* Register a new clock */ |
| 475 | int __init clk_register(struct clk *clk) |
| 476 | { |
| 477 | if (clk_is_peripheral(clk)) { |
| 478 | clk->parent = &mck; |
| 479 | clk->mode = pmc_periph_mode; |
| 480 | list_add_tail(&clk->node, &clocks); |
| 481 | } |
Andrew Victor | d481f86 | 2006-12-01 11:27:31 +0100 | [diff] [blame] | 482 | else if (clk_is_sys(clk)) { |
| 483 | clk->parent = &mck; |
| 484 | clk->mode = pmc_sys_mode; |
| 485 | |
| 486 | list_add_tail(&clk->node, &clocks); |
| 487 | } |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 488 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS |
| 489 | else if (clk_is_programmable(clk)) { |
| 490 | clk->mode = pmc_sys_mode; |
| 491 | init_programmable_clock(clk); |
| 492 | list_add_tail(&clk->node, &clocks); |
| 493 | } |
| 494 | #endif |
| 495 | |
| 496 | return 0; |
| 497 | } |
| 498 | |
| 499 | |
| 500 | /*------------------------------------------------------------------------*/ |
| 501 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 502 | static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) |
| 503 | { |
| 504 | unsigned mul, div; |
| 505 | |
| 506 | div = reg & 0xff; |
| 507 | mul = (reg >> 16) & 0x7ff; |
| 508 | if (div && mul) { |
| 509 | freq /= div; |
| 510 | freq *= mul + 1; |
| 511 | } else |
| 512 | freq = 0; |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 513 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 514 | return freq; |
| 515 | } |
| 516 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 517 | static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg) |
| 518 | { |
| 519 | if (pll == &pllb && (reg & AT91_PMC_USB96M)) |
| 520 | return freq / 2; |
| 521 | else |
| 522 | return freq; |
| 523 | } |
| 524 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 525 | static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq) |
| 526 | { |
| 527 | unsigned i, div = 0, mul = 0, diff = 1 << 30; |
| 528 | unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; |
| 529 | |
| 530 | /* PLL output max 240 MHz (or 180 MHz per errata) */ |
| 531 | if (out_freq > 240000000) |
| 532 | goto fail; |
| 533 | |
| 534 | for (i = 1; i < 256; i++) { |
| 535 | int diff1; |
| 536 | unsigned input, mul1; |
| 537 | |
| 538 | /* |
| 539 | * PLL input between 1MHz and 32MHz per spec, but lower |
| 540 | * frequences seem necessary in some cases so allow 100K. |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 541 | * Warning: some newer products need 2MHz min. |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 542 | */ |
| 543 | input = main_freq / i; |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 544 | if (cpu_is_at91sam9g20() && input < 2000000) |
| 545 | continue; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 546 | if (input < 100000) |
| 547 | continue; |
| 548 | if (input > 32000000) |
| 549 | continue; |
| 550 | |
| 551 | mul1 = out_freq / input; |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 552 | if (cpu_is_at91sam9g20() && mul > 63) |
| 553 | continue; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 554 | if (mul1 > 2048) |
| 555 | continue; |
| 556 | if (mul1 < 2) |
| 557 | goto fail; |
| 558 | |
| 559 | diff1 = out_freq - input * mul1; |
| 560 | if (diff1 < 0) |
| 561 | diff1 = -diff1; |
| 562 | if (diff > diff1) { |
| 563 | diff = diff1; |
| 564 | div = i; |
| 565 | mul = mul1; |
| 566 | if (diff == 0) |
| 567 | break; |
| 568 | } |
| 569 | } |
| 570 | if (i == 256 && diff > (out_freq >> 5)) |
| 571 | goto fail; |
| 572 | return ret | ((mul - 1) << 16) | div; |
| 573 | fail: |
| 574 | return 0; |
| 575 | } |
| 576 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 577 | static struct clk *const standard_pmc_clocks[] __initdata = { |
| 578 | /* four primary clocks */ |
| 579 | &clk32k, |
| 580 | &main_clk, |
| 581 | &plla, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 582 | |
| 583 | /* MCK */ |
| 584 | &mck |
| 585 | }; |
| 586 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 587 | /* PLLB generated USB full speed clock init */ |
| 588 | static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) |
| 589 | { |
| 590 | /* |
| 591 | * USB clock init: choose 48 MHz PLLB value, |
| 592 | * disable 48MHz clock during usb peripheral suspend. |
| 593 | * |
| 594 | * REVISIT: assumes MCK doesn't derive from PLLB! |
| 595 | */ |
| 596 | uhpck.parent = &pllb; |
| 597 | |
| 598 | at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; |
| 599 | pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); |
| 600 | if (cpu_is_at91rm9200()) { |
| 601 | uhpck.pmc_mask = AT91RM9200_PMC_UHP; |
| 602 | udpck.pmc_mask = AT91RM9200_PMC_UDP; |
| 603 | at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); |
| 604 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { |
| 605 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; |
| 606 | udpck.pmc_mask = AT91SAM926x_PMC_UDP; |
| 607 | } else if (cpu_is_at91cap9()) { |
| 608 | uhpck.pmc_mask = AT91CAP9_PMC_UHP; |
| 609 | } |
| 610 | at91_sys_write(AT91_CKGR_PLLBR, 0); |
| 611 | |
| 612 | udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); |
| 613 | uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); |
| 614 | } |
| 615 | |
| 616 | /* UPLL generated USB full speed clock init */ |
| 617 | static void __init at91_upll_usbfs_clock_init(unsigned long main_clock) |
| 618 | { |
| 619 | /* |
| 620 | * USB clock init: choose 480 MHz from UPLL, |
| 621 | */ |
| 622 | unsigned int usbr = AT91_PMC_USBS_UPLL; |
| 623 | |
| 624 | /* Setup divider by 10 to reach 48 MHz */ |
| 625 | usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV; |
| 626 | |
| 627 | at91_sys_write(AT91_PMC_USB, usbr); |
| 628 | |
| 629 | /* Now set uhpck values */ |
| 630 | uhpck.parent = &utmi_clk; |
| 631 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; |
| 632 | uhpck.rate_hz = utmi_clk.parent->rate_hz; |
| 633 | uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); |
| 634 | } |
| 635 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 636 | int __init at91_clock_init(unsigned long main_clock) |
| 637 | { |
| 638 | unsigned tmp, freq, mckr; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 639 | int i; |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 640 | |
| 641 | /* |
| 642 | * When the bootloader initialized the main oscillator correctly, |
| 643 | * there's no problem using the cycle counter. But if it didn't, |
| 644 | * or when using oscillator bypass mode, we must be told the speed |
| 645 | * of the main clock. |
| 646 | */ |
| 647 | if (!main_clock) { |
| 648 | do { |
| 649 | tmp = at91_sys_read(AT91_CKGR_MCFR); |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 650 | } while (!(tmp & AT91_PMC_MAINRDY)); |
| 651 | main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 652 | } |
| 653 | main_clk.rate_hz = main_clock; |
| 654 | |
| 655 | /* report if PLLA is more than mildly overclocked */ |
| 656 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 657 | if ((!cpu_has_800M_plla() && plla.rate_hz > 209000000) |
| 658 | || (cpu_has_800M_plla() && plla.rate_hz > 800000000)) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 659 | pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); |
| 660 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 661 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 662 | if (cpu_has_upll() && !cpu_has_pllb()) { |
| 663 | /* setup UTMI clock as the fourth primary clock |
| 664 | * (instead of pllb) */ |
| 665 | utmi_clk.type |= CLK_TYPE_PRIMARY; |
| 666 | utmi_clk.id = 3; |
| 667 | } |
| 668 | |
Andrew Victor | 69b648a | 2006-03-22 20:14:14 +0000 | [diff] [blame] | 669 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 670 | /* |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 671 | * USB HS clock init |
| 672 | */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 673 | if (cpu_has_utmi()) |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 674 | /* |
| 675 | * multiplier is hard-wired to 40 |
| 676 | * (obtain the USB High Speed 480 MHz when input is 12 MHz) |
| 677 | */ |
| 678 | utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 679 | |
| 680 | /* |
| 681 | * USB FS clock init |
| 682 | */ |
| 683 | if (cpu_has_pllb()) |
| 684 | at91_pllb_usbfs_clock_init(main_clock); |
| 685 | if (cpu_has_upll()) |
| 686 | /* assumes that we choose UPLL for USB and not PLLA */ |
| 687 | at91_upll_usbfs_clock_init(main_clock); |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 688 | |
| 689 | /* |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 690 | * MCK and CPU derive from one of those primary clocks. |
| 691 | * For now, assume this parentage won't change. |
| 692 | */ |
| 693 | mckr = at91_sys_read(AT91_PMC_MCKR); |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 694 | mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 695 | freq = mck.parent->rate_hz; |
Andrew Victor | a95c729 | 2007-11-19 11:52:09 +0100 | [diff] [blame] | 696 | freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 697 | if (cpu_is_at91rm9200()) { |
Andrew Victor | a95c729 | 2007-11-19 11:52:09 +0100 | [diff] [blame] | 698 | mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 699 | } else if (cpu_is_at91sam9g20()) { |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 700 | mck.rate_hz = (mckr & AT91_PMC_MDIV) ? |
| 701 | freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ |
| 702 | if (mckr & AT91_PMC_PDIV) |
| 703 | freq /= 2; /* processor clock division */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 704 | } else { |
sedji gaouaou | 6135266 | 2008-07-10 10:15:35 +0100 | [diff] [blame] | 705 | mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 706 | } |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 707 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 708 | /* Register the PMC's standard clocks */ |
| 709 | for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) |
| 710 | list_add_tail(&standard_pmc_clocks[i]->node, &clocks); |
| 711 | |
Nicolas Ferre | 6d0485a | 2009-03-31 17:13:15 +0100 | [diff] [blame] | 712 | if (cpu_has_pllb()) |
| 713 | list_add_tail(&pllb.node, &clocks); |
| 714 | |
| 715 | if (cpu_has_uhp()) |
| 716 | list_add_tail(&uhpck.node, &clocks); |
| 717 | |
| 718 | if (cpu_has_udpfs()) |
| 719 | list_add_tail(&udpck.node, &clocks); |
| 720 | |
| 721 | if (cpu_has_utmi()) |
Stelian Pop | 53d7168 | 2008-04-05 21:14:03 +0100 | [diff] [blame] | 722 | list_add_tail(&utmi_clk.node, &clocks); |
| 723 | |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 724 | /* MCK and CPU clock are "always on" */ |
| 725 | clk_enable(&mck); |
| 726 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 727 | printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", |
| 728 | freq / 1000000, (unsigned) mck.rate_hz / 1000000, |
| 729 | (unsigned) main_clock / 1000000, |
| 730 | ((unsigned) main_clock % 1000000) / 1000); |
| 731 | |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 732 | return 0; |
| 733 | } |
Andrew Victor | 91f8ed8 | 2006-06-19 13:20:23 +0100 | [diff] [blame] | 734 | |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 735 | /* |
| 736 | * Several unused clocks may be active. Turn them off. |
| 737 | */ |
| 738 | static int __init at91_clock_reset(void) |
| 739 | { |
| 740 | unsigned long pcdr = 0; |
| 741 | unsigned long scdr = 0; |
| 742 | struct clk *clk; |
| 743 | |
| 744 | list_for_each_entry(clk, &clocks, node) { |
| 745 | if (clk->users > 0) |
| 746 | continue; |
| 747 | |
| 748 | if (clk->mode == pmc_periph_mode) |
| 749 | pcdr |= clk->pmc_mask; |
| 750 | |
| 751 | if (clk->mode == pmc_sys_mode) |
| 752 | scdr |= clk->pmc_mask; |
| 753 | |
| 754 | pr_debug("Clocks: disable unused %s\n", clk->name); |
| 755 | } |
| 756 | |
| 757 | at91_sys_write(AT91_PMC_PCDR, pcdr); |
| 758 | at91_sys_write(AT91_PMC_SCDR, scdr); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 759 | |
| 760 | return 0; |
| 761 | } |
Andrew Victor | c9b75d1 | 2007-02-08 17:36:34 +0100 | [diff] [blame] | 762 | late_initcall(at91_clock_reset); |