Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/m68knommu/mm/memory.c |
| 3 | * |
| 4 | * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>, |
| 5 | * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com) |
| 6 | * |
| 7 | * Based on: |
| 8 | * |
| 9 | * linux/arch/m68k/mm/memory.c |
| 10 | * |
| 11 | * Copyright (C) 1995 Hamish Macdonald |
| 12 | */ |
| 13 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/mm.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/string.h> |
| 17 | #include <linux/types.h> |
| 18 | #include <linux/slab.h> |
| 19 | |
| 20 | #include <asm/setup.h> |
| 21 | #include <asm/segment.h> |
| 22 | #include <asm/page.h> |
| 23 | #include <asm/pgtable.h> |
| 24 | #include <asm/system.h> |
| 25 | #include <asm/traps.h> |
| 26 | #include <asm/io.h> |
| 27 | |
| 28 | /* |
| 29 | * cache_clear() semantics: Clear any cache entries for the area in question, |
| 30 | * without writing back dirty entries first. This is useful if the data will |
| 31 | * be overwritten anyway, e.g. by DMA to memory. The range is defined by a |
| 32 | * _physical_ address. |
| 33 | */ |
| 34 | |
| 35 | void cache_clear (unsigned long paddr, int len) |
| 36 | { |
| 37 | } |
| 38 | |
| 39 | |
| 40 | /* |
| 41 | * Define cache invalidate functions. The ColdFire 5407 is really |
| 42 | * the only processor that needs to do some work here. Anything |
| 43 | * that has separate data and instruction caches will be a problem. |
| 44 | */ |
| 45 | #ifdef CONFIG_M5407 |
| 46 | |
| 47 | static __inline__ void cache_invalidate_lines(unsigned long paddr, int len) |
| 48 | { |
| 49 | unsigned long sset, eset; |
| 50 | |
| 51 | sset = (paddr & 0x00000ff0); |
| 52 | eset = ((paddr + len) & 0x0000ff0) + 0x10; |
| 53 | |
| 54 | __asm__ __volatile__ ( |
| 55 | "nop\n\t" |
| 56 | "clrl %%d0\n\t" |
| 57 | "1:\n\t" |
| 58 | "movel %0,%%a0\n\t" |
| 59 | "addl %%d0,%%a0\n\t" |
| 60 | "2:\n\t" |
| 61 | ".word 0xf4e8\n\t" |
| 62 | "addl #0x10,%%a0\n\t" |
| 63 | "cmpl %1,%%a0\n\t" |
| 64 | "blt 2b\n\t" |
| 65 | "addql #1,%%d0\n\t" |
| 66 | "cmpil #4,%%d0\n\t" |
| 67 | "bne 1b" |
| 68 | : : "a" (sset), "a" (eset) : "d0", "a0" ); |
| 69 | } |
| 70 | |
| 71 | #else |
| 72 | #define cache_invalidate_lines(a,b) |
| 73 | #endif |
| 74 | |
| 75 | |
| 76 | /* |
| 77 | * cache_push() semantics: Write back any dirty cache data in the given area, |
| 78 | * and invalidate the range in the instruction cache. It needs not (but may) |
| 79 | * invalidate those entries also in the data cache. The range is defined by a |
| 80 | * _physical_ address. |
| 81 | */ |
| 82 | |
| 83 | void cache_push (unsigned long paddr, int len) |
| 84 | { |
| 85 | cache_invalidate_lines(paddr, len); |
| 86 | } |
| 87 | |
| 88 | |
| 89 | /* |
| 90 | * cache_push_v() semantics: Write back any dirty cache data in the given |
| 91 | * area, and invalidate those entries at least in the instruction cache. This |
| 92 | * is intended to be used after data has been written that can be executed as |
| 93 | * code later. The range is defined by a _user_mode_ _virtual_ address (or, |
| 94 | * more exactly, the space is defined by the %sfc/%dfc register.) |
| 95 | */ |
| 96 | |
| 97 | void cache_push_v (unsigned long vaddr, int len) |
| 98 | { |
| 99 | cache_invalidate_lines(vaddr, len); |
| 100 | } |
| 101 | |
| 102 | /* Map some physical address range into the kernel address space. The |
| 103 | * code is copied and adapted from map_chunk(). |
| 104 | */ |
| 105 | |
| 106 | unsigned long kernel_map(unsigned long paddr, unsigned long size, |
| 107 | int nocacheflag, unsigned long *memavailp ) |
| 108 | { |
| 109 | return paddr; |
| 110 | } |
| 111 | |
| 112 | |
| 113 | int is_in_rom(unsigned long addr) |
| 114 | { |
| 115 | extern unsigned long _ramstart, _ramend; |
| 116 | |
| 117 | /* |
| 118 | * What we are really trying to do is determine if addr is |
| 119 | * in an allocated kernel memory region. If not then assume |
| 120 | * we cannot free it or otherwise de-allocate it. Ideally |
| 121 | * we could restrict this to really being in a ROM or flash, |
| 122 | * but that would need to be done on a board by board basis, |
| 123 | * not globally. |
| 124 | */ |
| 125 | if ((addr < _ramstart) || (addr >= _ramend)) |
| 126 | return(1); |
| 127 | |
| 128 | /* Default case, not in ROM */ |
| 129 | return(0); |
| 130 | } |
| 131 | |