Mikael Starvik | 51533b6 | 2005-07-27 11:44:44 -0700 | [diff] [blame] | 1 | #ifndef __eth_defs_h |
| 2 | #define __eth_defs_h |
| 3 | |
| 4 | /* |
| 5 | * This file is autogenerated from |
| 6 | * file: ../../inst/eth/rtl/eth_regs.r |
| 7 | * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp |
| 8 | * last modfied: Mon Apr 11 16:07:03 2005 |
| 9 | * |
| 10 | * by /n/asic/design/tools/rdesc/src/rdes2c --outfile eth_defs.h ../../inst/eth/rtl/eth_regs.r |
| 11 | * id: $Id: eth_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $ |
| 12 | * Any changes here will be lost. |
| 13 | * |
| 14 | * -*- buffer-read-only: t -*- |
| 15 | */ |
| 16 | /* Main access macros */ |
| 17 | #ifndef REG_RD |
| 18 | #define REG_RD( scope, inst, reg ) \ |
| 19 | REG_READ( reg_##scope##_##reg, \ |
| 20 | (inst) + REG_RD_ADDR_##scope##_##reg ) |
| 21 | #endif |
| 22 | |
| 23 | #ifndef REG_WR |
| 24 | #define REG_WR( scope, inst, reg, val ) \ |
| 25 | REG_WRITE( reg_##scope##_##reg, \ |
| 26 | (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) |
| 27 | #endif |
| 28 | |
| 29 | #ifndef REG_RD_VECT |
| 30 | #define REG_RD_VECT( scope, inst, reg, index ) \ |
| 31 | REG_READ( reg_##scope##_##reg, \ |
| 32 | (inst) + REG_RD_ADDR_##scope##_##reg + \ |
| 33 | (index) * STRIDE_##scope##_##reg ) |
| 34 | #endif |
| 35 | |
| 36 | #ifndef REG_WR_VECT |
| 37 | #define REG_WR_VECT( scope, inst, reg, index, val ) \ |
| 38 | REG_WRITE( reg_##scope##_##reg, \ |
| 39 | (inst) + REG_WR_ADDR_##scope##_##reg + \ |
| 40 | (index) * STRIDE_##scope##_##reg, (val) ) |
| 41 | #endif |
| 42 | |
| 43 | #ifndef REG_RD_INT |
| 44 | #define REG_RD_INT( scope, inst, reg ) \ |
| 45 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) |
| 46 | #endif |
| 47 | |
| 48 | #ifndef REG_WR_INT |
| 49 | #define REG_WR_INT( scope, inst, reg, val ) \ |
| 50 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) |
| 51 | #endif |
| 52 | |
| 53 | #ifndef REG_RD_INT_VECT |
| 54 | #define REG_RD_INT_VECT( scope, inst, reg, index ) \ |
| 55 | REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ |
| 56 | (index) * STRIDE_##scope##_##reg ) |
| 57 | #endif |
| 58 | |
| 59 | #ifndef REG_WR_INT_VECT |
| 60 | #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ |
| 61 | REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ |
| 62 | (index) * STRIDE_##scope##_##reg, (val) ) |
| 63 | #endif |
| 64 | |
| 65 | #ifndef REG_TYPE_CONV |
| 66 | #define REG_TYPE_CONV( type, orgtype, val ) \ |
| 67 | ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) |
| 68 | #endif |
| 69 | |
| 70 | #ifndef reg_page_size |
| 71 | #define reg_page_size 8192 |
| 72 | #endif |
| 73 | |
| 74 | #ifndef REG_ADDR |
| 75 | #define REG_ADDR( scope, inst, reg ) \ |
| 76 | ( (inst) + REG_RD_ADDR_##scope##_##reg ) |
| 77 | #endif |
| 78 | |
| 79 | #ifndef REG_ADDR_VECT |
| 80 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ |
| 81 | ( (inst) + REG_RD_ADDR_##scope##_##reg + \ |
| 82 | (index) * STRIDE_##scope##_##reg ) |
| 83 | #endif |
| 84 | |
| 85 | /* C-code for register scope eth */ |
| 86 | |
| 87 | /* Register rw_ma0_lo, scope eth, type rw */ |
| 88 | typedef struct { |
| 89 | unsigned int addr : 32; |
| 90 | } reg_eth_rw_ma0_lo; |
| 91 | #define REG_RD_ADDR_eth_rw_ma0_lo 0 |
| 92 | #define REG_WR_ADDR_eth_rw_ma0_lo 0 |
| 93 | |
| 94 | /* Register rw_ma0_hi, scope eth, type rw */ |
| 95 | typedef struct { |
| 96 | unsigned int addr : 16; |
| 97 | unsigned int dummy1 : 16; |
| 98 | } reg_eth_rw_ma0_hi; |
| 99 | #define REG_RD_ADDR_eth_rw_ma0_hi 4 |
| 100 | #define REG_WR_ADDR_eth_rw_ma0_hi 4 |
| 101 | |
| 102 | /* Register rw_ma1_lo, scope eth, type rw */ |
| 103 | typedef struct { |
| 104 | unsigned int addr : 32; |
| 105 | } reg_eth_rw_ma1_lo; |
| 106 | #define REG_RD_ADDR_eth_rw_ma1_lo 8 |
| 107 | #define REG_WR_ADDR_eth_rw_ma1_lo 8 |
| 108 | |
| 109 | /* Register rw_ma1_hi, scope eth, type rw */ |
| 110 | typedef struct { |
| 111 | unsigned int addr : 16; |
| 112 | unsigned int dummy1 : 16; |
| 113 | } reg_eth_rw_ma1_hi; |
| 114 | #define REG_RD_ADDR_eth_rw_ma1_hi 12 |
| 115 | #define REG_WR_ADDR_eth_rw_ma1_hi 12 |
| 116 | |
| 117 | /* Register rw_ga_lo, scope eth, type rw */ |
| 118 | typedef struct { |
| 119 | unsigned int table : 32; |
| 120 | } reg_eth_rw_ga_lo; |
| 121 | #define REG_RD_ADDR_eth_rw_ga_lo 16 |
| 122 | #define REG_WR_ADDR_eth_rw_ga_lo 16 |
| 123 | |
| 124 | /* Register rw_ga_hi, scope eth, type rw */ |
| 125 | typedef struct { |
| 126 | unsigned int table : 32; |
| 127 | } reg_eth_rw_ga_hi; |
| 128 | #define REG_RD_ADDR_eth_rw_ga_hi 20 |
| 129 | #define REG_WR_ADDR_eth_rw_ga_hi 20 |
| 130 | |
| 131 | /* Register rw_gen_ctrl, scope eth, type rw */ |
| 132 | typedef struct { |
| 133 | unsigned int en : 1; |
| 134 | unsigned int phy : 2; |
| 135 | unsigned int protocol : 1; |
| 136 | unsigned int loopback : 1; |
| 137 | unsigned int flow_ctrl_dis : 1; |
| 138 | unsigned int dummy1 : 26; |
| 139 | } reg_eth_rw_gen_ctrl; |
| 140 | #define REG_RD_ADDR_eth_rw_gen_ctrl 24 |
| 141 | #define REG_WR_ADDR_eth_rw_gen_ctrl 24 |
| 142 | |
| 143 | /* Register rw_rec_ctrl, scope eth, type rw */ |
| 144 | typedef struct { |
| 145 | unsigned int ma0 : 1; |
| 146 | unsigned int ma1 : 1; |
| 147 | unsigned int individual : 1; |
| 148 | unsigned int broadcast : 1; |
| 149 | unsigned int undersize : 1; |
| 150 | unsigned int oversize : 1; |
| 151 | unsigned int bad_crc : 1; |
| 152 | unsigned int duplex : 1; |
| 153 | unsigned int max_size : 1; |
| 154 | unsigned int dummy1 : 23; |
| 155 | } reg_eth_rw_rec_ctrl; |
| 156 | #define REG_RD_ADDR_eth_rw_rec_ctrl 28 |
| 157 | #define REG_WR_ADDR_eth_rw_rec_ctrl 28 |
| 158 | |
| 159 | /* Register rw_tr_ctrl, scope eth, type rw */ |
| 160 | typedef struct { |
| 161 | unsigned int crc : 1; |
| 162 | unsigned int pad : 1; |
| 163 | unsigned int retry : 1; |
| 164 | unsigned int ignore_col : 1; |
| 165 | unsigned int cancel : 1; |
| 166 | unsigned int hsh_delay : 1; |
| 167 | unsigned int ignore_crs : 1; |
| 168 | unsigned int dummy1 : 25; |
| 169 | } reg_eth_rw_tr_ctrl; |
| 170 | #define REG_RD_ADDR_eth_rw_tr_ctrl 32 |
| 171 | #define REG_WR_ADDR_eth_rw_tr_ctrl 32 |
| 172 | |
| 173 | /* Register rw_clr_err, scope eth, type rw */ |
| 174 | typedef struct { |
| 175 | unsigned int clr : 1; |
| 176 | unsigned int dummy1 : 31; |
| 177 | } reg_eth_rw_clr_err; |
| 178 | #define REG_RD_ADDR_eth_rw_clr_err 36 |
| 179 | #define REG_WR_ADDR_eth_rw_clr_err 36 |
| 180 | |
| 181 | /* Register rw_mgm_ctrl, scope eth, type rw */ |
| 182 | typedef struct { |
| 183 | unsigned int mdio : 1; |
| 184 | unsigned int mdoe : 1; |
| 185 | unsigned int mdc : 1; |
| 186 | unsigned int phyclk : 1; |
| 187 | unsigned int txdata : 4; |
| 188 | unsigned int txen : 1; |
| 189 | unsigned int dummy1 : 23; |
| 190 | } reg_eth_rw_mgm_ctrl; |
| 191 | #define REG_RD_ADDR_eth_rw_mgm_ctrl 40 |
| 192 | #define REG_WR_ADDR_eth_rw_mgm_ctrl 40 |
| 193 | |
| 194 | /* Register r_stat, scope eth, type r */ |
| 195 | typedef struct { |
| 196 | unsigned int mdio : 1; |
| 197 | unsigned int exc_col : 1; |
| 198 | unsigned int urun : 1; |
| 199 | unsigned int phyclk : 1; |
| 200 | unsigned int txdata : 4; |
| 201 | unsigned int txen : 1; |
| 202 | unsigned int col : 1; |
| 203 | unsigned int crs : 1; |
| 204 | unsigned int txclk : 1; |
| 205 | unsigned int rxdata : 4; |
| 206 | unsigned int rxer : 1; |
| 207 | unsigned int rxdv : 1; |
| 208 | unsigned int rxclk : 1; |
| 209 | unsigned int dummy1 : 13; |
| 210 | } reg_eth_r_stat; |
| 211 | #define REG_RD_ADDR_eth_r_stat 44 |
| 212 | |
| 213 | /* Register rs_rec_cnt, scope eth, type rs */ |
| 214 | typedef struct { |
| 215 | unsigned int crc_err : 8; |
| 216 | unsigned int align_err : 8; |
| 217 | unsigned int oversize : 8; |
| 218 | unsigned int congestion : 8; |
| 219 | } reg_eth_rs_rec_cnt; |
| 220 | #define REG_RD_ADDR_eth_rs_rec_cnt 48 |
| 221 | |
| 222 | /* Register r_rec_cnt, scope eth, type r */ |
| 223 | typedef struct { |
| 224 | unsigned int crc_err : 8; |
| 225 | unsigned int align_err : 8; |
| 226 | unsigned int oversize : 8; |
| 227 | unsigned int congestion : 8; |
| 228 | } reg_eth_r_rec_cnt; |
| 229 | #define REG_RD_ADDR_eth_r_rec_cnt 52 |
| 230 | |
| 231 | /* Register rs_tr_cnt, scope eth, type rs */ |
| 232 | typedef struct { |
| 233 | unsigned int single_col : 8; |
| 234 | unsigned int mult_col : 8; |
| 235 | unsigned int late_col : 8; |
| 236 | unsigned int deferred : 8; |
| 237 | } reg_eth_rs_tr_cnt; |
| 238 | #define REG_RD_ADDR_eth_rs_tr_cnt 56 |
| 239 | |
| 240 | /* Register r_tr_cnt, scope eth, type r */ |
| 241 | typedef struct { |
| 242 | unsigned int single_col : 8; |
| 243 | unsigned int mult_col : 8; |
| 244 | unsigned int late_col : 8; |
| 245 | unsigned int deferred : 8; |
| 246 | } reg_eth_r_tr_cnt; |
| 247 | #define REG_RD_ADDR_eth_r_tr_cnt 60 |
| 248 | |
| 249 | /* Register rs_phy_cnt, scope eth, type rs */ |
| 250 | typedef struct { |
| 251 | unsigned int carrier_loss : 8; |
| 252 | unsigned int sqe_err : 8; |
| 253 | unsigned int dummy1 : 16; |
| 254 | } reg_eth_rs_phy_cnt; |
| 255 | #define REG_RD_ADDR_eth_rs_phy_cnt 64 |
| 256 | |
| 257 | /* Register r_phy_cnt, scope eth, type r */ |
| 258 | typedef struct { |
| 259 | unsigned int carrier_loss : 8; |
| 260 | unsigned int sqe_err : 8; |
| 261 | unsigned int dummy1 : 16; |
| 262 | } reg_eth_r_phy_cnt; |
| 263 | #define REG_RD_ADDR_eth_r_phy_cnt 68 |
| 264 | |
| 265 | /* Register rw_test_ctrl, scope eth, type rw */ |
| 266 | typedef struct { |
| 267 | unsigned int snmp_inc : 1; |
| 268 | unsigned int snmp : 1; |
| 269 | unsigned int backoff : 1; |
| 270 | unsigned int dummy1 : 29; |
| 271 | } reg_eth_rw_test_ctrl; |
| 272 | #define REG_RD_ADDR_eth_rw_test_ctrl 72 |
| 273 | #define REG_WR_ADDR_eth_rw_test_ctrl 72 |
| 274 | |
| 275 | /* Register rw_intr_mask, scope eth, type rw */ |
| 276 | typedef struct { |
| 277 | unsigned int crc : 1; |
| 278 | unsigned int align : 1; |
| 279 | unsigned int oversize : 1; |
| 280 | unsigned int congestion : 1; |
| 281 | unsigned int single_col : 1; |
| 282 | unsigned int mult_col : 1; |
| 283 | unsigned int late_col : 1; |
| 284 | unsigned int deferred : 1; |
| 285 | unsigned int carrier_loss : 1; |
| 286 | unsigned int sqe_test_err : 1; |
| 287 | unsigned int orun : 1; |
| 288 | unsigned int urun : 1; |
| 289 | unsigned int excessive_col : 1; |
| 290 | unsigned int mdio : 1; |
| 291 | unsigned int dummy1 : 18; |
| 292 | } reg_eth_rw_intr_mask; |
| 293 | #define REG_RD_ADDR_eth_rw_intr_mask 76 |
| 294 | #define REG_WR_ADDR_eth_rw_intr_mask 76 |
| 295 | |
| 296 | /* Register rw_ack_intr, scope eth, type rw */ |
| 297 | typedef struct { |
| 298 | unsigned int crc : 1; |
| 299 | unsigned int align : 1; |
| 300 | unsigned int oversize : 1; |
| 301 | unsigned int congestion : 1; |
| 302 | unsigned int single_col : 1; |
| 303 | unsigned int mult_col : 1; |
| 304 | unsigned int late_col : 1; |
| 305 | unsigned int deferred : 1; |
| 306 | unsigned int carrier_loss : 1; |
| 307 | unsigned int sqe_test_err : 1; |
| 308 | unsigned int orun : 1; |
| 309 | unsigned int urun : 1; |
| 310 | unsigned int excessive_col : 1; |
| 311 | unsigned int mdio : 1; |
| 312 | unsigned int dummy1 : 18; |
| 313 | } reg_eth_rw_ack_intr; |
| 314 | #define REG_RD_ADDR_eth_rw_ack_intr 80 |
| 315 | #define REG_WR_ADDR_eth_rw_ack_intr 80 |
| 316 | |
| 317 | /* Register r_intr, scope eth, type r */ |
| 318 | typedef struct { |
| 319 | unsigned int crc : 1; |
| 320 | unsigned int align : 1; |
| 321 | unsigned int oversize : 1; |
| 322 | unsigned int congestion : 1; |
| 323 | unsigned int single_col : 1; |
| 324 | unsigned int mult_col : 1; |
| 325 | unsigned int late_col : 1; |
| 326 | unsigned int deferred : 1; |
| 327 | unsigned int carrier_loss : 1; |
| 328 | unsigned int sqe_test_err : 1; |
| 329 | unsigned int orun : 1; |
| 330 | unsigned int urun : 1; |
| 331 | unsigned int excessive_col : 1; |
| 332 | unsigned int mdio : 1; |
| 333 | unsigned int dummy1 : 18; |
| 334 | } reg_eth_r_intr; |
| 335 | #define REG_RD_ADDR_eth_r_intr 84 |
| 336 | |
| 337 | /* Register r_masked_intr, scope eth, type r */ |
| 338 | typedef struct { |
| 339 | unsigned int crc : 1; |
| 340 | unsigned int align : 1; |
| 341 | unsigned int oversize : 1; |
| 342 | unsigned int congestion : 1; |
| 343 | unsigned int single_col : 1; |
| 344 | unsigned int mult_col : 1; |
| 345 | unsigned int late_col : 1; |
| 346 | unsigned int deferred : 1; |
| 347 | unsigned int carrier_loss : 1; |
| 348 | unsigned int sqe_test_err : 1; |
| 349 | unsigned int orun : 1; |
| 350 | unsigned int urun : 1; |
| 351 | unsigned int excessive_col : 1; |
| 352 | unsigned int mdio : 1; |
| 353 | unsigned int dummy1 : 18; |
| 354 | } reg_eth_r_masked_intr; |
| 355 | #define REG_RD_ADDR_eth_r_masked_intr 88 |
| 356 | |
| 357 | |
| 358 | /* Constants */ |
| 359 | enum { |
| 360 | regk_eth_discard = 0x00000000, |
| 361 | regk_eth_ether = 0x00000000, |
| 362 | regk_eth_full = 0x00000001, |
| 363 | regk_eth_half = 0x00000000, |
| 364 | regk_eth_hsh = 0x00000001, |
| 365 | regk_eth_mii = 0x00000001, |
| 366 | regk_eth_mii_clk = 0x00000000, |
| 367 | regk_eth_mii_rec = 0x00000002, |
| 368 | regk_eth_no = 0x00000000, |
| 369 | regk_eth_rec = 0x00000001, |
| 370 | regk_eth_rw_ga_hi_default = 0x00000000, |
| 371 | regk_eth_rw_ga_lo_default = 0x00000000, |
| 372 | regk_eth_rw_gen_ctrl_default = 0x00000000, |
| 373 | regk_eth_rw_intr_mask_default = 0x00000000, |
| 374 | regk_eth_rw_ma0_hi_default = 0x00000000, |
| 375 | regk_eth_rw_ma0_lo_default = 0x00000000, |
| 376 | regk_eth_rw_ma1_hi_default = 0x00000000, |
| 377 | regk_eth_rw_ma1_lo_default = 0x00000000, |
| 378 | regk_eth_rw_mgm_ctrl_default = 0x00000000, |
| 379 | regk_eth_rw_test_ctrl_default = 0x00000000, |
| 380 | regk_eth_size1518 = 0x00000000, |
| 381 | regk_eth_size1522 = 0x00000001, |
| 382 | regk_eth_yes = 0x00000001 |
| 383 | }; |
| 384 | #endif /* __eth_defs_h */ |