Uwe Zeisberger | f30c226 | 2006-10-03 23:01:26 +0200 | [diff] [blame] | 1 | /* linux/arch/arm/mach-s3c2410/s3c2410-clock.c |
Ben Dooks | 99c1385 | 2006-06-22 22:18:20 +0100 | [diff] [blame] | 2 | * |
| 3 | * Copyright (c) 2006 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * |
| 6 | * S3C2410,S3C2440,S3C2442 Clock control support |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/module.h> |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/list.h> |
| 27 | #include <linux/errno.h> |
| 28 | #include <linux/err.h> |
| 29 | #include <linux/sysdev.h> |
| 30 | #include <linux/clk.h> |
| 31 | #include <linux/mutex.h> |
| 32 | #include <linux/delay.h> |
| 33 | |
| 34 | #include <asm/hardware.h> |
| 35 | #include <asm/io.h> |
| 36 | |
| 37 | #include <asm/arch/regs-clock.h> |
| 38 | #include <asm/arch/regs-gpio.h> |
| 39 | |
| 40 | #include "clock.h" |
| 41 | #include "cpu.h" |
| 42 | |
| 43 | int s3c2410_clkcon_enable(struct clk *clk, int enable) |
| 44 | { |
| 45 | unsigned int clocks = clk->ctrlbit; |
| 46 | unsigned long clkcon; |
| 47 | |
| 48 | clkcon = __raw_readl(S3C2410_CLKCON); |
| 49 | |
| 50 | if (enable) |
| 51 | clkcon |= clocks; |
| 52 | else |
| 53 | clkcon &= ~clocks; |
| 54 | |
| 55 | /* ensure none of the special function bits set */ |
| 56 | clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER); |
| 57 | |
| 58 | __raw_writel(clkcon, S3C2410_CLKCON); |
| 59 | |
| 60 | return 0; |
| 61 | } |
| 62 | |
| 63 | static int s3c2410_upll_enable(struct clk *clk, int enable) |
| 64 | { |
| 65 | unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); |
| 66 | unsigned long orig = clkslow; |
| 67 | |
| 68 | if (enable) |
| 69 | clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF; |
| 70 | else |
| 71 | clkslow |= S3C2410_CLKSLOW_UCLK_OFF; |
| 72 | |
| 73 | __raw_writel(clkslow, S3C2410_CLKSLOW); |
| 74 | |
| 75 | /* if we started the UPLL, then allow to settle */ |
| 76 | |
| 77 | if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF)) |
| 78 | udelay(200); |
| 79 | |
| 80 | return 0; |
| 81 | } |
| 82 | |
| 83 | /* standard clock definitions */ |
| 84 | |
| 85 | static struct clk init_clocks_disable[] = { |
| 86 | { |
| 87 | .name = "nand", |
| 88 | .id = -1, |
| 89 | .parent = &clk_h, |
| 90 | .enable = s3c2410_clkcon_enable, |
| 91 | .ctrlbit = S3C2410_CLKCON_NAND, |
| 92 | }, { |
| 93 | .name = "sdi", |
| 94 | .id = -1, |
| 95 | .parent = &clk_p, |
| 96 | .enable = s3c2410_clkcon_enable, |
| 97 | .ctrlbit = S3C2410_CLKCON_SDI, |
| 98 | }, { |
| 99 | .name = "adc", |
| 100 | .id = -1, |
| 101 | .parent = &clk_p, |
| 102 | .enable = s3c2410_clkcon_enable, |
| 103 | .ctrlbit = S3C2410_CLKCON_ADC, |
| 104 | }, { |
| 105 | .name = "i2c", |
| 106 | .id = -1, |
| 107 | .parent = &clk_p, |
| 108 | .enable = s3c2410_clkcon_enable, |
| 109 | .ctrlbit = S3C2410_CLKCON_IIC, |
| 110 | }, { |
| 111 | .name = "iis", |
| 112 | .id = -1, |
| 113 | .parent = &clk_p, |
| 114 | .enable = s3c2410_clkcon_enable, |
| 115 | .ctrlbit = S3C2410_CLKCON_IIS, |
| 116 | }, { |
| 117 | .name = "spi", |
| 118 | .id = -1, |
| 119 | .parent = &clk_p, |
| 120 | .enable = s3c2410_clkcon_enable, |
| 121 | .ctrlbit = S3C2410_CLKCON_SPI, |
| 122 | } |
| 123 | }; |
| 124 | |
| 125 | static struct clk init_clocks[] = { |
| 126 | { |
| 127 | .name = "lcd", |
| 128 | .id = -1, |
| 129 | .parent = &clk_h, |
| 130 | .enable = s3c2410_clkcon_enable, |
| 131 | .ctrlbit = S3C2410_CLKCON_LCDC, |
| 132 | }, { |
| 133 | .name = "gpio", |
| 134 | .id = -1, |
| 135 | .parent = &clk_p, |
| 136 | .enable = s3c2410_clkcon_enable, |
| 137 | .ctrlbit = S3C2410_CLKCON_GPIO, |
| 138 | }, { |
| 139 | .name = "usb-host", |
| 140 | .id = -1, |
| 141 | .parent = &clk_h, |
| 142 | .enable = s3c2410_clkcon_enable, |
| 143 | .ctrlbit = S3C2410_CLKCON_USBH, |
| 144 | }, { |
| 145 | .name = "usb-device", |
| 146 | .id = -1, |
| 147 | .parent = &clk_h, |
| 148 | .enable = s3c2410_clkcon_enable, |
| 149 | .ctrlbit = S3C2410_CLKCON_USBD, |
| 150 | }, { |
| 151 | .name = "timers", |
| 152 | .id = -1, |
| 153 | .parent = &clk_p, |
| 154 | .enable = s3c2410_clkcon_enable, |
| 155 | .ctrlbit = S3C2410_CLKCON_PWMT, |
| 156 | }, { |
| 157 | .name = "uart", |
| 158 | .id = 0, |
| 159 | .parent = &clk_p, |
| 160 | .enable = s3c2410_clkcon_enable, |
| 161 | .ctrlbit = S3C2410_CLKCON_UART0, |
| 162 | }, { |
| 163 | .name = "uart", |
| 164 | .id = 1, |
| 165 | .parent = &clk_p, |
| 166 | .enable = s3c2410_clkcon_enable, |
| 167 | .ctrlbit = S3C2410_CLKCON_UART1, |
| 168 | }, { |
| 169 | .name = "uart", |
| 170 | .id = 2, |
| 171 | .parent = &clk_p, |
| 172 | .enable = s3c2410_clkcon_enable, |
| 173 | .ctrlbit = S3C2410_CLKCON_UART2, |
| 174 | }, { |
| 175 | .name = "rtc", |
| 176 | .id = -1, |
| 177 | .parent = &clk_p, |
| 178 | .enable = s3c2410_clkcon_enable, |
| 179 | .ctrlbit = S3C2410_CLKCON_RTC, |
| 180 | }, { |
| 181 | .name = "watchdog", |
| 182 | .id = -1, |
| 183 | .parent = &clk_p, |
| 184 | .ctrlbit = 0, |
Ben Dooks | 22346ae | 2006-06-24 21:21:36 +0100 | [diff] [blame] | 185 | }, { |
| 186 | .name = "usb-bus-host", |
| 187 | .id = -1, |
| 188 | .parent = &clk_usb_bus, |
| 189 | }, { |
| 190 | .name = "usb-bus-gadget", |
| 191 | .id = -1, |
| 192 | .parent = &clk_usb_bus, |
| 193 | }, |
Ben Dooks | 99c1385 | 2006-06-22 22:18:20 +0100 | [diff] [blame] | 194 | }; |
| 195 | |
| 196 | /* s3c2410_baseclk_add() |
| 197 | * |
| 198 | * Add all the clocks used by the s3c2410 or compatible CPUs |
| 199 | * such as the S3C2440 and S3C2442. |
| 200 | * |
| 201 | * We cannot use a system device as we are needed before any |
| 202 | * of the init-calls that initialise the devices are actually |
| 203 | * done. |
| 204 | */ |
| 205 | |
| 206 | int __init s3c2410_baseclk_add(void) |
| 207 | { |
| 208 | unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW); |
| 209 | unsigned long clkcon = __raw_readl(S3C2410_CLKCON); |
| 210 | struct clk *clkp; |
| 211 | struct clk *xtal; |
| 212 | int ret; |
| 213 | int ptr; |
| 214 | |
| 215 | clk_upll.enable = s3c2410_upll_enable; |
| 216 | |
| 217 | if (s3c24xx_register_clock(&clk_usb_bus) < 0) |
| 218 | printk(KERN_ERR "failed to register usb bus clock\n"); |
| 219 | |
| 220 | /* register clocks from clock array */ |
| 221 | |
| 222 | clkp = init_clocks; |
| 223 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { |
| 224 | /* ensure that we note the clock state */ |
| 225 | |
| 226 | clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0; |
| 227 | |
| 228 | ret = s3c24xx_register_clock(clkp); |
| 229 | if (ret < 0) { |
| 230 | printk(KERN_ERR "Failed to register clock %s (%d)\n", |
| 231 | clkp->name, ret); |
| 232 | } |
| 233 | } |
| 234 | |
| 235 | /* We must be careful disabling the clocks we are not intending to |
| 236 | * be using at boot time, as subsytems such as the LCD which do |
| 237 | * their own DMA requests to the bus can cause the system to lockup |
| 238 | * if they where in the middle of requesting bus access. |
| 239 | * |
| 240 | * Disabling the LCD clock if the LCD is active is very dangerous, |
| 241 | * and therefore the bootloader should be careful to not enable |
| 242 | * the LCD clock if it is not needed. |
| 243 | */ |
| 244 | |
| 245 | /* install (and disable) the clocks we do not need immediately */ |
| 246 | |
| 247 | clkp = init_clocks_disable; |
| 248 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { |
| 249 | |
| 250 | ret = s3c24xx_register_clock(clkp); |
| 251 | if (ret < 0) { |
| 252 | printk(KERN_ERR "Failed to register clock %s (%d)\n", |
| 253 | clkp->name, ret); |
| 254 | } |
| 255 | |
| 256 | s3c2410_clkcon_enable(clkp, 0); |
| 257 | } |
| 258 | |
| 259 | /* show the clock-slow value */ |
| 260 | |
| 261 | xtal = clk_get(NULL, "xtal"); |
| 262 | |
| 263 | printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n", |
| 264 | print_mhz(clk_get_rate(xtal) / |
| 265 | ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))), |
| 266 | (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast", |
| 267 | (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on", |
| 268 | (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on"); |
| 269 | |
| 270 | return 0; |
| 271 | } |