Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Intel specific MCE features. |
| 3 | * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca> |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 4 | * Copyright (C) 2008, 2009 Intel Corporation |
| 5 | * Author: Andi Kleen |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | */ |
| 7 | |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 8 | #include <linux/gfp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | #include <linux/interrupt.h> |
| 10 | #include <linux/percpu.h> |
Alexey Dobriyan | d43c36d | 2009-10-07 17:09:06 +0400 | [diff] [blame] | 11 | #include <linux/sched.h> |
H. Peter Anvin | 1bf7b31 | 2009-06-17 08:31:15 -0700 | [diff] [blame] | 12 | #include <asm/apic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | #include <asm/processor.h> |
| 14 | #include <asm/msr.h> |
| 15 | #include <asm/mce.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | |
Chen Gong | 55babd8 | 2012-08-09 11:44:51 -0700 | [diff] [blame] | 17 | #include "mce-internal.h" |
| 18 | |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 19 | /* |
| 20 | * Support for Intel Correct Machine Check Interrupts. This allows |
| 21 | * the CPU to raise an interrupt when a corrected machine check happened. |
| 22 | * Normally we pick those up using a regular polling timer. |
| 23 | * Also supports reliable discovery of shared banks. |
| 24 | */ |
| 25 | |
Naveen N. Rao | 0644414 | 2013-06-25 23:58:59 +0530 | [diff] [blame] | 26 | /* |
| 27 | * CMCI can be delivered to multiple cpus that share a machine check bank |
| 28 | * so we need to designate a single cpu to process errors logged in each bank |
| 29 | * in the interrupt handler (otherwise we would have many races and potential |
| 30 | * double reporting of the same error). |
| 31 | * Note that this can change when a cpu is offlined or brought online since |
| 32 | * some MCA banks are shared across cpus. When a cpu is offlined, cmci_clear() |
| 33 | * disables CMCI on all banks owned by the cpu and clears this bitfield. At |
| 34 | * this point, cmci_rediscover() kicks in and a different cpu may end up |
| 35 | * taking ownership of some of the shared MCA banks that were previously |
| 36 | * owned by the offlined cpu. |
| 37 | */ |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 38 | static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned); |
| 39 | |
| 40 | /* |
| 41 | * cmci_discover_lock protects against parallel discovery attempts |
| 42 | * which could race against each other. |
| 43 | */ |
Thomas Gleixner | 59d958d | 2010-07-15 14:28:02 +0200 | [diff] [blame] | 44 | static DEFINE_RAW_SPINLOCK(cmci_discover_lock); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 45 | |
Chen Gong | 55babd8 | 2012-08-09 11:44:51 -0700 | [diff] [blame] | 46 | #define CMCI_THRESHOLD 1 |
| 47 | #define CMCI_POLL_INTERVAL (30 * HZ) |
| 48 | #define CMCI_STORM_INTERVAL (1 * HZ) |
| 49 | #define CMCI_STORM_THRESHOLD 15 |
| 50 | |
| 51 | static DEFINE_PER_CPU(unsigned long, cmci_time_stamp); |
| 52 | static DEFINE_PER_CPU(unsigned int, cmci_storm_cnt); |
| 53 | static DEFINE_PER_CPU(unsigned int, cmci_storm_state); |
| 54 | |
| 55 | enum { |
| 56 | CMCI_STORM_NONE, |
| 57 | CMCI_STORM_ACTIVE, |
| 58 | CMCI_STORM_SUBSIDED, |
| 59 | }; |
| 60 | |
| 61 | static atomic_t cmci_storm_on_cpus; |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 62 | |
H. Peter Anvin | df20e2e | 2009-02-24 13:19:02 -0800 | [diff] [blame] | 63 | static int cmci_supported(int *banks) |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 64 | { |
| 65 | u64 cap; |
| 66 | |
Borislav Petkov | 7af19e4 | 2012-10-15 20:25:17 +0200 | [diff] [blame] | 67 | if (mca_cfg.cmci_disabled || mca_cfg.ignore_ce) |
Hidetoshi Seto | 62fdac5 | 2009-06-11 16:06:07 +0900 | [diff] [blame] | 68 | return 0; |
| 69 | |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 70 | /* |
| 71 | * Vendor check is not strictly needed, but the initial |
| 72 | * initialization is vendor keyed and this |
| 73 | * makes sure none of the backdoors are entered otherwise. |
| 74 | */ |
| 75 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) |
| 76 | return 0; |
| 77 | if (!cpu_has_apic || lapic_get_maxlvt() < 6) |
| 78 | return 0; |
| 79 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
| 80 | *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff); |
| 81 | return !!(cap & MCG_CMCI_P); |
| 82 | } |
| 83 | |
Chen Gong | 55babd8 | 2012-08-09 11:44:51 -0700 | [diff] [blame] | 84 | void mce_intel_cmci_poll(void) |
| 85 | { |
| 86 | if (__this_cpu_read(cmci_storm_state) == CMCI_STORM_NONE) |
| 87 | return; |
| 88 | machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); |
| 89 | } |
| 90 | |
| 91 | void mce_intel_hcpu_update(unsigned long cpu) |
| 92 | { |
| 93 | if (per_cpu(cmci_storm_state, cpu) == CMCI_STORM_ACTIVE) |
| 94 | atomic_dec(&cmci_storm_on_cpus); |
| 95 | |
| 96 | per_cpu(cmci_storm_state, cpu) = CMCI_STORM_NONE; |
| 97 | } |
| 98 | |
| 99 | unsigned long mce_intel_adjust_timer(unsigned long interval) |
| 100 | { |
| 101 | int r; |
| 102 | |
| 103 | if (interval < CMCI_POLL_INTERVAL) |
| 104 | return interval; |
| 105 | |
| 106 | switch (__this_cpu_read(cmci_storm_state)) { |
| 107 | case CMCI_STORM_ACTIVE: |
| 108 | /* |
| 109 | * We switch back to interrupt mode once the poll timer has |
| 110 | * silenced itself. That means no events recorded and the |
| 111 | * timer interval is back to our poll interval. |
| 112 | */ |
| 113 | __this_cpu_write(cmci_storm_state, CMCI_STORM_SUBSIDED); |
| 114 | r = atomic_sub_return(1, &cmci_storm_on_cpus); |
| 115 | if (r == 0) |
| 116 | pr_notice("CMCI storm subsided: switching to interrupt mode\n"); |
| 117 | /* FALLTHROUGH */ |
| 118 | |
| 119 | case CMCI_STORM_SUBSIDED: |
| 120 | /* |
| 121 | * We wait for all cpus to go back to SUBSIDED |
| 122 | * state. When that happens we switch back to |
| 123 | * interrupt mode. |
| 124 | */ |
| 125 | if (!atomic_read(&cmci_storm_on_cpus)) { |
| 126 | __this_cpu_write(cmci_storm_state, CMCI_STORM_NONE); |
| 127 | cmci_reenable(); |
| 128 | cmci_recheck(); |
| 129 | } |
| 130 | return CMCI_POLL_INTERVAL; |
| 131 | default: |
| 132 | /* |
| 133 | * We have shiny weather. Let the poll do whatever it |
| 134 | * thinks. |
| 135 | */ |
| 136 | return interval; |
| 137 | } |
| 138 | } |
| 139 | |
| 140 | static bool cmci_storm_detect(void) |
| 141 | { |
| 142 | unsigned int cnt = __this_cpu_read(cmci_storm_cnt); |
| 143 | unsigned long ts = __this_cpu_read(cmci_time_stamp); |
| 144 | unsigned long now = jiffies; |
| 145 | int r; |
| 146 | |
| 147 | if (__this_cpu_read(cmci_storm_state) != CMCI_STORM_NONE) |
| 148 | return true; |
| 149 | |
| 150 | if (time_before_eq(now, ts + CMCI_STORM_INTERVAL)) { |
| 151 | cnt++; |
| 152 | } else { |
| 153 | cnt = 1; |
| 154 | __this_cpu_write(cmci_time_stamp, now); |
| 155 | } |
| 156 | __this_cpu_write(cmci_storm_cnt, cnt); |
| 157 | |
| 158 | if (cnt <= CMCI_STORM_THRESHOLD) |
| 159 | return false; |
| 160 | |
| 161 | cmci_clear(); |
| 162 | __this_cpu_write(cmci_storm_state, CMCI_STORM_ACTIVE); |
| 163 | r = atomic_add_return(1, &cmci_storm_on_cpus); |
| 164 | mce_timer_kick(CMCI_POLL_INTERVAL); |
| 165 | |
| 166 | if (r == 1) |
| 167 | pr_notice("CMCI storm detected: switching to poll mode\n"); |
| 168 | return true; |
| 169 | } |
| 170 | |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 171 | /* |
| 172 | * The interrupt handler. This is called on every event. |
| 173 | * Just call the poller directly to log any events. |
| 174 | * This could in theory increase the threshold under high load, |
| 175 | * but doesn't for now. |
| 176 | */ |
| 177 | static void intel_threshold_interrupt(void) |
| 178 | { |
Chen Gong | 55babd8 | 2012-08-09 11:44:51 -0700 | [diff] [blame] | 179 | if (cmci_storm_detect()) |
| 180 | return; |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 181 | machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); |
Andi Kleen | 9ff36ee | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 182 | mce_notify_irq(); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 183 | } |
| 184 | |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 185 | /* |
| 186 | * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks |
| 187 | * on this CPU. Use the algorithm recommended in the SDM to discover shared |
| 188 | * banks. |
| 189 | */ |
Tony Luck | 4670a30 | 2012-08-09 10:59:21 -0700 | [diff] [blame] | 190 | static void cmci_discover(int banks) |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 191 | { |
| 192 | unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned); |
Hidetoshi Seto | e529992 | 2009-05-08 17:28:40 +0900 | [diff] [blame] | 193 | unsigned long flags; |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 194 | int i; |
Naveen N. Rao | 450cc20 | 2012-09-27 10:08:00 -0700 | [diff] [blame] | 195 | int bios_wrong_thresh = 0; |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 196 | |
Thomas Gleixner | 59d958d | 2010-07-15 14:28:02 +0200 | [diff] [blame] | 197 | raw_spin_lock_irqsave(&cmci_discover_lock, flags); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 198 | for (i = 0; i < banks; i++) { |
| 199 | u64 val; |
Naveen N. Rao | 450cc20 | 2012-09-27 10:08:00 -0700 | [diff] [blame] | 200 | int bios_zero_thresh = 0; |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 201 | |
| 202 | if (test_bit(i, owned)) |
| 203 | continue; |
| 204 | |
Naveen N. Rao | c3d1fb5 | 2013-07-01 21:08:47 +0530 | [diff] [blame] | 205 | /* Skip banks in firmware first mode */ |
| 206 | if (test_bit(i, mce_banks_ce_disabled)) |
| 207 | continue; |
| 208 | |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 209 | rdmsrl(MSR_IA32_MCx_CTL2(i), val); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 210 | |
| 211 | /* Already owned by someone else? */ |
Huang Ying | 1f9a0bd | 2010-06-08 14:09:08 +0800 | [diff] [blame] | 212 | if (val & MCI_CTL2_CMCI_EN) { |
Tony Luck | 4670a30 | 2012-08-09 10:59:21 -0700 | [diff] [blame] | 213 | clear_bit(i, owned); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 214 | __clear_bit(i, __get_cpu_var(mce_poll_banks)); |
| 215 | continue; |
| 216 | } |
| 217 | |
Borislav Petkov | 1462594 | 2012-10-17 12:05:33 +0200 | [diff] [blame] | 218 | if (!mca_cfg.bios_cmci_threshold) { |
Naveen N. Rao | 450cc20 | 2012-09-27 10:08:00 -0700 | [diff] [blame] | 219 | val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK; |
| 220 | val |= CMCI_THRESHOLD; |
| 221 | } else if (!(val & MCI_CTL2_CMCI_THRESHOLD_MASK)) { |
| 222 | /* |
| 223 | * If bios_cmci_threshold boot option was specified |
| 224 | * but the threshold is zero, we'll try to initialize |
| 225 | * it to 1. |
| 226 | */ |
| 227 | bios_zero_thresh = 1; |
| 228 | val |= CMCI_THRESHOLD; |
| 229 | } |
| 230 | |
| 231 | val |= MCI_CTL2_CMCI_EN; |
Andi Kleen | a2d32bc | 2009-07-09 00:31:44 +0200 | [diff] [blame] | 232 | wrmsrl(MSR_IA32_MCx_CTL2(i), val); |
| 233 | rdmsrl(MSR_IA32_MCx_CTL2(i), val); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 234 | |
| 235 | /* Did the enable bit stick? -- the bank supports CMCI */ |
Huang Ying | 1f9a0bd | 2010-06-08 14:09:08 +0800 | [diff] [blame] | 236 | if (val & MCI_CTL2_CMCI_EN) { |
Tony Luck | 4670a30 | 2012-08-09 10:59:21 -0700 | [diff] [blame] | 237 | set_bit(i, owned); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 238 | __clear_bit(i, __get_cpu_var(mce_poll_banks)); |
Naveen N. Rao | 450cc20 | 2012-09-27 10:08:00 -0700 | [diff] [blame] | 239 | /* |
| 240 | * We are able to set thresholds for some banks that |
| 241 | * had a threshold of 0. This means the BIOS has not |
| 242 | * set the thresholds properly or does not work with |
| 243 | * this boot option. Note down now and report later. |
| 244 | */ |
Borislav Petkov | 1462594 | 2012-10-17 12:05:33 +0200 | [diff] [blame] | 245 | if (mca_cfg.bios_cmci_threshold && bios_zero_thresh && |
Naveen N. Rao | 450cc20 | 2012-09-27 10:08:00 -0700 | [diff] [blame] | 246 | (val & MCI_CTL2_CMCI_THRESHOLD_MASK)) |
| 247 | bios_wrong_thresh = 1; |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 248 | } else { |
| 249 | WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks))); |
| 250 | } |
| 251 | } |
Thomas Gleixner | 59d958d | 2010-07-15 14:28:02 +0200 | [diff] [blame] | 252 | raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); |
Borislav Petkov | 1462594 | 2012-10-17 12:05:33 +0200 | [diff] [blame] | 253 | if (mca_cfg.bios_cmci_threshold && bios_wrong_thresh) { |
Naveen N. Rao | 450cc20 | 2012-09-27 10:08:00 -0700 | [diff] [blame] | 254 | pr_info_once( |
| 255 | "bios_cmci_threshold: Some banks do not have valid thresholds set\n"); |
| 256 | pr_info_once( |
| 257 | "bios_cmci_threshold: Make sure your BIOS supports this boot option\n"); |
| 258 | } |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 259 | } |
| 260 | |
| 261 | /* |
| 262 | * Just in case we missed an event during initialization check |
| 263 | * all the CMCI owned banks. |
| 264 | */ |
H. Peter Anvin | df20e2e | 2009-02-24 13:19:02 -0800 | [diff] [blame] | 265 | void cmci_recheck(void) |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 266 | { |
| 267 | unsigned long flags; |
| 268 | int banks; |
| 269 | |
Tejun Heo | 7b543a5 | 2010-12-18 16:30:05 +0100 | [diff] [blame] | 270 | if (!mce_available(__this_cpu_ptr(&cpu_info)) || !cmci_supported(&banks)) |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 271 | return; |
| 272 | local_irq_save(flags); |
| 273 | machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); |
| 274 | local_irq_restore(flags); |
| 275 | } |
| 276 | |
Naveen N. Rao | c3d1fb5 | 2013-07-01 21:08:47 +0530 | [diff] [blame] | 277 | /* Caller must hold the lock on cmci_discover_lock */ |
| 278 | static void __cmci_disable_bank(int bank) |
| 279 | { |
| 280 | u64 val; |
| 281 | |
| 282 | if (!test_bit(bank, __get_cpu_var(mce_banks_owned))) |
| 283 | return; |
| 284 | rdmsrl(MSR_IA32_MCx_CTL2(bank), val); |
| 285 | val &= ~MCI_CTL2_CMCI_EN; |
| 286 | wrmsrl(MSR_IA32_MCx_CTL2(bank), val); |
| 287 | __clear_bit(bank, __get_cpu_var(mce_banks_owned)); |
| 288 | } |
| 289 | |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 290 | /* |
| 291 | * Disable CMCI on this CPU for all banks it owns when it goes down. |
| 292 | * This allows other CPUs to claim the banks on rediscovery. |
| 293 | */ |
H. Peter Anvin | df20e2e | 2009-02-24 13:19:02 -0800 | [diff] [blame] | 294 | void cmci_clear(void) |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 295 | { |
Hidetoshi Seto | e529992 | 2009-05-08 17:28:40 +0900 | [diff] [blame] | 296 | unsigned long flags; |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 297 | int i; |
| 298 | int banks; |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 299 | |
| 300 | if (!cmci_supported(&banks)) |
| 301 | return; |
Thomas Gleixner | 59d958d | 2010-07-15 14:28:02 +0200 | [diff] [blame] | 302 | raw_spin_lock_irqsave(&cmci_discover_lock, flags); |
Naveen N. Rao | c3d1fb5 | 2013-07-01 21:08:47 +0530 | [diff] [blame] | 303 | for (i = 0; i < banks; i++) |
| 304 | __cmci_disable_bank(i); |
Thomas Gleixner | 59d958d | 2010-07-15 14:28:02 +0200 | [diff] [blame] | 305 | raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 306 | } |
| 307 | |
Srivatsa S. Bhat | 7a0c819 | 2013-03-20 15:31:29 +0530 | [diff] [blame] | 308 | static void cmci_rediscover_work_func(void *arg) |
Tang Chen | 85b9763 | 2012-10-29 11:01:50 +0800 | [diff] [blame] | 309 | { |
| 310 | int banks; |
| 311 | |
| 312 | /* Recheck banks in case CPUs don't all have the same */ |
| 313 | if (cmci_supported(&banks)) |
| 314 | cmci_discover(banks); |
Tang Chen | 85b9763 | 2012-10-29 11:01:50 +0800 | [diff] [blame] | 315 | } |
| 316 | |
Srivatsa S. Bhat | 7a0c819 | 2013-03-20 15:31:29 +0530 | [diff] [blame] | 317 | /* After a CPU went down cycle through all the others and rediscover */ |
| 318 | void cmci_rediscover(void) |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 319 | { |
Srivatsa S. Bhat | 7a0c819 | 2013-03-20 15:31:29 +0530 | [diff] [blame] | 320 | int banks; |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 321 | |
| 322 | if (!cmci_supported(&banks)) |
| 323 | return; |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 324 | |
Srivatsa S. Bhat | 7a0c819 | 2013-03-20 15:31:29 +0530 | [diff] [blame] | 325 | on_each_cpu(cmci_rediscover_work_func, NULL, 1); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 326 | } |
| 327 | |
| 328 | /* |
| 329 | * Reenable CMCI on this CPU in case a CPU down failed. |
| 330 | */ |
| 331 | void cmci_reenable(void) |
| 332 | { |
| 333 | int banks; |
| 334 | if (cmci_supported(&banks)) |
Tony Luck | 4670a30 | 2012-08-09 10:59:21 -0700 | [diff] [blame] | 335 | cmci_discover(banks); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 336 | } |
| 337 | |
Naveen N. Rao | c3d1fb5 | 2013-07-01 21:08:47 +0530 | [diff] [blame] | 338 | void cmci_disable_bank(int bank) |
| 339 | { |
| 340 | int banks; |
| 341 | unsigned long flags; |
| 342 | |
| 343 | if (!cmci_supported(&banks)) |
| 344 | return; |
| 345 | |
| 346 | raw_spin_lock_irqsave(&cmci_discover_lock, flags); |
| 347 | __cmci_disable_bank(bank); |
| 348 | raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); |
| 349 | } |
| 350 | |
Hidetoshi Seto | 514ec49 | 2009-03-16 17:07:33 +0900 | [diff] [blame] | 351 | static void intel_init_cmci(void) |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 352 | { |
| 353 | int banks; |
| 354 | |
| 355 | if (!cmci_supported(&banks)) |
| 356 | return; |
| 357 | |
| 358 | mce_threshold_vector = intel_threshold_interrupt; |
Tony Luck | 4670a30 | 2012-08-09 10:59:21 -0700 | [diff] [blame] | 359 | cmci_discover(banks); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 360 | /* |
| 361 | * For CPU #0 this runs with still disabled APIC, but that's |
| 362 | * ok because only the vector is set up. We still do another |
| 363 | * check for the banks later for CPU #0 just to make sure |
| 364 | * to not miss any events. |
| 365 | */ |
| 366 | apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED); |
| 367 | cmci_recheck(); |
| 368 | } |
| 369 | |
H. Peter Anvin | cc3ca22 | 2009-02-20 23:35:51 -0800 | [diff] [blame] | 370 | void mce_intel_feature_init(struct cpuinfo_x86 *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 371 | { |
| 372 | intel_init_thermal(c); |
Andi Kleen | 88ccbed | 2009-02-12 13:49:36 +0100 | [diff] [blame] | 373 | intel_init_cmci(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 374 | } |