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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Tony Lindgren7c38cf02005-09-08 23:07:38 +01002 * linux/arch/arm/mach-omap1/irq.c
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * Interrupt handler for all OMAP boards
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
Jan Engelhardt96de0e22007-10-19 23:21:04 +02008 * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * Completely re-written to support various OMAP chips with bank specific
11 * interrupt handlers.
12 *
13 * Some snippets of the code taken from the older OMAP interrupt handler
14 * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
15 *
16 * GPIO interrupt handler moved to gpio.c by Juha Yrjola
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
22 *
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
37 */
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <linux/init.h>
40#include <linux/module.h>
41#include <linux/sched.h>
42#include <linux/interrupt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070043
Russell Kingbe509722008-08-04 10:41:28 +010044#include <asm/arch/hardware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <asm/irq.h>
46#include <asm/mach/irq.h>
47#include <asm/arch/gpio.h>
Tony Lindgren3179a012005-11-10 14:26:48 +000048#include <asm/arch/cpu.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070049
50#include <asm/io.h>
51
52#define IRQ_BANK(irq) ((irq) >> 5)
53#define IRQ_BIT(irq) ((irq) & 0x1f)
54
55struct omap_irq_bank {
56 unsigned long base_reg;
57 unsigned long trigger_map;
Tony Lindgren3b59b6b2005-07-10 19:58:09 +010058 unsigned long wake_enable;
Linus Torvalds1da177e2005-04-16 15:20:36 -070059};
60
Tony Lindgren120db2c2006-04-02 17:46:27 +010061static unsigned int irq_bank_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -070062static struct omap_irq_bank *irq_banks;
63
64static inline unsigned int irq_bank_readl(int bank, int offset)
65{
66 return omap_readl(irq_banks[bank].base_reg + offset);
67}
68
69static inline void irq_bank_writel(unsigned long value, int bank, int offset)
70{
71 omap_writel(value, irq_banks[bank].base_reg + offset);
72}
73
74static void omap_ack_irq(unsigned int irq)
75{
76 if (irq > 31)
77 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
78
79 omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
80}
81
82static void omap_mask_irq(unsigned int irq)
83{
84 int bank = IRQ_BANK(irq);
85 u32 l;
86
87 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
88 l |= 1 << IRQ_BIT(irq);
89 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
90}
91
92static void omap_unmask_irq(unsigned int irq)
93{
94 int bank = IRQ_BANK(irq);
95 u32 l;
96
97 l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
98 l &= ~(1 << IRQ_BIT(irq));
99 omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
100}
101
102static void omap_mask_ack_irq(unsigned int irq)
103{
104 omap_mask_irq(irq);
105 omap_ack_irq(irq);
106}
107
Tony Lindgren3b59b6b2005-07-10 19:58:09 +0100108static int omap_wake_irq(unsigned int irq, unsigned int enable)
109{
110 int bank = IRQ_BANK(irq);
111
112 if (enable)
113 irq_banks[bank].wake_enable |= IRQ_BIT(irq);
114 else
115 irq_banks[bank].wake_enable &= ~IRQ_BIT(irq);
116
117 return 0;
118}
119
120
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121/*
122 * Allows tuning the IRQ type and priority
123 *
124 * NOTE: There is currently no OMAP fiq handler for Linux. Read the
125 * mailing list threads on FIQ handlers if you are planning to
126 * add a FIQ handler for OMAP.
127 */
128static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
129{
130 signed int bank;
131 unsigned long val, offset;
132
133 bank = IRQ_BANK(irq);
134 /* FIQ is only available on bank 0 interrupts */
135 fiq = bank ? 0 : (fiq & 0x1);
136 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
137 offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
138 irq_bank_writel(val, bank, offset);
139}
140
141#ifdef CONFIG_ARCH_OMAP730
142static struct omap_irq_bank omap730_irq_banks[] = {
Tony Lindgren120db2c2006-04-02 17:46:27 +0100143 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
144 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
146};
147#endif
148
Tony Lindgren3179a012005-11-10 14:26:48 +0000149#ifdef CONFIG_ARCH_OMAP15XX
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150static struct omap_irq_bank omap1510_irq_banks[] = {
Tony Lindgren120db2c2006-04-02 17:46:27 +0100151 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
152 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153};
Tony Lindgren3179a012005-11-10 14:26:48 +0000154static struct omap_irq_bank omap310_irq_banks[] = {
Tony Lindgren120db2c2006-04-02 17:46:27 +0100155 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
156 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
Tony Lindgren3179a012005-11-10 14:26:48 +0000157};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158#endif
159
160#if defined(CONFIG_ARCH_OMAP16XX)
161
162static struct omap_irq_bank omap1610_irq_banks[] = {
Tony Lindgren120db2c2006-04-02 17:46:27 +0100163 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
164 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
Tony Lindgren3b59b6b2005-07-10 19:58:09 +0100165 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
167};
168#endif
169
David Brownell38c677c2006-08-01 22:26:25 +0100170static struct irq_chip omap_irq_chip = {
171 .name = "MPU",
Russell King2be863c2005-09-06 23:13:17 +0100172 .ack = omap_mask_ack_irq,
173 .mask = omap_mask_irq,
174 .unmask = omap_unmask_irq,
175 .set_wake = omap_wake_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176};
177
178void __init omap_init_irq(void)
179{
180 int i, j;
181
182#ifdef CONFIG_ARCH_OMAP730
183 if (cpu_is_omap730()) {
184 irq_banks = omap730_irq_banks;
185 irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
186 }
187#endif
Tony Lindgren3179a012005-11-10 14:26:48 +0000188#ifdef CONFIG_ARCH_OMAP15XX
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 if (cpu_is_omap1510()) {
190 irq_banks = omap1510_irq_banks;
191 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
192 }
Tony Lindgren3179a012005-11-10 14:26:48 +0000193 if (cpu_is_omap310()) {
194 irq_banks = omap310_irq_banks;
195 irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
196 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197#endif
198#if defined(CONFIG_ARCH_OMAP16XX)
199 if (cpu_is_omap16xx()) {
200 irq_banks = omap1610_irq_banks;
201 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
202 }
203#endif
204 printk("Total of %i interrupts in %i interrupt banks\n",
205 irq_bank_count * 32, irq_bank_count);
206
207 /* Mask and clear all interrupts */
208 for (i = 0; i < irq_bank_count; i++) {
209 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
210 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
211 }
212
213 /* Clear any pending interrupts */
214 irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
215 irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
216
217 /* Enable interrupts in global mask */
218 if (cpu_is_omap730()) {
219 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
220 }
221
222 /* Install the interrupt handlers for each bank */
223 for (i = 0; i < irq_bank_count; i++) {
224 for (j = i * 32; j < (i + 1) * 32; j++) {
225 int irq_trigger;
226
227 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
228 omap_irq_set_cfg(j, 0, 0, irq_trigger);
229
230 set_irq_chip(j, &omap_irq_chip);
Russell King10dd5ce2006-11-23 11:41:32 +0000231 set_irq_handler(j, handle_level_irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232 set_irq_flags(j, IRQF_VALID);
233 }
234 }
235
236 /* Unmask level 2 handler */
Tony Lindgren3179a012005-11-10 14:26:48 +0000237
238 if (cpu_is_omap730())
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239 omap_unmask_irq(INT_730_IH2_IRQ);
Andrzej Zaborowskief557d72006-12-06 17:13:48 -0800240 else if (cpu_is_omap15xx())
Tony Lindgren3179a012005-11-10 14:26:48 +0000241 omap_unmask_irq(INT_1510_IH2_IRQ);
242 else if (cpu_is_omap16xx())
243 omap_unmask_irq(INT_1610_IH2_IRQ);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244}