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Ingo Molnarc140df92008-01-30 13:30:09 +01001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Firmware replacement code.
Ingo Molnarc140df92008-01-30 13:30:09 +01003 *
Pavel Machek8caac562008-11-26 17:15:27 +01004 * Work around broken BIOSes that don't set an aperture, only set the
5 * aperture in the AGP bridge, or set too small aperture.
6 *
Ingo Molnarc140df92008-01-30 13:30:09 +01007 * If all fails map the aperture over some low memory. This is cheaper than
8 * doing bounce buffering. The memory is lost. This is done at early boot
9 * because only the bootmem allocator can allocate 32+MB.
10 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 * Copyright 2002 Andi Kleen, SuSE Labs.
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
Yinghai Lu32e3f2b2010-12-17 16:58:40 -080016#include <linux/memblock.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/mmzone.h>
18#include <linux/pci_ids.h>
19#include <linux/pci.h>
20#include <linux/bitops.h>
Aaron Durbin56dd6692006-09-26 10:52:40 +020021#include <linux/ioport.h>
Pavel Machek2050d452008-03-13 23:05:41 +010022#include <linux/suspend.h>
Catalin Marinasacde31d2009-08-27 14:29:20 +010023#include <linux/kmemleak.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <asm/e820.h>
25#include <asm/io.h>
FUJITA Tomonori46a7fa22008-07-11 10:23:42 +090026#include <asm/iommu.h>
Joerg Roedel395624f2007-10-24 12:49:47 +020027#include <asm/gart.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <asm/pci-direct.h>
Andi Kleenca8642f2006-01-11 22:44:27 +010029#include <asm/dma.h>
Andreas Herrmann23ac4ae2010-09-17 18:03:43 +020030#include <asm/amd_nb.h>
FUJITA Tomonoride957622009-11-10 19:46:14 +090031#include <asm/x86_init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070032
Joerg Roedel0440d4c2007-10-24 12:49:50 +020033int gart_iommu_aperture;
Pavel Machek7de6a4c2008-03-13 11:03:58 +010034int gart_iommu_aperture_disabled __initdata;
35int gart_iommu_aperture_allowed __initdata;
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
37int fallback_aper_order __initdata = 1; /* 64MB */
Pavel Machek7de6a4c2008-03-13 11:03:58 +010038int fallback_aper_force __initdata;
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
40int fix_aperture __initdata = 1;
41
Aaron Durbin56dd6692006-09-26 10:52:40 +020042static struct resource gart_resource = {
43 .name = "GART",
44 .flags = IORESOURCE_MEM,
45};
46
47static void __init insert_aperture_resource(u32 aper_base, u32 aper_size)
48{
49 gart_resource.start = aper_base;
50 gart_resource.end = aper_base + aper_size - 1;
51 insert_resource(&iomem_resource, &gart_resource);
52}
53
Andrew Morton42442ed2005-06-08 15:49:25 -070054/* This code runs before the PCI subsystem is initialized, so just
55 access the northbridge directly. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070056
Ingo Molnarc140df92008-01-30 13:30:09 +010057static u32 __init allocate_aperture(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070058{
Linus Torvalds1da177e2005-04-16 15:20:36 -070059 u32 aper_size;
Yinghai Lu32e3f2b2010-12-17 16:58:40 -080060 unsigned long addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -070061
Yinghai Lu7677b2e2008-04-14 20:40:37 -070062 /* aper_size should <= 1G */
63 if (fallback_aper_order > 5)
64 fallback_aper_order = 5;
Ingo Molnarc140df92008-01-30 13:30:09 +010065 aper_size = (32 * 1024 * 1024) << fallback_aper_order;
Linus Torvalds1da177e2005-04-16 15:20:36 -070066
Ingo Molnarc140df92008-01-30 13:30:09 +010067 /*
68 * Aperture has to be naturally aligned. This means a 2GB aperture
69 * won't have much chance of finding a place in the lower 4GB of
70 * memory. Unfortunately we cannot move it up because that would
71 * make the IOMMU useless.
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 */
Yinghai Lu7677b2e2008-04-14 20:40:37 -070073 /*
74 * using 512M as goal, in case kexec will load kernel_big
75 * that will do the on position decompress, and could overlap with
Lucas De Marchi0d2eb442011-03-17 16:24:16 -030076 * that position with gart that is used.
Yinghai Lu7677b2e2008-04-14 20:40:37 -070077 * sequende:
78 * kernel_small
79 * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
80 * ==> kernel_small(gart area become e820_reserved)
81 * ==> kexec (with kdump trigger path or previous doesn't shutdown gart)
82 * ==> kerne_big (uncompressed size will be big than 64M or 128M)
83 * so don't use 512M below as gart iommu, leave the space for kernel
84 * code for safe
85 */
Yinghai Lu32e3f2b2010-12-17 16:58:40 -080086 addr = memblock_find_in_range(0, 1ULL<<32, aper_size, 512ULL<<20);
87 if (addr == MEMBLOCK_ERROR || addr + aper_size > 0xffffffff) {
88 printk(KERN_ERR
89 "Cannot allocate aperture memory hole (%lx,%uK)\n",
90 addr, aper_size>>10);
91 return 0;
92 }
93 memblock_x86_reserve_range(addr, addr + aper_size, "aperture64");
Catalin Marinasacde31d2009-08-27 14:29:20 +010094 /*
95 * Kmemleak should not scan this block as it may not be mapped via the
96 * kernel direct mapping.
97 */
Yinghai Lu32e3f2b2010-12-17 16:58:40 -080098 kmemleak_ignore(phys_to_virt(addr));
Ingo Molnar31183ba2008-01-30 13:30:10 +010099 printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n",
Yinghai Lu32e3f2b2010-12-17 16:58:40 -0800100 aper_size >> 10, addr);
101 insert_aperture_resource((u32)addr, aper_size);
102 register_nosave_region(addr >> PAGE_SHIFT,
103 (addr+aper_size) >> PAGE_SHIFT);
Ingo Molnarc140df92008-01-30 13:30:09 +0100104
Yinghai Lu32e3f2b2010-12-17 16:58:40 -0800105 return (u32)addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106}
107
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108
Andrew Morton42442ed2005-06-08 15:49:25 -0700109/* Find a PCI capability */
Pavel Machekdd564d02008-05-27 18:03:56 +0200110static u32 __init find_cap(int bus, int slot, int func, int cap)
Ingo Molnarc140df92008-01-30 13:30:09 +0100111{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112 int bytes;
Ingo Molnarc140df92008-01-30 13:30:09 +0100113 u8 pos;
114
Yinghai Lu55c0d722008-04-19 01:31:11 -0700115 if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
Ingo Molnarc140df92008-01-30 13:30:09 +0100116 PCI_STATUS_CAP_LIST))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117 return 0;
Ingo Molnarc140df92008-01-30 13:30:09 +0100118
Yinghai Lu55c0d722008-04-19 01:31:11 -0700119 pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
Ingo Molnarc140df92008-01-30 13:30:09 +0100120 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121 u8 id;
Ingo Molnarc140df92008-01-30 13:30:09 +0100122
123 pos &= ~3;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700124 id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125 if (id == 0xff)
126 break;
Ingo Molnarc140df92008-01-30 13:30:09 +0100127 if (id == cap)
128 return pos;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700129 pos = read_pci_config_byte(bus, slot, func,
Ingo Molnarc140df92008-01-30 13:30:09 +0100130 pos+PCI_CAP_LIST_NEXT);
131 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132 return 0;
Ingo Molnarc140df92008-01-30 13:30:09 +0100133}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134
135/* Read a standard AGPv3 bridge header */
Pavel Machekdd564d02008-05-27 18:03:56 +0200136static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
Ingo Molnarc140df92008-01-30 13:30:09 +0100137{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138 u32 apsize;
139 u32 apsizereg;
140 int nbits;
141 u32 aper_low, aper_hi;
142 u64 aper;
Yinghai Lu1edc1ab2008-04-13 01:11:41 -0700143 u32 old_order;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144
Yinghai Lu55c0d722008-04-19 01:31:11 -0700145 printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", bus, slot, func);
146 apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 if (apsizereg == 0xffffffff) {
Ingo Molnar31183ba2008-01-30 13:30:10 +0100148 printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149 return 0;
150 }
151
Yinghai Lu1edc1ab2008-04-13 01:11:41 -0700152 /* old_order could be the value from NB gart setting */
153 old_order = *order;
154
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155 apsize = apsizereg & 0xfff;
156 /* Some BIOS use weird encodings not in the AGPv3 table. */
Ingo Molnarc140df92008-01-30 13:30:09 +0100157 if (apsize & 0xff)
158 apsize |= 0xf00;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159 nbits = hweight16(apsize);
160 *order = 7 - nbits;
161 if ((int)*order < 0) /* < 32MB */
162 *order = 0;
Ingo Molnarc140df92008-01-30 13:30:09 +0100163
Yinghai Lu55c0d722008-04-19 01:31:11 -0700164 aper_low = read_pci_config(bus, slot, func, 0x10);
165 aper_hi = read_pci_config(bus, slot, func, 0x14);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
167
Yinghai Lu1edc1ab2008-04-13 01:11:41 -0700168 /*
169 * On some sick chips, APSIZE is 0. It means it wants 4G
170 * so let double check that order, and lets trust AMD NB settings:
171 */
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700172 printk(KERN_INFO "Aperture from AGP @ %Lx old size %u MB\n",
173 aper, 32 << old_order);
174 if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
Yinghai Lu1edc1ab2008-04-13 01:11:41 -0700175 printk(KERN_INFO "Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n",
176 32 << *order, apsizereg);
177 *order = old_order;
178 }
179
Ingo Molnar31183ba2008-01-30 13:30:10 +0100180 printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
181 aper, 32 << *order, apsizereg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700183 if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
Ingo Molnarc140df92008-01-30 13:30:09 +0100184 return 0;
185 return (u32)aper;
186}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187
Ingo Molnarc140df92008-01-30 13:30:09 +0100188/*
189 * Look for an AGP bridge. Windows only expects the aperture in the
190 * AGP bridge and some BIOS forget to initialize the Northbridge too.
191 * Work around this here.
192 *
193 * Do an PCI bus scan by hand because we're running before the PCI
194 * subsystem.
195 *
Hans Rosenfeldeec1d4f2010-10-29 17:14:30 +0200196 * All AMD AGP bridges are AGPv3 compliant, so we can do this scan
Ingo Molnarc140df92008-01-30 13:30:09 +0100197 * generically. It's probably overkill to always scan all slots because
198 * the AGP bridges should be always an own bus on the HT hierarchy,
199 * but do it here for future safety.
200 */
Pavel Machekdd564d02008-05-27 18:03:56 +0200201static u32 __init search_agp_bridge(u32 *order, int *valid_agp)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700202{
Yinghai Lu55c0d722008-04-19 01:31:11 -0700203 int bus, slot, func;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204
205 /* Poor man's PCI discovery */
Yinghai Lu55c0d722008-04-19 01:31:11 -0700206 for (bus = 0; bus < 256; bus++) {
Ingo Molnarc140df92008-01-30 13:30:09 +0100207 for (slot = 0; slot < 32; slot++) {
208 for (func = 0; func < 8; func++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209 u32 class, cap;
210 u8 type;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700211 class = read_pci_config(bus, slot, func,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212 PCI_CLASS_REVISION);
213 if (class == 0xffffffff)
Ingo Molnarc140df92008-01-30 13:30:09 +0100214 break;
215
216 switch (class >> 16) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217 case PCI_CLASS_BRIDGE_HOST:
218 case PCI_CLASS_BRIDGE_OTHER: /* needed? */
219 /* AGP bridge? */
Yinghai Lu55c0d722008-04-19 01:31:11 -0700220 cap = find_cap(bus, slot, func,
Ingo Molnarc140df92008-01-30 13:30:09 +0100221 PCI_CAP_ID_AGP);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222 if (!cap)
223 break;
Ingo Molnarc140df92008-01-30 13:30:09 +0100224 *valid_agp = 1;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700225 return read_agp(bus, slot, func, cap,
Ingo Molnarc140df92008-01-30 13:30:09 +0100226 order);
227 }
228
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229 /* No multi-function device? */
Yinghai Lu55c0d722008-04-19 01:31:11 -0700230 type = read_pci_config_byte(bus, slot, func,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231 PCI_HEADER_TYPE);
232 if (!(type & 0x80))
233 break;
Ingo Molnarc140df92008-01-30 13:30:09 +0100234 }
235 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236 }
Ingo Molnar31183ba2008-01-30 13:30:10 +0100237 printk(KERN_INFO "No AGP bridge found\n");
Ingo Molnarc140df92008-01-30 13:30:09 +0100238
Linus Torvalds1da177e2005-04-16 15:20:36 -0700239 return 0;
240}
241
Yinghai Luaaf23042008-01-30 13:33:09 +0100242static int gart_fix_e820 __initdata = 1;
243
244static int __init parse_gart_mem(char *p)
245{
246 if (!p)
247 return -EINVAL;
248
249 if (!strncmp(p, "off", 3))
250 gart_fix_e820 = 0;
251 else if (!strncmp(p, "on", 2))
252 gart_fix_e820 = 1;
253
254 return 0;
255}
256early_param("gart_fix_e820", parse_gart_mem);
257
258void __init early_gart_iommu_check(void)
259{
260 /*
261 * in case it is enabled before, esp for kexec/kdump,
262 * previous kernel already enable that. memset called
263 * by allocate_aperture/__alloc_bootmem_nopanic cause restart.
264 * or second kernel have different position for GART hole. and new
265 * kernel could use hole as RAM that is still used by GART set by
266 * first kernel
267 * or BIOS forget to put that in reserved.
268 * try to update e820 to make that region as reserved.
269 */
Andi Kleenfa10ba62010-07-20 15:19:49 -0700270 u32 agp_aper_order = 0;
Yinghai Luf3eee542009-12-14 11:52:15 +0900271 int i, fix, slot, valid_agp = 0;
Yinghai Luaaf23042008-01-30 13:33:09 +0100272 u32 ctl;
273 u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
274 u64 aper_base = 0, last_aper_base = 0;
Pavel Machekfa5b8a32008-05-26 20:40:47 +0200275 int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
Yinghai Luaaf23042008-01-30 13:33:09 +0100276
277 if (!early_pci_allowed())
278 return;
279
Pavel Machekfa5b8a32008-05-26 20:40:47 +0200280 /* This is mostly duplicate of iommu_hole_init */
Andi Kleenfa10ba62010-07-20 15:19:49 -0700281 search_agp_bridge(&agp_aper_order, &valid_agp);
Yinghai Luf3eee542009-12-14 11:52:15 +0900282
Yinghai Luaaf23042008-01-30 13:33:09 +0100283 fix = 0;
Jan Beulich24d9b702011-01-10 16:20:23 +0000284 for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) {
Yinghai Lu55c0d722008-04-19 01:31:11 -0700285 int bus;
286 int dev_base, dev_limit;
Yinghai Luaaf23042008-01-30 13:33:09 +0100287
Jan Beulich24d9b702011-01-10 16:20:23 +0000288 bus = amd_nb_bus_dev_ranges[i].bus;
289 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
290 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
Yinghai Luaaf23042008-01-30 13:33:09 +0100291
Yinghai Lu55c0d722008-04-19 01:31:11 -0700292 for (slot = dev_base; slot < dev_limit; slot++) {
Hans Rosenfeldeec1d4f2010-10-29 17:14:30 +0200293 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
Yinghai Lu55c0d722008-04-19 01:31:11 -0700294 continue;
295
296 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
Borislav Petkov57ab43e2010-09-03 18:39:39 +0200297 aper_enabled = ctl & GARTEN;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700298 aper_order = (ctl >> 1) & 7;
299 aper_size = (32 * 1024 * 1024) << aper_order;
300 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
301 aper_base <<= 25;
302
Pavel Machekfa5b8a32008-05-26 20:40:47 +0200303 if (last_valid) {
304 if ((aper_order != last_aper_order) ||
305 (aper_base != last_aper_base) ||
306 (aper_enabled != last_aper_enabled)) {
307 fix = 1;
308 break;
309 }
Yinghai Lu55c0d722008-04-19 01:31:11 -0700310 }
Pavel Machekfa5b8a32008-05-26 20:40:47 +0200311
Yinghai Lu55c0d722008-04-19 01:31:11 -0700312 last_aper_order = aper_order;
313 last_aper_base = aper_base;
314 last_aper_enabled = aper_enabled;
Pavel Machekfa5b8a32008-05-26 20:40:47 +0200315 last_valid = 1;
Yinghai Luaaf23042008-01-30 13:33:09 +0100316 }
Yinghai Luaaf23042008-01-30 13:33:09 +0100317 }
318
319 if (!fix && !aper_enabled)
320 return;
321
322 if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
323 fix = 1;
324
325 if (gart_fix_e820 && !fix && aper_enabled) {
Yinghai Lu07545572008-06-21 03:50:47 -0700326 if (e820_any_mapped(aper_base, aper_base + aper_size,
327 E820_RAM)) {
Pavel Machek0abbc782008-05-20 16:27:17 +0200328 /* reserve it, so we can reuse it in second kernel */
Yinghai Luaaf23042008-01-30 13:33:09 +0100329 printk(KERN_INFO "update e820 for GART\n");
Yinghai Lud0be6bd2008-06-15 18:58:51 -0700330 e820_add_region(aper_base, aper_size, E820_RESERVED);
Yinghai Luaaf23042008-01-30 13:33:09 +0100331 update_e820();
332 }
Yinghai Luaaf23042008-01-30 13:33:09 +0100333 }
334
Yinghai Luf3eee542009-12-14 11:52:15 +0900335 if (valid_agp)
Pavel Machek4f384f82008-05-26 21:17:30 +0200336 return;
337
Yinghai Luf3eee542009-12-14 11:52:15 +0900338 /* disable them all at first */
Jan Beulich24d9b702011-01-10 16:20:23 +0000339 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
Yinghai Lu55c0d722008-04-19 01:31:11 -0700340 int bus;
341 int dev_base, dev_limit;
Yinghai Luaaf23042008-01-30 13:33:09 +0100342
Jan Beulich24d9b702011-01-10 16:20:23 +0000343 bus = amd_nb_bus_dev_ranges[i].bus;
344 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
345 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700346
347 for (slot = dev_base; slot < dev_limit; slot++) {
Hans Rosenfeldeec1d4f2010-10-29 17:14:30 +0200348 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
Yinghai Lu55c0d722008-04-19 01:31:11 -0700349 continue;
350
351 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
Borislav Petkov57ab43e2010-09-03 18:39:39 +0200352 ctl &= ~GARTEN;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700353 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
354 }
Yinghai Luaaf23042008-01-30 13:33:09 +0100355 }
356
357}
358
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700359static int __initdata printed_gart_size_msg;
360
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400361int __init gart_iommu_hole_init(void)
Ingo Molnarc140df92008-01-30 13:30:09 +0100362{
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700363 u32 agp_aper_base = 0, agp_aper_order = 0;
Andi Kleen50895c52005-11-05 17:25:53 +0100364 u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365 u64 aper_base, last_aper_base = 0;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700366 int fix, slot, valid_agp = 0;
367 int i, node;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368
Joerg Roedel0440d4c2007-10-24 12:49:50 +0200369 if (gart_iommu_aperture_disabled || !fix_aperture ||
370 !early_pci_allowed())
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400371 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372
Dan Aloni753811d2007-07-21 17:11:36 +0200373 printk(KERN_INFO "Checking aperture...\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700375 if (!fallback_aper_force)
376 agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
377
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378 fix = 0;
Yinghai Lu47db4c32008-01-30 13:33:18 +0100379 node = 0;
Jan Beulich24d9b702011-01-10 16:20:23 +0000380 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
Yinghai Lu55c0d722008-04-19 01:31:11 -0700381 int bus;
382 int dev_base, dev_limit;
Joerg Roedel4b838732010-04-07 12:57:35 +0200383 u32 ctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384
Jan Beulich24d9b702011-01-10 16:20:23 +0000385 bus = amd_nb_bus_dev_ranges[i].bus;
386 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
387 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388
Yinghai Lu55c0d722008-04-19 01:31:11 -0700389 for (slot = dev_base; slot < dev_limit; slot++) {
Hans Rosenfeldeec1d4f2010-10-29 17:14:30 +0200390 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
Yinghai Lu55c0d722008-04-19 01:31:11 -0700391 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392
Yinghai Lu55c0d722008-04-19 01:31:11 -0700393 iommu_detected = 1;
394 gart_iommu_aperture = 1;
FUJITA Tomonoride957622009-11-10 19:46:14 +0900395 x86_init.iommu.iommu_init = gart_iommu_init;
Ingo Molnarc140df92008-01-30 13:30:09 +0100396
Joerg Roedel4b838732010-04-07 12:57:35 +0200397 ctl = read_pci_config(bus, slot, 3,
398 AMD64_GARTAPERTURECTL);
399
400 /*
401 * Before we do anything else disable the GART. It may
402 * still be enabled if we boot into a crash-kernel here.
403 * Reconfiguring the GART while it is enabled could have
404 * unknown side-effects.
405 */
406 ctl &= ~GARTEN;
407 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
408
409 aper_order = (ctl >> 1) & 7;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700410 aper_size = (32 * 1024 * 1024) << aper_order;
411 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
412 aper_base <<= 25;
413
414 printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
415 node, aper_base, aper_size >> 20);
416 node++;
417
418 if (!aperture_valid(aper_base, aper_size, 64<<20)) {
419 if (valid_agp && agp_aper_base &&
420 agp_aper_base == aper_base &&
421 agp_aper_order == aper_order) {
422 /* the same between two setting from NB and agp */
Yinghai Luc987d122008-06-24 22:14:09 -0700423 if (!no_iommu &&
424 max_pfn > MAX_DMA32_PFN &&
425 !printed_gart_size_msg) {
Yinghai Lu55c0d722008-04-19 01:31:11 -0700426 printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n");
427 printk(KERN_ERR "please increase GART size in your BIOS setup\n");
428 printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n");
429 printed_gart_size_msg = 1;
430 }
431 } else {
432 fix = 1;
433 goto out;
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700434 }
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700435 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436
Yinghai Lu55c0d722008-04-19 01:31:11 -0700437 if ((last_aper_order && aper_order != last_aper_order) ||
438 (last_aper_base && aper_base != last_aper_base)) {
439 fix = 1;
440 goto out;
441 }
442 last_aper_order = aper_order;
443 last_aper_base = aper_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444 }
Ingo Molnarc140df92008-01-30 13:30:09 +0100445 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446
Yinghai Lu55c0d722008-04-19 01:31:11 -0700447out:
Aaron Durbin56dd6692006-09-26 10:52:40 +0200448 if (!fix && !fallback_aper_force) {
449 if (last_aper_base) {
450 unsigned long n = (32 * 1024 * 1024) << last_aper_order;
Ingo Molnarc140df92008-01-30 13:30:09 +0100451
Aaron Durbin56dd6692006-09-26 10:52:40 +0200452 insert_aperture_resource((u32)last_aper_base, n);
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400453 return 1;
Aaron Durbin56dd6692006-09-26 10:52:40 +0200454 }
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400455 return 0;
Aaron Durbin56dd6692006-09-26 10:52:40 +0200456 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700458 if (!fallback_aper_force) {
459 aper_alloc = agp_aper_base;
460 aper_order = agp_aper_order;
461 }
Ingo Molnarc140df92008-01-30 13:30:09 +0100462
463 if (aper_alloc) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464 /* Got the aperture from the AGP bridge */
Yinghai Luc987d122008-06-24 22:14:09 -0700465 } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) ||
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466 force_iommu ||
467 valid_agp ||
Ingo Molnarc140df92008-01-30 13:30:09 +0100468 fallback_aper_force) {
Adam Jackson9b156842008-09-29 14:52:03 -0400469 printk(KERN_INFO
Ingo Molnar31183ba2008-01-30 13:30:10 +0100470 "Your BIOS doesn't leave a aperture memory hole\n");
Adam Jackson9b156842008-09-29 14:52:03 -0400471 printk(KERN_INFO
Ingo Molnar31183ba2008-01-30 13:30:10 +0100472 "Please enable the IOMMU option in the BIOS setup\n");
Adam Jackson9b156842008-09-29 14:52:03 -0400473 printk(KERN_INFO
Ingo Molnar31183ba2008-01-30 13:30:10 +0100474 "This costs you %d MB of RAM\n",
475 32 << fallback_aper_order);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476
477 aper_order = fallback_aper_order;
478 aper_alloc = allocate_aperture();
Ingo Molnarc140df92008-01-30 13:30:09 +0100479 if (!aper_alloc) {
480 /*
481 * Could disable AGP and IOMMU here, but it's
482 * probably not worth it. But the later users
483 * cannot deal with bad apertures and turning
484 * on the aperture over memory causes very
485 * strange problems, so it's better to panic
486 * early.
487 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488 panic("Not enough memory for aperture");
489 }
Ingo Molnarc140df92008-01-30 13:30:09 +0100490 } else {
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400491 return 0;
Ingo Molnarc140df92008-01-30 13:30:09 +0100492 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493
494 /* Fix up the north bridges */
Jan Beulich24d9b702011-01-10 16:20:23 +0000495 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
Borislav Petkov260133a2010-09-03 18:39:40 +0200496 int bus, dev_base, dev_limit;
497
498 /*
499 * Don't enable translation yet but enable GART IO and CPU
500 * accesses and set DISTLBWALKPRB since GART table memory is UC.
501 */
502 u32 ctl = DISTLBWALKPRB | aper_order << 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503
Jan Beulich24d9b702011-01-10 16:20:23 +0000504 bus = amd_nb_bus_dev_ranges[i].bus;
505 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
506 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700507 for (slot = dev_base; slot < dev_limit; slot++) {
Hans Rosenfeldeec1d4f2010-10-29 17:14:30 +0200508 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
Yinghai Lu55c0d722008-04-19 01:31:11 -0700509 continue;
510
Borislav Petkov260133a2010-09-03 18:39:40 +0200511 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
Yinghai Lu55c0d722008-04-19 01:31:11 -0700512 write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
513 }
Ingo Molnarc140df92008-01-30 13:30:09 +0100514 }
Rafael J. Wysocki6703f6d2008-06-10 00:10:48 +0200515
516 set_up_gart_resume(aper_order, aper_alloc);
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400517
518 return 1;
Ingo Molnarc140df92008-01-30 13:30:09 +0100519}