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googlers / maze / linux / bd8031b49a9b05933fb1ec1c36620ed4e1e67793 / . / drivers / scsi / arcmsr / arcmsr.h
blob: aff96db9ccf6b78fc5d38967bb45d8e85842201b [file] [log] [blame]
Erich Chen1c57e862006-07-12 08:59:32 -0700[diff] [blame]1/*
2*******************************************************************************
3** O.S : Linux
4** FILE NAME : arcmsr.h
5** BY : Erich Chen
6** Description: SCSI RAID Device Driver for
7** ARECA RAID Host adapter
8*******************************************************************************
9** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
10**
11** Web site: www.areca.com.tw
12** E-mail: erich@areca.com.tw
13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License version 2 as
16** published by the Free Software Foundation.
17** This program is distributed in the hope that it will be useful,
18** but WITHOUT ANY WARRANTY; without even the implied warranty of
19** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20** GNU General Public License for more details.
21*******************************************************************************
22** Redistribution and use in source and binary forms, with or without
23** modification, are permitted provided that the following conditions
24** are met:
25** 1. Redistributions of source code must retain the above copyright
26** notice, this list of conditions and the following disclaimer.
27** 2. Redistributions in binary form must reproduce the above copyright
28** notice, this list of conditions and the following disclaimer in the
29** documentation and/or other materials provided with the distribution.
30** 3. The name of the author may not be used to endorse or promote products
31** derived from this software without specific prior written permission.
32**
33** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
34** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
35** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
36** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
37** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
38** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
40** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41**(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43*******************************************************************************
44*/
45#include <linux/interrupt.h>
46
47struct class_device_attribute;
48
49#define ARCMSR_MAX_OUTSTANDING_CMD 256
50#define ARCMSR_MAX_FREECCB_NUM 288
51#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.13"
52#define ARCMSR_SCSI_INITIATOR_ID 255
53#define ARCMSR_MAX_XFER_SECTORS 512
54#define ARCMSR_MAX_TARGETID 17
55#define ARCMSR_MAX_TARGETLUN 8
56#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD
57#define ARCMSR_MAX_QBUFFER 4096
58#define ARCMSR_MAX_SG_ENTRIES 38
59
60/*
61*******************************************************************************
62** split 64bits dma addressing
63*******************************************************************************
64*/
65#define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
66#define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
67/*
68*******************************************************************************
69** MESSAGE CONTROL CODE
70*******************************************************************************
71*/
72struct CMD_MESSAGE
73{
74 uint32_t HeaderLength;
75 uint8_t Signature[8];
76 uint32_t Timeout;
77 uint32_t ControlCode;
78 uint32_t ReturnCode;
79 uint32_t Length;
80};
81/*
82*******************************************************************************
83** IOP Message Transfer Data for user space
84*******************************************************************************
85*/
86struct CMD_MESSAGE_FIELD
87{
88 struct CMD_MESSAGE cmdmessage;
89 uint8_t messagedatabuffer[1032];
90};
91/* IOP message transfer */
92#define ARCMSR_MESSAGE_FAIL 0x0001
93/* DeviceType */
94#define ARECA_SATA_RAID 0x90000000
95/* FunctionCode */
96#define FUNCTION_READ_RQBUFFER 0x0801
97#define FUNCTION_WRITE_WQBUFFER 0x0802
98#define FUNCTION_CLEAR_RQBUFFER 0x0803
99#define FUNCTION_CLEAR_WQBUFFER 0x0804
100#define FUNCTION_CLEAR_ALLQBUFFER 0x0805
101#define FUNCTION_RETURN_CODE_3F 0x0806
102#define FUNCTION_SAY_HELLO 0x0807
103#define FUNCTION_SAY_GOODBYE 0x0808
104#define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
105/* ARECA IO CONTROL CODE*/
106#define ARCMSR_MESSAGE_READ_RQBUFFER \
107 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER
108#define ARCMSR_MESSAGE_WRITE_WQBUFFER \
109 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER
110#define ARCMSR_MESSAGE_CLEAR_RQBUFFER \
111 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER
112#define ARCMSR_MESSAGE_CLEAR_WQBUFFER \
113 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER
114#define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \
115 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER
116#define ARCMSR_MESSAGE_RETURN_CODE_3F \
117 ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F
118#define ARCMSR_MESSAGE_SAY_HELLO \
119 ARECA_SATA_RAID | FUNCTION_SAY_HELLO
120#define ARCMSR_MESSAGE_SAY_GOODBYE \
121 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE
122#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \
123 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE
124/* ARECA IOCTL ReturnCode */
125#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
126#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
127#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
128/*
129*************************************************************
130** structure for holding DMA address data
131*************************************************************
132*/
133#define IS_SG64_ADDR 0x01000000 /* bit24 */
134struct SG32ENTRY
135{
136 uint32_t length;
137 uint32_t address;
138};
139struct SG64ENTRY
140{
141 uint32_t length;
142 uint32_t address;
143 uint32_t addresshigh;
144};
145struct SGENTRY_UNION
146{
147 union
148 {
149 struct SG32ENTRY sg32entry;
150 struct SG64ENTRY sg64entry;
151 }u;
152};
153/*
154********************************************************************
155** Q Buffer of IOP Message Transfer
156********************************************************************
157*/
158struct QBUFFER
159{
160 uint32_t data_len;
161 uint8_t data[124];
162};
163/*
164*******************************************************************************
165** FIRMWARE INFO
166*******************************************************************************
167*/
168struct FIRMWARE_INFO
169{
170 uint32_t signature; /*0, 00-03*/
171 uint32_t request_len; /*1, 04-07*/
172 uint32_t numbers_queue; /*2, 08-11*/
173 uint32_t sdram_size; /*3, 12-15*/
174 uint32_t ide_channels; /*4, 16-19*/
175 char vendor[40]; /*5, 20-59*/
176 char model[8]; /*15, 60-67*/
177 char firmware_ver[16]; /*17, 68-83*/
178 char device_map[16]; /*21, 84-99*/
179};
180/* signature of set and get firmware config */
181#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
182#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
183/* message code of inbound message register */
184#define ARCMSR_INBOUND_MESG0_NOP 0x00000000
185#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
186#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
187#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
188#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
189#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
190#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
191#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
192#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
193/* doorbell interrupt generator */
194#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
195#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
196#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
197#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
198/* ccb areca cdb flag */
199#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
200#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
201#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
202#define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000
203/* outbound firmware ok */
204#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
205/*
206*******************************************************************************
207** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
208*******************************************************************************
209*/
210struct ARCMSR_CDB
211{
212 uint8_t Bus;
213 uint8_t TargetID;
214 uint8_t LUN;
215 uint8_t Function;
216
217 uint8_t CdbLength;
218 uint8_t sgcount;
219 uint8_t Flags;
220#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01
221#define ARCMSR_CDB_FLAG_BIOS 0x02
222#define ARCMSR_CDB_FLAG_WRITE 0x04
223#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00
224#define ARCMSR_CDB_FLAG_HEADQ 0x08
225#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
226 uint8_t Reserved1;
227
228 uint32_t Context;
229 uint32_t DataLength;
230
231 uint8_t Cdb[16];
232
233 uint8_t DeviceStatus;
234#define ARCMSR_DEV_CHECK_CONDITION 0x02
235#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
236#define ARCMSR_DEV_ABORTED 0xF1
237#define ARCMSR_DEV_INIT_FAIL 0xF2
238 uint8_t SenseData[15];
239
240 union
241 {
242 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES];
243 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES];
244 } u;
245};
246/*
247*******************************************************************************
248** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331)
249*******************************************************************************
250*/
251struct MessageUnit
252{
253 uint32_t resrved0[4]; /*0000 000F*/
254 uint32_t inbound_msgaddr0; /*0010 0013*/
255 uint32_t inbound_msgaddr1; /*0014 0017*/
256 uint32_t outbound_msgaddr0; /*0018 001B*/
257 uint32_t outbound_msgaddr1; /*001C 001F*/
258 uint32_t inbound_doorbell; /*0020 0023*/
259 uint32_t inbound_intstatus; /*0024 0027*/
260 uint32_t inbound_intmask; /*0028 002B*/
261 uint32_t outbound_doorbell; /*002C 002F*/
262 uint32_t outbound_intstatus; /*0030 0033*/
263 uint32_t outbound_intmask; /*0034 0037*/
264 uint32_t reserved1[2]; /*0038 003F*/
265 uint32_t inbound_queueport; /*0040 0043*/
266 uint32_t outbound_queueport; /*0044 0047*/
267 uint32_t reserved2[2]; /*0048 004F*/
268 uint32_t reserved3[492]; /*0050 07FF 492*/
269 uint32_t reserved4[128]; /*0800 09FF 128*/
270 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/
271 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/
272 uint32_t reserved5[32]; /*0E80 0EFF 32*/
273 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/
274 uint32_t reserved6[32]; /*0F80 0FFF 32*/
275};
276/*
277*******************************************************************************
278** Adapter Control Block
279*******************************************************************************
280*/
281struct AdapterControlBlock
282{
283 struct pci_dev * pdev;
284 struct Scsi_Host * host;
285 unsigned long vir2phy_offset;
286 /* Offset is used in making arc cdb physical to virtual calculations */
287 uint32_t outbound_int_enable;
288
289 struct MessageUnit __iomem * pmu;
290 /* message unit ATU inbound base address0 */
291
292 uint32_t acb_flags;
293#define ACB_F_SCSISTOPADAPTER 0x0001
294#define ACB_F_MSG_STOP_BGRB 0x0002
295 /* stop RAID background rebuild */
296#define ACB_F_MSG_START_BGRB 0x0004
297 /* stop RAID background rebuild */
298#define ACB_F_IOPDATA_OVERFLOW 0x0008
299 /* iop message data rqbuffer overflow */
300#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
301 /* message clear wqbuffer */
302#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
303 /* message clear rqbuffer */
304#define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
305#define ACB_F_BUS_RESET 0x0080
306#define ACB_F_IOP_INITED 0x0100
307 /* iop init */
308
309 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM];
310 /* used for memory free */
311 struct list_head ccb_free_list;
312 /* head of free ccb list */
313 atomic_t ccboutstandingcount;
314
315 void * dma_coherent;
316 /* dma_coherent used for memory free */
317 dma_addr_t dma_coherent_handle;
318 /* dma_coherent_handle used for memory free */
319
320 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER];
321 /* data collection buffer for read from 80331 */
322 int32_t rqbuf_firstindex;
323 /* first of read buffer */
324 int32_t rqbuf_lastindex;
325 /* last of read buffer */
326 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER];
327 /* data collection buffer for write to 80331 */
328 int32_t wqbuf_firstindex;
329 /* first of write buffer */
330 int32_t wqbuf_lastindex;
331 /* last of write buffer */
332 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN];
333 /* id0 ..... id15, lun0...lun7 */
334#define ARECA_RAID_GONE 0x55
335#define ARECA_RAID_GOOD 0xaa
336 uint32_t num_resets;
337 uint32_t num_aborts;
338 uint32_t firm_request_len;
339 uint32_t firm_numbers_queue;
340 uint32_t firm_sdram_size;
341 uint32_t firm_hd_channels;
342 char firm_model[12];
343 char firm_version[20];
344};/* HW_DEVICE_EXTENSION */
345/*
346*******************************************************************************
347** Command Control Block
348** this CCB length must be 32 bytes boundary
349*******************************************************************************
350*/
351struct CommandControlBlock
352{
353 struct ARCMSR_CDB arcmsr_cdb;
354 /*
355 ** 0-503 (size of CDB=504):
356 ** arcmsr messenger scsi command descriptor size 504 bytes
357 */
358 uint32_t cdb_shifted_phyaddr;
359 /* 504-507 */
360 uint32_t reserved1;
361 /* 508-511 */
362#if BITS_PER_LONG == 64
363 /* ======================512+64 bytes======================== */
364 struct list_head list;
365 /* 512-527 16 bytes next/prev ptrs for ccb lists */
366 struct scsi_cmnd * pcmd;
367 /* 528-535 8 bytes pointer of linux scsi command */
368 struct AdapterControlBlock * acb;
369 /* 536-543 8 bytes pointer of acb */
370
371 uint16_t ccb_flags;
372 /* 544-545 */
373 #define CCB_FLAG_READ 0x0000
374 #define CCB_FLAG_WRITE 0x0001
375 #define CCB_FLAG_ERROR 0x0002
376 #define CCB_FLAG_FLUSHCACHE 0x0004
377 #define CCB_FLAG_MASTER_ABORTED 0x0008
378 uint16_t startdone;
379 /* 546-547 */
380 #define ARCMSR_CCB_DONE 0x0000
381 #define ARCMSR_CCB_START 0x55AA
382 #define ARCMSR_CCB_ABORTED 0xAA55
383 #define ARCMSR_CCB_ILLEGAL 0xFFFF
384 uint32_t reserved2[7];
385 /* 548-551 552-555 556-559 560-563 564-567 568-571 572-575 */
386#else
387 /* ======================512+32 bytes======================== */
388 struct list_head list;
389 /* 512-519 8 bytes next/prev ptrs for ccb lists */
390 struct scsi_cmnd * pcmd;
391 /* 520-523 4 bytes pointer of linux scsi command */
392 struct AdapterControlBlock * acb;
393 /* 524-527 4 bytes pointer of acb */
394
395 uint16_t ccb_flags;
396 /* 528-529 */
397 #define CCB_FLAG_READ 0x0000
398 #define CCB_FLAG_WRITE 0x0001
399 #define CCB_FLAG_ERROR 0x0002
400 #define CCB_FLAG_FLUSHCACHE 0x0004
401 #define CCB_FLAG_MASTER_ABORTED 0x0008
402 uint16_t startdone;
403 /* 530-531 */
404 #define ARCMSR_CCB_DONE 0x0000
405 #define ARCMSR_CCB_START 0x55AA
406 #define ARCMSR_CCB_ABORTED 0xAA55
407 #define ARCMSR_CCB_ILLEGAL 0xFFFF
408 uint32_t reserved2[3];
409 /* 532-535 536-539 540-543 */
410#endif
411 /* ========================================================== */
412};
413/*
414*******************************************************************************
415** ARECA SCSI sense data
416*******************************************************************************
417*/
418struct SENSE_DATA
419{
420 uint8_t ErrorCode:7;
421#define SCSI_SENSE_CURRENT_ERRORS 0x70
422#define SCSI_SENSE_DEFERRED_ERRORS 0x71
423 uint8_t Valid:1;
424 uint8_t SegmentNumber;
425 uint8_t SenseKey:4;
426 uint8_t Reserved:1;
427 uint8_t IncorrectLength:1;
428 uint8_t EndOfMedia:1;
429 uint8_t FileMark:1;
430 uint8_t Information[4];
431 uint8_t AdditionalSenseLength;
432 uint8_t CommandSpecificInformation[4];
433 uint8_t AdditionalSenseCode;
434 uint8_t AdditionalSenseCodeQualifier;
435 uint8_t FieldReplaceableUnitCode;
436 uint8_t SenseKeySpecific[3];
437};
438/*
439*******************************************************************************
440** Outbound Interrupt Status Register - OISR
441*******************************************************************************
442*/
443#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30
444#define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
445#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
446#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
447#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
448#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
449#define ARCMSR_MU_OUTBOUND_HANDLE_INT \
450 (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \
451 |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \
452 |ARCMSR_MU_OUTBOUND_DOORBELL_INT \
453 |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \
454 |ARCMSR_MU_OUTBOUND_PCI_INT)
455/*
456*******************************************************************************
457** Outbound Interrupt Mask Register - OIMR
458*******************************************************************************
459*/
460#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34
461#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
462#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
463#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
464#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
465#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
466#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
467
468extern void arcmsr_post_Qbuffer(struct AdapterControlBlock *acb);
469extern struct class_device_attribute *arcmsr_host_attrs[];
470extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *acb);
471void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb);
472