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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* linux/arch/arm/mach-s3c2410/mach-bast.c
2 *
Ben Dooksccae9412009-11-13 22:54:14 +00003 * Copyright 2003-2008 Simtec Electronics
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
Linus Torvalds1da177e2005-04-16 15:20:36 -070011*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
Ben Dooksec976d62009-05-13 22:52:24 +010019#include <linux/gpio.h>
Ben Dooks6ddc4b02008-04-16 00:06:14 +010020#include <linux/sysdev.h>
Ben Dooksb6d1f542006-12-17 23:22:26 +010021#include <linux/serial_core.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010022#include <linux/platform_device.h>
Ben Dooksd97a6662005-06-23 21:56:47 +010023#include <linux/dm9000.h>
Ben Dooksb7a12d12008-07-03 11:24:37 +010024#include <linux/ata_platform.h>
Ben Dooks042cf0f2008-07-03 11:24:41 +010025#include <linux/i2c.h>
Russell Kingfced80c2008-09-06 12:10:45 +010026#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
Ben Dooks5ce4b1f2007-07-12 10:44:53 +010028#include <net/ax88796.h>
29
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32#include <asm/mach/irq.h>
33
Russell Kinga09e64f2008-08-05 16:14:15 +010034#include <mach/bast-map.h>
35#include <mach/bast-irq.h>
36#include <mach/bast-cpld.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
Russell Kinga09e64f2008-08-05 16:14:15 +010038#include <mach/hardware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#include <asm/irq.h>
40#include <asm/mach-types.h>
41
42//#include <asm/debug-ll.h>
Ben Dooksa2b7ba92008-10-07 22:26:09 +010043#include <plat/regs-serial.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010044#include <mach/regs-gpio.h>
45#include <mach/regs-mem.h>
46#include <mach/regs-lcd.h>
Ben Dooks58c8d572005-10-28 15:31:46 +010047
Ben Dooks885f9eb2009-07-18 10:12:26 +010048#include <plat/hwmon.h>
Ben Dooks7926b5a2008-10-30 10:14:35 +000049#include <plat/nand.h>
Ben Dooks9498cb72008-10-30 10:14:33 +000050#include <plat/iic.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010051#include <mach/fb.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
53#include <linux/mtd/mtd.h>
54#include <linux/mtd/nand.h>
55#include <linux/mtd/nand_ecc.h>
56#include <linux/mtd/partitions.h>
57
Ben Dooks65cc3372005-07-18 10:24:32 +010058#include <linux/serial_8250.h>
59
Ben Dooksd5120ae2008-10-07 23:09:51 +010060#include <plat/clock.h>
Ben Dooksa2b7ba92008-10-07 22:26:09 +010061#include <plat/devs.h>
62#include <plat/cpu.h>
Ben Dooksca0b4902009-07-30 23:23:39 +010063#include <plat/cpu-freq.h>
Ben Dooks40b956f2010-05-04 14:38:49 +090064#include <plat/gpio-cfg.h>
Ben Dooks4d3a3462009-11-13 22:34:20 +000065#include <plat/audio-simtec.h>
Ben Dooks9d529c62008-07-03 11:24:39 +010066
Linus Torvalds1da177e2005-04-16 15:20:36 -070067#include "usb-simtec.h"
Ben Dooks9d529c62008-07-03 11:24:39 +010068#include "nor-simtec.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070069
Ben Dooksccae9412009-11-13 22:54:14 +000070#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
72/* macros for virtual address mods for the io space entries */
73#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
74#define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
75#define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
76#define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
77
78/* macros to modify the physical addresses for io space */
79
Ben Dooks1d23b652005-11-08 19:15:31 +000080#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
81#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
82#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
83#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
Linus Torvalds1da177e2005-04-16 15:20:36 -070084
85static struct map_desc bast_iodesc[] __initdata = {
86 /* ISA IO areas */
Ben Dooks1d23b652005-11-08 19:15:31 +000087 {
88 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
89 .pfn = PA_CS2(BAST_PA_ISAIO),
90 .length = SZ_16M,
91 .type = MT_DEVICE,
92 }, {
93 .virtual = (u32)S3C24XX_VA_ISA_WORD,
94 .pfn = PA_CS3(BAST_PA_ISAIO),
95 .length = SZ_16M,
96 .type = MT_DEVICE,
97 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070098 /* bast CPLD control registers, and external interrupt controls */
Ben Dooks1d23b652005-11-08 19:15:31 +000099 {
100 .virtual = (u32)BAST_VA_CTRL1,
101 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
102 .length = SZ_1M,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = (u32)BAST_VA_CTRL2,
106 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
107 .length = SZ_1M,
108 .type = MT_DEVICE,
109 }, {
110 .virtual = (u32)BAST_VA_CTRL3,
111 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
112 .length = SZ_1M,
113 .type = MT_DEVICE,
114 }, {
115 .virtual = (u32)BAST_VA_CTRL4,
116 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
117 .length = SZ_1M,
118 .type = MT_DEVICE,
119 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120 /* PC104 IRQ mux */
Ben Dooks1d23b652005-11-08 19:15:31 +0000121 {
122 .virtual = (u32)BAST_VA_PC104_IRQREQ,
123 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
124 .length = SZ_1M,
125 .type = MT_DEVICE,
126 }, {
127 .virtual = (u32)BAST_VA_PC104_IRQRAW,
128 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
129 .length = SZ_1M,
130 .type = MT_DEVICE,
131 }, {
132 .virtual = (u32)BAST_VA_PC104_IRQMASK,
133 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
134 .length = SZ_1M,
135 .type = MT_DEVICE,
136 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137
138 /* peripheral space... one for each of fast/slow/byte/16bit */
139 /* note, ide is only decoded in word space, even though some registers
140 * are only 8bit */
141
142 /* slow, byte */
143 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
144 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146
147 /* slow, word */
148 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
149 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151
152 /* fast, byte */
153 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
154 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156
157 /* fast, word */
158 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
159 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161};
162
163#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
164#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
165#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
166
167static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
168 [0] = {
169 .name = "uclk",
170 .divisor = 1,
171 .min_baud = 0,
172 .max_baud = 0,
173 },
174 [1] = {
175 .name = "pclk",
176 .divisor = 1,
177 .min_baud = 0,
Ben Dooksb526bf22005-11-16 15:05:12 +0000178 .max_baud = 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 }
180};
181
182
Ben Dooks66a9b492006-06-18 23:04:05 +0100183static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 [0] = {
185 .hwport = 0,
186 .flags = 0,
187 .ucon = UCON,
188 .ulcon = ULCON,
189 .ufcon = UFCON,
190 .clocks = bast_serial_clocks,
Ben Dooksb526bf22005-11-16 15:05:12 +0000191 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192 },
193 [1] = {
194 .hwport = 1,
195 .flags = 0,
196 .ucon = UCON,
197 .ulcon = ULCON,
198 .ufcon = UFCON,
199 .clocks = bast_serial_clocks,
Ben Dooksb526bf22005-11-16 15:05:12 +0000200 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 },
202 /* port 2 is not actually used */
203 [2] = {
204 .hwport = 2,
205 .flags = 0,
206 .ucon = UCON,
207 .ulcon = ULCON,
208 .ufcon = UFCON,
209 .clocks = bast_serial_clocks,
Ben Dooksb526bf22005-11-16 15:05:12 +0000210 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211 }
212};
213
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214/* NAND Flash on BAST board */
215
Ben Dooks6ddc4b02008-04-16 00:06:14 +0100216#ifdef CONFIG_PM
217static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
218{
219 /* ensure that an nRESET is not generated on resume. */
Ben Dooks408c8b82010-05-04 12:49:04 +0900220 gpio_direction_output(S3C2410_GPA(21), 1);
Ben Dooks6ddc4b02008-04-16 00:06:14 +0100221 return 0;
222}
223
224static int bast_pm_resume(struct sys_device *sd)
225{
Ben Dooks40b956f2010-05-04 14:38:49 +0900226 s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
Ben Dooks6ddc4b02008-04-16 00:06:14 +0100227 return 0;
228}
229
230#else
231#define bast_pm_suspend NULL
232#define bast_pm_resume NULL
233#endif
234
235static struct sysdev_class bast_pm_sysclass = {
Ben Dooks140749e2008-04-19 13:08:43 +0100236 .name = "mach-bast",
Ben Dooks6ddc4b02008-04-16 00:06:14 +0100237 .suspend = bast_pm_suspend,
238 .resume = bast_pm_resume,
239};
240
241static struct sys_device bast_pm_sysdev = {
242 .cls = &bast_pm_sysclass,
243};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244
245static int smartmedia_map[] = { 0 };
246static int chip0_map[] = { 1 };
247static int chip1_map[] = { 2 };
248static int chip2_map[] = { 3 };
249
Ben Dooks2a3a1802009-09-28 13:59:49 +0300250static struct mtd_partition __initdata bast_default_nand_part[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251 [0] = {
252 .name = "Boot Agent",
253 .size = SZ_16K,
Ben Dooksb526bf22005-11-16 15:05:12 +0000254 .offset = 0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255 },
256 [1] = {
257 .name = "/boot",
258 .size = SZ_4M - SZ_16K,
259 .offset = SZ_16K,
260 },
261 [2] = {
262 .name = "user",
263 .offset = SZ_4M,
264 .size = MTDPART_SIZ_FULL,
265 }
266};
267
268/* the bast has 4 selectable slots for nand-flash, the three
269 * on-board chip areas, as well as the external SmartMedia
270 * slot.
271 *
272 * Note, there is no current hot-plug support for the SmartMedia
273 * socket.
274*/
275
Ben Dooks2a3a1802009-09-28 13:59:49 +0300276static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700277 [0] = {
278 .name = "SmartMedia",
279 .nr_chips = 1,
280 .nr_map = smartmedia_map,
Ben Dooksd3ef7ee2009-12-23 19:25:02 +0000281 .options = NAND_SCAN_SILENT_NODEV,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
Ben Dooksb526bf22005-11-16 15:05:12 +0000283 .partitions = bast_default_nand_part,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284 },
285 [1] = {
286 .name = "chip0",
287 .nr_chips = 1,
288 .nr_map = chip0_map,
289 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
Ben Dooksb526bf22005-11-16 15:05:12 +0000290 .partitions = bast_default_nand_part,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291 },
292 [2] = {
293 .name = "chip1",
294 .nr_chips = 1,
295 .nr_map = chip1_map,
Ben Dooksd3ef7ee2009-12-23 19:25:02 +0000296 .options = NAND_SCAN_SILENT_NODEV,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
Ben Dooksb526bf22005-11-16 15:05:12 +0000298 .partitions = bast_default_nand_part,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299 },
300 [3] = {
301 .name = "chip2",
302 .nr_chips = 1,
303 .nr_map = chip2_map,
Ben Dooksd3ef7ee2009-12-23 19:25:02 +0000304 .options = NAND_SCAN_SILENT_NODEV,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305 .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
Ben Dooksb526bf22005-11-16 15:05:12 +0000306 .partitions = bast_default_nand_part,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307 }
308};
309
310static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
311{
312 unsigned int tmp;
313
314 slot = set->nr_map[slot] & 3;
315
316 pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
317 slot, set, set->nr_map);
318
319 tmp = __raw_readb(BAST_VA_CTRL2);
320 tmp &= BAST_CPLD_CTLR2_IDERST;
321 tmp |= slot;
322 tmp |= BAST_CPLD_CTRL2_WNAND;
323
324 pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
325
326 __raw_writeb(tmp, BAST_VA_CTRL2);
327}
328
Ben Dooks2a3a1802009-09-28 13:59:49 +0300329static struct s3c2410_platform_nand __initdata bast_nand_info = {
Ben Dooksb048dbf2005-10-20 23:21:19 +0100330 .tacls = 30,
331 .twrph0 = 60,
332 .twrph1 = 60,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 .nr_sets = ARRAY_SIZE(bast_nand_sets),
334 .sets = bast_nand_sets,
335 .select_chip = bast_nand_select,
336};
337
Ben Dooksd97a6662005-06-23 21:56:47 +0100338/* DM9000 */
339
340static struct resource bast_dm9k_resource[] = {
341 [0] = {
342 .start = S3C2410_CS5 + BAST_PA_DM9000,
343 .end = S3C2410_CS5 + BAST_PA_DM9000 + 3,
Ben Dooksb526bf22005-11-16 15:05:12 +0000344 .flags = IORESOURCE_MEM,
Ben Dooksd97a6662005-06-23 21:56:47 +0100345 },
346 [1] = {
347 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
348 .end = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
Ben Dooksb526bf22005-11-16 15:05:12 +0000349 .flags = IORESOURCE_MEM,
Ben Dooksd97a6662005-06-23 21:56:47 +0100350 },
351 [2] = {
352 .start = IRQ_DM9000,
353 .end = IRQ_DM9000,
Ben Dooks9cf345e2008-07-03 11:24:22 +0100354 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
Ben Dooksd97a6662005-06-23 21:56:47 +0100355 }
356
357};
358
359/* for the moment we limit ourselves to 16bit IO until some
360 * better IO routines can be written and tested
361*/
362
Ben Dooks9f693d72005-10-12 19:58:07 +0100363static struct dm9000_plat_data bast_dm9k_platdata = {
Ben Dooksb526bf22005-11-16 15:05:12 +0000364 .flags = DM9000_PLATF_16BITONLY,
Ben Dooksd97a6662005-06-23 21:56:47 +0100365};
366
367static struct platform_device bast_device_dm9k = {
368 .name = "dm9000",
369 .id = 0,
370 .num_resources = ARRAY_SIZE(bast_dm9k_resource),
371 .resource = bast_dm9k_resource,
372 .dev = {
373 .platform_data = &bast_dm9k_platdata,
374 }
375};
376
Ben Dooks65cc3372005-07-18 10:24:32 +0100377/* serial devices */
378
379#define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
380#define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
381#define SERIAL_CLK (1843200)
382
383static struct plat_serial8250_port bast_sio_data[] = {
384 [0] = {
385 .mapbase = SERIAL_BASE + 0x2f8,
386 .irq = IRQ_PCSERIAL1,
387 .flags = SERIAL_FLAGS,
388 .iotype = UPIO_MEM,
389 .regshift = 0,
390 .uartclk = SERIAL_CLK,
391 },
392 [1] = {
393 .mapbase = SERIAL_BASE + 0x3f8,
394 .irq = IRQ_PCSERIAL2,
395 .flags = SERIAL_FLAGS,
396 .iotype = UPIO_MEM,
397 .regshift = 0,
398 .uartclk = SERIAL_CLK,
399 },
400 { }
401};
402
403static struct platform_device bast_sio = {
404 .name = "serial8250",
Russell King6df29de2005-09-08 16:04:41 +0100405 .id = PLAT8250_DEV_PLATFORM,
Ben Dooks65cc3372005-07-18 10:24:32 +0100406 .dev = {
407 .platform_data = &bast_sio_data,
408 },
409};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410
Ben Dooks1fcf8442005-08-03 19:49:16 +0100411/* we have devices on the bus which cannot work much over the
412 * standard 100KHz i2c bus frequency
413*/
414
Ben Dooks3e1b7762008-10-31 16:14:40 +0000415static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
Ben Dooks1fcf8442005-08-03 19:49:16 +0100416 .flags = 0,
417 .slave_addr = 0x10,
Daniel Silverstonec564e6a2009-03-13 13:53:46 +0000418 .frequency = 100*1000,
Ben Dooks1fcf8442005-08-03 19:49:16 +0100419};
420
Ben Dooks5ce4b1f2007-07-12 10:44:53 +0100421/* Asix AX88796 10/100 ethernet controller */
422
423static struct ax_plat_data bast_asix_platdata = {
424 .flags = AXFLG_MAC_FROMDEV,
425 .wordlength = 2,
426 .dcr_val = 0x48,
427 .rcr_val = 0x40,
428};
429
430static struct resource bast_asix_resource[] = {
431 [0] = {
432 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
433 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
434 .flags = IORESOURCE_MEM,
435 },
436 [1] = {
437 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
438 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
439 .flags = IORESOURCE_MEM,
440 },
441 [2] = {
442 .start = IRQ_ASIX,
443 .end = IRQ_ASIX,
444 .flags = IORESOURCE_IRQ
445 }
446};
447
448static struct platform_device bast_device_asix = {
449 .name = "ax88796",
450 .id = 0,
451 .num_resources = ARRAY_SIZE(bast_asix_resource),
452 .resource = bast_asix_resource,
453 .dev = {
454 .platform_data = &bast_asix_platdata
455 }
456};
457
458/* Asix AX88796 10/100 ethernet controller parallel port */
459
460static struct resource bast_asixpp_resource[] = {
461 [0] = {
462 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
463 .end = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
464 .flags = IORESOURCE_MEM,
465 }
466};
467
468static struct platform_device bast_device_axpp = {
469 .name = "ax88796-pp",
470 .id = 0,
471 .num_resources = ARRAY_SIZE(bast_asixpp_resource),
472 .resource = bast_asixpp_resource,
473};
474
475/* LCD/VGA controller */
Ben Dooks58c8d572005-10-28 15:31:46 +0100476
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700477static struct s3c2410fb_display __initdata bast_lcd_info[] = {
478 {
Krzysztof Helt1f411532007-10-16 01:28:57 -0700479 .type = S3C2410_LCDCON1_TFT,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700480 .width = 640,
481 .height = 480,
Krzysztof Helt5f20f692007-10-16 01:28:59 -0700482
Krzysztof Helt69816692007-10-16 01:29:06 -0700483 .pixclock = 33333,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700484 .xres = 640,
485 .yres = 480,
486 .bpp = 4,
Krzysztof Helt1f411532007-10-16 01:28:57 -0700487 .left_margin = 40,
488 .right_margin = 20,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700489 .hsync_len = 88,
Krzysztof Helt5f20f692007-10-16 01:28:59 -0700490 .upper_margin = 30,
491 .lower_margin = 32,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700492 .vsync_len = 3,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700493
Krzysztof Heltf28ef572007-10-16 01:28:58 -0700494 .lcdcon5 = 0x00014b02,
Ben Dooks58c8d572005-10-28 15:31:46 +0100495 },
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700496 {
Krzysztof Helt1f411532007-10-16 01:28:57 -0700497 .type = S3C2410_LCDCON1_TFT,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700498 .width = 640,
499 .height = 480,
Ben Dooks58c8d572005-10-28 15:31:46 +0100500
Krzysztof Helt69816692007-10-16 01:29:06 -0700501 .pixclock = 33333,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700502 .xres = 640,
503 .yres = 480,
504 .bpp = 8,
Krzysztof Helt1f411532007-10-16 01:28:57 -0700505 .left_margin = 40,
506 .right_margin = 20,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700507 .hsync_len = 88,
Krzysztof Helt5f20f692007-10-16 01:28:59 -0700508 .upper_margin = 30,
509 .lower_margin = 32,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700510 .vsync_len = 3,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700511
Krzysztof Heltf28ef572007-10-16 01:28:58 -0700512 .lcdcon5 = 0x00014b02,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700513 },
514 {
Krzysztof Helt1f411532007-10-16 01:28:57 -0700515 .type = S3C2410_LCDCON1_TFT,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700516 .width = 640,
517 .height = 480,
518
Krzysztof Helt69816692007-10-16 01:29:06 -0700519 .pixclock = 33333,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700520 .xres = 640,
521 .yres = 480,
522 .bpp = 16,
Krzysztof Helt1f411532007-10-16 01:28:57 -0700523 .left_margin = 40,
524 .right_margin = 20,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700525 .hsync_len = 88,
Krzysztof Helt5f20f692007-10-16 01:28:59 -0700526 .upper_margin = 30,
527 .lower_margin = 32,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700528 .vsync_len = 3,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700529
Krzysztof Heltf28ef572007-10-16 01:28:58 -0700530 .lcdcon5 = 0x00014b02,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700531 },
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700532};
533
534/* LCD/VGA controller */
535
536static struct s3c2410fb_mach_info __initdata bast_fb_info = {
537
538 .displays = bast_lcd_info,
539 .num_displays = ARRAY_SIZE(bast_lcd_info),
Ben Dooks9cbae122007-12-23 03:09:38 +0100540 .default_display = 1,
Ben Dooks58c8d572005-10-28 15:31:46 +0100541};
542
Ben Dooks042cf0f2008-07-03 11:24:41 +0100543/* I2C devices fitted. */
544
545static struct i2c_board_info bast_i2c_devs[] __initdata = {
546 {
547 I2C_BOARD_INFO("tlv320aic23", 0x1a),
548 }, {
549 I2C_BOARD_INFO("simtec-pmu", 0x6b),
550 }, {
551 I2C_BOARD_INFO("ch7013", 0x75),
552 },
553};
Ben Dooksb7a12d12008-07-03 11:24:37 +0100554
Ben Dooks885f9eb2009-07-18 10:12:26 +0100555static struct s3c_hwmon_pdata bast_hwmon_info = {
556 /* LCD contrast (0-6.6V) */
557 .in[0] = &(struct s3c_hwmon_chcfg) {
558 .name = "lcd-contrast",
559 .mult = 3300,
560 .div = 512,
561 },
562 /* LED current feedback */
563 .in[1] = &(struct s3c_hwmon_chcfg) {
564 .name = "led-feedback",
565 .mult = 3300,
566 .div = 1024,
567 },
568 /* LCD feedback (0-6.6V) */
569 .in[2] = &(struct s3c_hwmon_chcfg) {
570 .name = "lcd-feedback",
571 .mult = 3300,
572 .div = 512,
573 },
574 /* Vcore (1.8-2.0V), Vref 3.3V */
575 .in[3] = &(struct s3c_hwmon_chcfg) {
576 .name = "vcore",
577 .mult = 3300,
578 .div = 1024,
579 },
580};
581
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582/* Standard BAST devices */
Ben Dooks885f9eb2009-07-18 10:12:26 +0100583// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584
585static struct platform_device *bast_devices[] __initdata = {
Ben Dooksb8132482009-11-23 00:13:39 +0000586 &s3c_device_ohci,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700587 &s3c_device_lcd,
588 &s3c_device_wdt,
Ben Dooks3e1b7762008-10-31 16:14:40 +0000589 &s3c_device_i2c0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590 &s3c_device_rtc,
591 &s3c_device_nand,
Ben Dooks885f9eb2009-07-18 10:12:26 +0100592 &s3c_device_adc,
593 &s3c_device_hwmon,
Ben Dooksd97a6662005-06-23 21:56:47 +0100594 &bast_device_dm9k,
Ben Dooks5ce4b1f2007-07-12 10:44:53 +0100595 &bast_device_asix,
596 &bast_device_axpp,
Ben Dooks65cc3372005-07-18 10:24:32 +0100597 &bast_sio,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598};
599
Ben Dooks2bc75092008-07-15 17:17:48 +0100600static struct clk *bast_clocks[] __initdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700601 &s3c24xx_dclk0,
602 &s3c24xx_dclk1,
603 &s3c24xx_clkout0,
604 &s3c24xx_clkout1,
605 &s3c24xx_uclk,
606};
607
Ben Dooksca0b4902009-07-30 23:23:39 +0100608static struct s3c_cpufreq_board __initdata bast_cpufreq = {
609 .refresh = 7800, /* 7.8usec */
610 .auto_io = 1,
611 .need_io = 1,
612};
613
Ben Dooks4d3a3462009-11-13 22:34:20 +0000614static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
615 .have_mic = 1,
616 .have_lout = 1,
617};
618
Ben Dooks5fe10ab2005-09-20 17:24:33 +0100619static void __init bast_map_io(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700620{
621 /* initialise the clocks */
622
Ben Dooksd96a9802008-04-16 00:12:39 +0100623 s3c24xx_dclk0.parent = &clk_upll;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624 s3c24xx_dclk0.rate = 12*1000*1000;
625
Ben Dooksd96a9802008-04-16 00:12:39 +0100626 s3c24xx_dclk1.parent = &clk_upll;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 s3c24xx_dclk1.rate = 24*1000*1000;
628
629 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
630 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
631
632 s3c24xx_uclk.parent = &s3c24xx_clkout1;
633
Ben Dooksce89c202007-04-20 11:15:27 +0100634 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
635
Maurus Cuelenaere6cd82ff2010-05-04 13:12:32 +0200636 s3c_hwmon_set_platdata(&bast_hwmon_info);
Ben Dooks3e1b7762008-10-31 16:14:40 +0000637
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
639 s3c24xx_init_clocks(0);
640 s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641}
642
Ben Dooks58c8d572005-10-28 15:31:46 +0100643static void __init bast_init(void)
644{
Ben Dooks6ddc4b02008-04-16 00:06:14 +0100645 sysdev_class_register(&bast_pm_sysclass);
646 sysdev_register(&bast_pm_sysdev);
647
Ben Dooksa8af6de2009-05-15 14:57:09 +0100648 s3c_i2c0_set_platdata(&bast_i2c_info);
Ben Dooks2a3a1802009-09-28 13:59:49 +0300649 s3c_nand_set_platdata(&bast_nand_info);
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700650 s3c24xx_fb_set_platdata(&bast_fb_info);
Ben Dooks57e51712007-04-20 11:19:16 +0100651 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
Ben Dooks9d529c62008-07-03 11:24:39 +0100652
Ben Dooks042cf0f2008-07-03 11:24:41 +0100653 i2c_register_board_info(0, bast_i2c_devs,
654 ARRAY_SIZE(bast_i2c_devs));
655
Ben Dooks7a05a2c2009-05-18 20:15:01 +0100656 usb_simtec_init();
Ben Dooks9d529c62008-07-03 11:24:39 +0100657 nor_simtec_init();
Ben Dooks4d3a3462009-11-13 22:34:20 +0000658 simtec_audio_add(NULL, true, &bast_audio);
Ben Dooksca0b4902009-07-30 23:23:39 +0100659
Ben Dooks408c8b82010-05-04 12:49:04 +0900660 WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
661
Ben Dooksca0b4902009-07-30 23:23:39 +0100662 s3c_cpufreq_setboard(&bast_cpufreq);
Ben Dooks58c8d572005-10-28 15:31:46 +0100663}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664
665MACHINE_START(BAST, "Simtec-BAST")
Russell Kinge9dea0c2005-07-03 17:38:58 +0100666 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
Russell Kinge9dea0c2005-07-03 17:38:58 +0100667 .boot_params = S3C2410_SDRAM_PA + 0x100,
Ben Dooksf705b1a2005-06-29 11:09:15 +0100668 .map_io = bast_map_io,
669 .init_irq = s3c24xx_init_irq,
Ben Dooks58c8d572005-10-28 15:31:46 +0100670 .init_machine = bast_init,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671 .timer = &s3c24xx_timer,
672MACHINE_END