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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * Copyright (C) 2001 Ralf Baechle
Maciej W. Rozycki925ddb02005-02-03 23:06:29 +00006 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
7 * Author: Maciej W. Rozycki <macro@mips.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * This file define the irq handler for MIPS CPU interrupts.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17/*
18 * Almost all MIPS CPUs define 8 interrupt sources. They are typically
19 * level triggered (i.e., cannot be cleared from CPU; must be cleared from
20 * device). The first two are software interrupts which we don't really
21 * use or support. The last one is usually the CPU timer interrupt if
22 * counter register is present or, for CPUs with an external FPU, by
23 * convention it's the FPU exception interrupt.
24 *
25 * Don't even think about using this on SMP. You have been warned.
26 *
27 * This file exports one global function:
Atsushi Nemoto97dcb822007-01-08 02:14:29 +090028 * void mips_cpu_irq_init(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 */
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/kernel.h>
33
34#include <asm/irq_cpu.h>
35#include <asm/mipsregs.h>
Ralf Baechled03d0a52005-08-17 13:44:26 +000036#include <asm/mipsmtregs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037#include <asm/system.h>
38
Linus Torvalds1da177e2005-04-16 15:20:36 -070039static inline void unmask_mips_irq(unsigned int irq)
40{
Atsushi Nemoto97dcb822007-01-08 02:14:29 +090041 set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
Ralf Baechle569f75b2005-07-13 18:20:33 +000042 irq_enable_hazard();
Linus Torvalds1da177e2005-04-16 15:20:36 -070043}
44
45static inline void mask_mips_irq(unsigned int irq)
46{
Atsushi Nemoto97dcb822007-01-08 02:14:29 +090047 clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
Ralf Baechle569f75b2005-07-13 18:20:33 +000048 irq_disable_hazard();
Linus Torvalds1da177e2005-04-16 15:20:36 -070049}
50
Ralf Baechle94dee172006-07-02 14:41:42 +010051static struct irq_chip mips_cpu_irq_controller = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +090052 .name = "MIPS",
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +090053 .ack = mask_mips_irq,
54 .mask = mask_mips_irq,
55 .mask_ack = mask_mips_irq,
56 .unmask = unmask_mips_irq,
Atsushi Nemoto14178362006-11-14 01:13:18 +090057 .eoi = unmask_mips_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -070058};
59
Ralf Baechled03d0a52005-08-17 13:44:26 +000060/*
61 * Basically the same as above but taking care of all the MT stuff
62 */
63
64#define unmask_mips_mt_irq unmask_mips_irq
65#define mask_mips_mt_irq mask_mips_irq
Ralf Baechled03d0a52005-08-17 13:44:26 +000066
67static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
68{
69 unsigned int vpflags = dvpe();
70
Atsushi Nemoto97dcb822007-01-08 02:14:29 +090071 clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
Ralf Baechled03d0a52005-08-17 13:44:26 +000072 evpe(vpflags);
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +090073 unmask_mips_mt_irq(irq);
Ralf Baechled03d0a52005-08-17 13:44:26 +000074
75 return 0;
76}
77
Ralf Baechled03d0a52005-08-17 13:44:26 +000078/*
79 * While we ack the interrupt interrupts are disabled and thus we don't need
80 * to deal with concurrency issues. Same for mips_cpu_irq_end.
81 */
82static void mips_mt_cpu_irq_ack(unsigned int irq)
83{
84 unsigned int vpflags = dvpe();
Atsushi Nemoto97dcb822007-01-08 02:14:29 +090085 clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
Ralf Baechled03d0a52005-08-17 13:44:26 +000086 evpe(vpflags);
87 mask_mips_mt_irq(irq);
88}
89
Ralf Baechle94dee172006-07-02 14:41:42 +010090static struct irq_chip mips_mt_cpu_irq_controller = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +090091 .name = "MIPS",
Ralf Baechled03d0a52005-08-17 13:44:26 +000092 .startup = mips_mt_cpu_irq_startup,
Ralf Baechled03d0a52005-08-17 13:44:26 +000093 .ack = mips_mt_cpu_irq_ack,
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +090094 .mask = mask_mips_mt_irq,
95 .mask_ack = mips_mt_cpu_irq_ack,
96 .unmask = unmask_mips_mt_irq,
Atsushi Nemoto14178362006-11-14 01:13:18 +090097 .eoi = unmask_mips_mt_irq,
Ralf Baechled03d0a52005-08-17 13:44:26 +000098};
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
Atsushi Nemoto97dcb822007-01-08 02:14:29 +0900100void __init mips_cpu_irq_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101{
Atsushi Nemoto97dcb822007-01-08 02:14:29 +0900102 int irq_base = MIPS_CPU_IRQ_BASE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103 int i;
104
Maciej W. Rozycki925ddb02005-02-03 23:06:29 +0000105 /* Mask interrupts. */
106 clear_c0_status(ST0_IM);
107 clear_c0_cause(CAUSEF_IP);
108
Ralf Baechled03d0a52005-08-17 13:44:26 +0000109 /*
110 * Only MT is using the software interrupts currently, so we just
111 * leave them uninitialized for other processors.
112 */
113 if (cpu_has_mipsmt)
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +0900114 for (i = irq_base; i < irq_base + 2; i++)
115 set_irq_chip(i, &mips_mt_cpu_irq_controller);
Ralf Baechled03d0a52005-08-17 13:44:26 +0000116
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +0900117 for (i = irq_base + 2; i < irq_base + 8; i++)
Atsushi Nemoto14178362006-11-14 01:13:18 +0900118 set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
119 handle_level_irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120}