blob: e535cd13f7cc7255f9210d0922de59a69c2ad9a5 [file] [log] [blame]
Zhang Wei173acc72008-03-01 07:42:48 -07001/*
2 * Freescale MPC85xx, MPC83xx DMA Engine support
3 *
Li Yange2c8e4252010-11-11 20:16:29 +08004 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
Zhang Wei173acc72008-03-01 07:42:48 -07005 *
6 * Author:
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9 *
10 * Description:
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
Stefan Weilc2e07b32010-08-03 19:44:52 +020013 * The support for MPC8349 DMA controller is also added.
Zhang Wei173acc72008-03-01 07:42:48 -070014 *
Ira W. Snydera7aea372009-04-23 16:17:54 -070015 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
18 * on some platforms.
19 *
Zhang Wei173acc72008-03-01 07:42:48 -070020 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/pci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Zhang Wei173acc72008-03-01 07:42:48 -070031#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmapool.h>
36#include <linux/of_platform.h>
37
38#include "fsldma.h"
39
Ira Snyderb1584712011-03-03 07:54:55 +000040#define chan_dbg(chan, fmt, arg...) \
41 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
42#define chan_err(chan, fmt, arg...) \
43 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
44
45static const char msg_ld_oom[] = "No free memory for link descriptor";
Ira Snyderc14330412010-09-30 11:46:45 +000046
Ira Snydere8bd84d2011-03-03 07:54:54 +000047/*
48 * Register Helpers
49 */
Zhang Wei173acc72008-03-01 07:42:48 -070050
Ira Snydera1c03312010-01-06 13:34:05 +000051static void set_sr(struct fsldma_chan *chan, u32 val)
Zhang Wei173acc72008-03-01 07:42:48 -070052{
Ira Snydera1c03312010-01-06 13:34:05 +000053 DMA_OUT(chan, &chan->regs->sr, val, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070054}
55
Ira Snydera1c03312010-01-06 13:34:05 +000056static u32 get_sr(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070057{
Ira Snydera1c03312010-01-06 13:34:05 +000058 return DMA_IN(chan, &chan->regs->sr, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070059}
60
Ira Snydere8bd84d2011-03-03 07:54:54 +000061static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
62{
63 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
64}
65
66static dma_addr_t get_cdar(struct fsldma_chan *chan)
67{
68 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
69}
70
71static dma_addr_t get_ndar(struct fsldma_chan *chan)
72{
73 return DMA_IN(chan, &chan->regs->ndar, 64);
74}
75
76static u32 get_bcr(struct fsldma_chan *chan)
77{
78 return DMA_IN(chan, &chan->regs->bcr, 32);
79}
80
81/*
82 * Descriptor Helpers
83 */
84
Ira Snydera1c03312010-01-06 13:34:05 +000085static void set_desc_cnt(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -070086 struct fsl_dma_ld_hw *hw, u32 count)
87{
Ira Snydera1c03312010-01-06 13:34:05 +000088 hw->count = CPU_TO_DMA(chan, count, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070089}
90
Ira Snydera1c03312010-01-06 13:34:05 +000091static void set_desc_src(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -070092 struct fsl_dma_ld_hw *hw, dma_addr_t src)
93{
94 u64 snoop_bits;
95
Ira Snydera1c03312010-01-06 13:34:05 +000096 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
Zhang Wei173acc72008-03-01 07:42:48 -070097 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
Ira Snydera1c03312010-01-06 13:34:05 +000098 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
Zhang Wei173acc72008-03-01 07:42:48 -070099}
100
Ira Snydera1c03312010-01-06 13:34:05 +0000101static void set_desc_dst(struct fsldma_chan *chan,
Ira Snyder738f5f72010-01-06 13:34:02 +0000102 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
Zhang Wei173acc72008-03-01 07:42:48 -0700103{
104 u64 snoop_bits;
105
Ira Snydera1c03312010-01-06 13:34:05 +0000106 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
Zhang Wei173acc72008-03-01 07:42:48 -0700107 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
Ira Snydera1c03312010-01-06 13:34:05 +0000108 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700109}
110
Ira Snydera1c03312010-01-06 13:34:05 +0000111static void set_desc_next(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -0700112 struct fsl_dma_ld_hw *hw, dma_addr_t next)
113{
114 u64 snoop_bits;
115
Ira Snydera1c03312010-01-06 13:34:05 +0000116 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
Zhang Wei173acc72008-03-01 07:42:48 -0700117 ? FSL_DMA_SNEN : 0;
Ira Snydera1c03312010-01-06 13:34:05 +0000118 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700119}
120
Ira Snydere8bd84d2011-03-03 07:54:54 +0000121static void set_ld_eol(struct fsldma_chan *chan,
122 struct fsl_desc_sw *desc)
Zhang Wei173acc72008-03-01 07:42:48 -0700123{
Ira Snydere8bd84d2011-03-03 07:54:54 +0000124 u64 snoop_bits;
125
126 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
127 ? FSL_DMA_SNEN : 0;
128
129 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
130 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
131 | snoop_bits, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700132}
133
Ira Snydere8bd84d2011-03-03 07:54:54 +0000134/*
135 * DMA Engine Hardware Control Helpers
136 */
Zhang Wei173acc72008-03-01 07:42:48 -0700137
Ira Snydere8bd84d2011-03-03 07:54:54 +0000138static void dma_init(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700139{
Ira Snydere8bd84d2011-03-03 07:54:54 +0000140 /* Reset the channel */
141 DMA_OUT(chan, &chan->regs->mr, 0, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700142
Ira Snydere8bd84d2011-03-03 07:54:54 +0000143 switch (chan->feature & FSL_DMA_IP_MASK) {
144 case FSL_DMA_IP_85XX:
145 /* Set the channel to below modes:
146 * EIE - Error interrupt enable
147 * EOSIE - End of segments interrupt enable (basic mode)
148 * EOLNIE - End of links interrupt enable
149 * BWC - Bandwidth sharing among channels
150 */
151 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
152 | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE
153 | FSL_DMA_MR_EOSIE, 32);
154 break;
155 case FSL_DMA_IP_83XX:
156 /* Set the channel to below modes:
157 * EOTIE - End-of-transfer interrupt enable
158 * PRC_RM - PCI read multiple
159 */
160 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
161 | FSL_DMA_MR_PRC_RM, 32);
162 break;
163 }
Zhang Weif79abb62008-03-18 18:45:00 -0700164}
165
Ira Snydera1c03312010-01-06 13:34:05 +0000166static int dma_is_idle(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700167{
Ira Snydera1c03312010-01-06 13:34:05 +0000168 u32 sr = get_sr(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700169 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
170}
171
Ira Snydera1c03312010-01-06 13:34:05 +0000172static void dma_start(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700173{
Ira Snyder272ca652010-01-06 13:33:59 +0000174 u32 mode;
Zhang Wei173acc72008-03-01 07:42:48 -0700175
Ira Snydera1c03312010-01-06 13:34:05 +0000176 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000177
Ira Snydera1c03312010-01-06 13:34:05 +0000178 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
179 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
180 DMA_OUT(chan, &chan->regs->bcr, 0, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000181 mode |= FSL_DMA_MR_EMP_EN;
182 } else {
183 mode &= ~FSL_DMA_MR_EMP_EN;
184 }
Ira Snyder43a1a3e2009-05-28 09:26:40 +0000185 }
Zhang Wei173acc72008-03-01 07:42:48 -0700186
Ira Snydera1c03312010-01-06 13:34:05 +0000187 if (chan->feature & FSL_DMA_CHAN_START_EXT)
Ira Snyder272ca652010-01-06 13:33:59 +0000188 mode |= FSL_DMA_MR_EMS_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700189 else
Ira Snyder272ca652010-01-06 13:33:59 +0000190 mode |= FSL_DMA_MR_CS;
Zhang Wei173acc72008-03-01 07:42:48 -0700191
Ira Snydera1c03312010-01-06 13:34:05 +0000192 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700193}
194
Ira Snydera1c03312010-01-06 13:34:05 +0000195static void dma_halt(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700196{
Ira Snyder272ca652010-01-06 13:33:59 +0000197 u32 mode;
Dan Williams900325a2009-03-02 15:33:46 -0700198 int i;
199
Ira Snydera1c03312010-01-06 13:34:05 +0000200 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000201 mode |= FSL_DMA_MR_CA;
Ira Snydera1c03312010-01-06 13:34:05 +0000202 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000203
204 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA);
Ira Snydera1c03312010-01-06 13:34:05 +0000205 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700206
Dan Williams900325a2009-03-02 15:33:46 -0700207 for (i = 0; i < 100; i++) {
Ira Snydera1c03312010-01-06 13:34:05 +0000208 if (dma_is_idle(chan))
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000209 return;
210
Zhang Wei173acc72008-03-01 07:42:48 -0700211 udelay(10);
Dan Williams900325a2009-03-02 15:33:46 -0700212 }
Ira Snyder272ca652010-01-06 13:33:59 +0000213
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000214 if (!dma_is_idle(chan))
Ira Snyderb1584712011-03-03 07:54:55 +0000215 chan_err(chan, "DMA halt timeout!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700216}
217
Zhang Wei173acc72008-03-01 07:42:48 -0700218/**
219 * fsl_chan_set_src_loop_size - Set source address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000220 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700221 * @size : Address loop size, 0 for disable loop
222 *
223 * The set source address hold transfer size. The source
224 * address hold or loop transfer size is when the DMA transfer
225 * data from source address (SA), if the loop size is 4, the DMA will
226 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
227 * SA + 1 ... and so on.
228 */
Ira Snydera1c03312010-01-06 13:34:05 +0000229static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700230{
Ira Snyder272ca652010-01-06 13:33:59 +0000231 u32 mode;
232
Ira Snydera1c03312010-01-06 13:34:05 +0000233 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000234
Zhang Wei173acc72008-03-01 07:42:48 -0700235 switch (size) {
236 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000237 mode &= ~FSL_DMA_MR_SAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700238 break;
239 case 1:
240 case 2:
241 case 4:
242 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000243 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
Zhang Wei173acc72008-03-01 07:42:48 -0700244 break;
245 }
Ira Snyder272ca652010-01-06 13:33:59 +0000246
Ira Snydera1c03312010-01-06 13:34:05 +0000247 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700248}
249
250/**
Ira Snyder738f5f72010-01-06 13:34:02 +0000251 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000252 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700253 * @size : Address loop size, 0 for disable loop
254 *
255 * The set destination address hold transfer size. The destination
256 * address hold or loop transfer size is when the DMA transfer
257 * data to destination address (TA), if the loop size is 4, the DMA will
258 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
259 * TA + 1 ... and so on.
260 */
Ira Snydera1c03312010-01-06 13:34:05 +0000261static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700262{
Ira Snyder272ca652010-01-06 13:33:59 +0000263 u32 mode;
264
Ira Snydera1c03312010-01-06 13:34:05 +0000265 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000266
Zhang Wei173acc72008-03-01 07:42:48 -0700267 switch (size) {
268 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000269 mode &= ~FSL_DMA_MR_DAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700270 break;
271 case 1:
272 case 2:
273 case 4:
274 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000275 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
Zhang Wei173acc72008-03-01 07:42:48 -0700276 break;
277 }
Ira Snyder272ca652010-01-06 13:33:59 +0000278
Ira Snydera1c03312010-01-06 13:34:05 +0000279 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700280}
281
282/**
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700283 * fsl_chan_set_request_count - Set DMA Request Count for external control
Ira Snydera1c03312010-01-06 13:34:05 +0000284 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700285 * @size : Number of bytes to transfer in a single request
286 *
287 * The Freescale DMA channel can be controlled by the external signal DREQ#.
288 * The DMA request count is how many bytes are allowed to transfer before
289 * pausing the channel, after which a new assertion of DREQ# resumes channel
290 * operation.
291 *
292 * A size of 0 disables external pause control. The maximum size is 1024.
293 */
Ira Snydera1c03312010-01-06 13:34:05 +0000294static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700295{
Ira Snyder272ca652010-01-06 13:33:59 +0000296 u32 mode;
297
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700298 BUG_ON(size > 1024);
Ira Snyder272ca652010-01-06 13:33:59 +0000299
Ira Snydera1c03312010-01-06 13:34:05 +0000300 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000301 mode |= (__ilog2(size) << 24) & 0x0f000000;
302
Ira Snydera1c03312010-01-06 13:34:05 +0000303 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700304}
305
306/**
Zhang Wei173acc72008-03-01 07:42:48 -0700307 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
Ira Snydera1c03312010-01-06 13:34:05 +0000308 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700309 * @enable : 0 is disabled, 1 is enabled.
Zhang Wei173acc72008-03-01 07:42:48 -0700310 *
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700311 * The Freescale DMA channel can be controlled by the external signal DREQ#.
312 * The DMA Request Count feature should be used in addition to this feature
313 * to set the number of bytes to transfer before pausing the channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700314 */
Ira Snydera1c03312010-01-06 13:34:05 +0000315static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700316{
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700317 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000318 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700319 else
Ira Snydera1c03312010-01-06 13:34:05 +0000320 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700321}
322
323/**
324 * fsl_chan_toggle_ext_start - Toggle channel external start status
Ira Snydera1c03312010-01-06 13:34:05 +0000325 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700326 * @enable : 0 is disabled, 1 is enabled.
327 *
328 * If enable the external start, the channel can be started by an
329 * external DMA start pin. So the dma_start() does not start the
330 * transfer immediately. The DMA channel will wait for the
331 * control pin asserted.
332 */
Ira Snydera1c03312010-01-06 13:34:05 +0000333static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700334{
335 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000336 chan->feature |= FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700337 else
Ira Snydera1c03312010-01-06 13:34:05 +0000338 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700339}
340
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000341static void append_ld_queue(struct fsldma_chan *chan,
342 struct fsl_desc_sw *desc)
343{
344 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
345
346 if (list_empty(&chan->ld_pending))
347 goto out_splice;
348
349 /*
350 * Add the hardware descriptor to the chain of hardware descriptors
351 * that already exists in memory.
352 *
353 * This will un-set the EOL bit of the existing transaction, and the
354 * last link in this transaction will become the EOL descriptor.
355 */
356 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
357
358 /*
359 * Add the software descriptor and all children to the list
360 * of pending transactions
361 */
362out_splice:
363 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
364}
365
Zhang Wei173acc72008-03-01 07:42:48 -0700366static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
367{
Ira Snydera1c03312010-01-06 13:34:05 +0000368 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
Dan Williamseda34232009-09-08 17:53:02 -0700369 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
370 struct fsl_desc_sw *child;
Zhang Wei173acc72008-03-01 07:42:48 -0700371 unsigned long flags;
372 dma_cookie_t cookie;
373
Ira Snydera1c03312010-01-06 13:34:05 +0000374 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700375
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000376 /*
377 * assign cookies to all of the software descriptors
378 * that make up this transaction
379 */
Ira Snydera1c03312010-01-06 13:34:05 +0000380 cookie = chan->common.cookie;
Dan Williamseda34232009-09-08 17:53:02 -0700381 list_for_each_entry(child, &desc->tx_list, node) {
Ira Snyderbcfb7462009-05-15 14:27:16 -0700382 cookie++;
383 if (cookie < 0)
384 cookie = 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700385
Steven J. Magnani6ca3a7a2010-02-25 13:39:30 -0600386 child->async_tx.cookie = cookie;
Ira Snyderbcfb7462009-05-15 14:27:16 -0700387 }
388
Ira Snydera1c03312010-01-06 13:34:05 +0000389 chan->common.cookie = cookie;
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000390
391 /* put this transaction onto the tail of the pending queue */
Ira Snydera1c03312010-01-06 13:34:05 +0000392 append_ld_queue(chan, desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700393
Ira Snydera1c03312010-01-06 13:34:05 +0000394 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700395
396 return cookie;
397}
398
399/**
400 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
Ira Snydera1c03312010-01-06 13:34:05 +0000401 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700402 *
403 * Return - The descriptor allocated. NULL for failed.
404 */
405static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
Ira Snydera1c03312010-01-06 13:34:05 +0000406 struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700407{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000408 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700409 dma_addr_t pdesc;
Zhang Wei173acc72008-03-01 07:42:48 -0700410
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000411 desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
412 if (!desc) {
Ira Snyderb1584712011-03-03 07:54:55 +0000413 chan_dbg(chan, "out of memory for link descriptor\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000414 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700415 }
416
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000417 memset(desc, 0, sizeof(*desc));
418 INIT_LIST_HEAD(&desc->tx_list);
419 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
420 desc->async_tx.tx_submit = fsl_dma_tx_submit;
421 desc->async_tx.phys = pdesc;
422
423 return desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700424}
425
426
427/**
428 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000429 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700430 *
431 * This function will create a dma pool for descriptor allocation.
432 *
433 * Return - The number of descriptors allocated.
434 */
Ira Snydera1c03312010-01-06 13:34:05 +0000435static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700436{
Ira Snydera1c03312010-01-06 13:34:05 +0000437 struct fsldma_chan *chan = to_fsl_chan(dchan);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700438
439 /* Has this channel already been allocated? */
Ira Snydera1c03312010-01-06 13:34:05 +0000440 if (chan->desc_pool)
Timur Tabi77cd62e2008-09-26 17:00:11 -0700441 return 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700442
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000443 /*
444 * We need the descriptor to be aligned to 32bytes
Zhang Wei173acc72008-03-01 07:42:48 -0700445 * for meeting FSL DMA specification requirement.
446 */
Ira Snyderb1584712011-03-03 07:54:55 +0000447 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000448 sizeof(struct fsl_desc_sw),
449 __alignof__(struct fsl_desc_sw), 0);
Ira Snydera1c03312010-01-06 13:34:05 +0000450 if (!chan->desc_pool) {
Ira Snyderb1584712011-03-03 07:54:55 +0000451 chan_err(chan, "unable to allocate descriptor pool\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000452 return -ENOMEM;
Zhang Wei173acc72008-03-01 07:42:48 -0700453 }
454
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000455 /* there is at least one descriptor free to be allocated */
Zhang Wei173acc72008-03-01 07:42:48 -0700456 return 1;
457}
458
459/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000460 * fsldma_free_desc_list - Free all descriptors in a queue
461 * @chan: Freescae DMA channel
462 * @list: the list to free
463 *
464 * LOCKING: must hold chan->desc_lock
465 */
466static void fsldma_free_desc_list(struct fsldma_chan *chan,
467 struct list_head *list)
468{
469 struct fsl_desc_sw *desc, *_desc;
470
471 list_for_each_entry_safe(desc, _desc, list, node) {
472 list_del(&desc->node);
473 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
474 }
475}
476
477static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
478 struct list_head *list)
479{
480 struct fsl_desc_sw *desc, *_desc;
481
482 list_for_each_entry_safe_reverse(desc, _desc, list, node) {
483 list_del(&desc->node);
484 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
485 }
486}
487
488/**
Zhang Wei173acc72008-03-01 07:42:48 -0700489 * fsl_dma_free_chan_resources - Free all resources of the channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000490 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700491 */
Ira Snydera1c03312010-01-06 13:34:05 +0000492static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700493{
Ira Snydera1c03312010-01-06 13:34:05 +0000494 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700495 unsigned long flags;
496
Ira Snyderb1584712011-03-03 07:54:55 +0000497 chan_dbg(chan, "free all channel resources\n");
Ira Snydera1c03312010-01-06 13:34:05 +0000498 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000499 fsldma_free_desc_list(chan, &chan->ld_pending);
500 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snydera1c03312010-01-06 13:34:05 +0000501 spin_unlock_irqrestore(&chan->desc_lock, flags);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700502
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000503 dma_pool_destroy(chan->desc_pool);
Ira Snydera1c03312010-01-06 13:34:05 +0000504 chan->desc_pool = NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700505}
506
Zhang Wei2187c262008-03-13 17:45:28 -0700507static struct dma_async_tx_descriptor *
Ira Snydera1c03312010-01-06 13:34:05 +0000508fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
Zhang Wei2187c262008-03-13 17:45:28 -0700509{
Ira Snydera1c03312010-01-06 13:34:05 +0000510 struct fsldma_chan *chan;
Zhang Wei2187c262008-03-13 17:45:28 -0700511 struct fsl_desc_sw *new;
512
Ira Snydera1c03312010-01-06 13:34:05 +0000513 if (!dchan)
Zhang Wei2187c262008-03-13 17:45:28 -0700514 return NULL;
515
Ira Snydera1c03312010-01-06 13:34:05 +0000516 chan = to_fsl_chan(dchan);
Zhang Wei2187c262008-03-13 17:45:28 -0700517
Ira Snydera1c03312010-01-06 13:34:05 +0000518 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei2187c262008-03-13 17:45:28 -0700519 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000520 chan_err(chan, "%s\n", msg_ld_oom);
Zhang Wei2187c262008-03-13 17:45:28 -0700521 return NULL;
522 }
523
524 new->async_tx.cookie = -EBUSY;
Dan Williams636bdea2008-04-17 20:17:26 -0700525 new->async_tx.flags = flags;
Zhang Wei2187c262008-03-13 17:45:28 -0700526
Zhang Weif79abb62008-03-18 18:45:00 -0700527 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700528 list_add_tail(&new->node, &new->tx_list);
Zhang Weif79abb62008-03-18 18:45:00 -0700529
Zhang Wei2187c262008-03-13 17:45:28 -0700530 /* Set End-of-link to the last link descriptor of new list*/
Ira Snydera1c03312010-01-06 13:34:05 +0000531 set_ld_eol(chan, new);
Zhang Wei2187c262008-03-13 17:45:28 -0700532
533 return &new->async_tx;
534}
535
Zhang Wei173acc72008-03-01 07:42:48 -0700536static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
Ira Snydera1c03312010-01-06 13:34:05 +0000537 struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src,
Zhang Wei173acc72008-03-01 07:42:48 -0700538 size_t len, unsigned long flags)
539{
Ira Snydera1c03312010-01-06 13:34:05 +0000540 struct fsldma_chan *chan;
Zhang Wei173acc72008-03-01 07:42:48 -0700541 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
542 size_t copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700543
Ira Snydera1c03312010-01-06 13:34:05 +0000544 if (!dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700545 return NULL;
546
547 if (!len)
548 return NULL;
549
Ira Snydera1c03312010-01-06 13:34:05 +0000550 chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700551
552 do {
553
554 /* Allocate the link descriptor from DMA pool */
Ira Snydera1c03312010-01-06 13:34:05 +0000555 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700556 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000557 chan_err(chan, "%s\n", msg_ld_oom);
Ira Snyder2e077f82009-05-15 09:59:46 -0700558 goto fail;
Zhang Wei173acc72008-03-01 07:42:48 -0700559 }
560#ifdef FSL_DMA_LD_DEBUG
Ira Snyderb1584712011-03-03 07:54:55 +0000561 chan_dbg(chan, "new link desc alloc %p\n", new);
Zhang Wei173acc72008-03-01 07:42:48 -0700562#endif
563
Zhang Wei56822842008-03-13 10:45:27 -0700564 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
Zhang Wei173acc72008-03-01 07:42:48 -0700565
Ira Snydera1c03312010-01-06 13:34:05 +0000566 set_desc_cnt(chan, &new->hw, copy);
567 set_desc_src(chan, &new->hw, dma_src);
568 set_desc_dst(chan, &new->hw, dma_dst);
Zhang Wei173acc72008-03-01 07:42:48 -0700569
570 if (!first)
571 first = new;
572 else
Ira Snydera1c03312010-01-06 13:34:05 +0000573 set_desc_next(chan, &prev->hw, new->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700574
575 new->async_tx.cookie = 0;
Dan Williams636bdea2008-04-17 20:17:26 -0700576 async_tx_ack(&new->async_tx);
Zhang Wei173acc72008-03-01 07:42:48 -0700577
578 prev = new;
579 len -= copy;
580 dma_src += copy;
Ira Snyder738f5f72010-01-06 13:34:02 +0000581 dma_dst += copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700582
583 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700584 list_add_tail(&new->node, &first->tx_list);
Zhang Wei173acc72008-03-01 07:42:48 -0700585 } while (len);
586
Dan Williams636bdea2008-04-17 20:17:26 -0700587 new->async_tx.flags = flags; /* client is in control of this ack */
Zhang Wei173acc72008-03-01 07:42:48 -0700588 new->async_tx.cookie = -EBUSY;
589
590 /* Set End-of-link to the last link descriptor of new list*/
Ira Snydera1c03312010-01-06 13:34:05 +0000591 set_ld_eol(chan, new);
Zhang Wei173acc72008-03-01 07:42:48 -0700592
Ira Snyder2e077f82009-05-15 09:59:46 -0700593 return &first->async_tx;
594
595fail:
596 if (!first)
597 return NULL;
598
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000599 fsldma_free_desc_list_reverse(chan, &first->tx_list);
Ira Snyder2e077f82009-05-15 09:59:46 -0700600 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700601}
602
Ira Snyderc14330412010-09-30 11:46:45 +0000603static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
604 struct scatterlist *dst_sg, unsigned int dst_nents,
605 struct scatterlist *src_sg, unsigned int src_nents,
606 unsigned long flags)
607{
608 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
609 struct fsldma_chan *chan = to_fsl_chan(dchan);
610 size_t dst_avail, src_avail;
611 dma_addr_t dst, src;
612 size_t len;
613
614 /* basic sanity checks */
615 if (dst_nents == 0 || src_nents == 0)
616 return NULL;
617
618 if (dst_sg == NULL || src_sg == NULL)
619 return NULL;
620
621 /*
622 * TODO: should we check that both scatterlists have the same
623 * TODO: number of bytes in total? Is that really an error?
624 */
625
626 /* get prepared for the loop */
627 dst_avail = sg_dma_len(dst_sg);
628 src_avail = sg_dma_len(src_sg);
629
630 /* run until we are out of scatterlist entries */
631 while (true) {
632
633 /* create the largest transaction possible */
634 len = min_t(size_t, src_avail, dst_avail);
635 len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
636 if (len == 0)
637 goto fetch;
638
639 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
640 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
641
642 /* allocate and populate the descriptor */
643 new = fsl_dma_alloc_descriptor(chan);
644 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000645 chan_err(chan, "%s\n", msg_ld_oom);
Ira Snyderc14330412010-09-30 11:46:45 +0000646 goto fail;
647 }
648#ifdef FSL_DMA_LD_DEBUG
Ira Snyderb1584712011-03-03 07:54:55 +0000649 chan_dbg(chan, "new link desc alloc %p\n", new);
Ira Snyderc14330412010-09-30 11:46:45 +0000650#endif
651
652 set_desc_cnt(chan, &new->hw, len);
653 set_desc_src(chan, &new->hw, src);
654 set_desc_dst(chan, &new->hw, dst);
655
656 if (!first)
657 first = new;
658 else
659 set_desc_next(chan, &prev->hw, new->async_tx.phys);
660
661 new->async_tx.cookie = 0;
662 async_tx_ack(&new->async_tx);
663 prev = new;
664
665 /* Insert the link descriptor to the LD ring */
666 list_add_tail(&new->node, &first->tx_list);
667
668 /* update metadata */
669 dst_avail -= len;
670 src_avail -= len;
671
672fetch:
673 /* fetch the next dst scatterlist entry */
674 if (dst_avail == 0) {
675
676 /* no more entries: we're done */
677 if (dst_nents == 0)
678 break;
679
680 /* fetch the next entry: if there are no more: done */
681 dst_sg = sg_next(dst_sg);
682 if (dst_sg == NULL)
683 break;
684
685 dst_nents--;
686 dst_avail = sg_dma_len(dst_sg);
687 }
688
689 /* fetch the next src scatterlist entry */
690 if (src_avail == 0) {
691
692 /* no more entries: we're done */
693 if (src_nents == 0)
694 break;
695
696 /* fetch the next entry: if there are no more: done */
697 src_sg = sg_next(src_sg);
698 if (src_sg == NULL)
699 break;
700
701 src_nents--;
702 src_avail = sg_dma_len(src_sg);
703 }
704 }
705
706 new->async_tx.flags = flags; /* client is in control of this ack */
707 new->async_tx.cookie = -EBUSY;
708
709 /* Set End-of-link to the last link descriptor of new list */
710 set_ld_eol(chan, new);
711
712 return &first->async_tx;
713
714fail:
715 if (!first)
716 return NULL;
717
718 fsldma_free_desc_list_reverse(chan, &first->tx_list);
719 return NULL;
720}
721
Zhang Wei173acc72008-03-01 07:42:48 -0700722/**
Ira Snyderbbea0b62009-09-08 17:53:04 -0700723 * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
724 * @chan: DMA channel
725 * @sgl: scatterlist to transfer to/from
726 * @sg_len: number of entries in @scatterlist
727 * @direction: DMA direction
728 * @flags: DMAEngine flags
729 *
730 * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
731 * DMA_SLAVE API, this gets the device-specific information from the
732 * chan->private variable.
733 */
734static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
Ira Snydera1c03312010-01-06 13:34:05 +0000735 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
Ira Snyderbbea0b62009-09-08 17:53:04 -0700736 enum dma_data_direction direction, unsigned long flags)
737{
Ira Snyderbbea0b62009-09-08 17:53:04 -0700738 /*
Ira Snyder968f19a2010-09-30 11:46:46 +0000739 * This operation is not supported on the Freescale DMA controller
Ira Snyderbbea0b62009-09-08 17:53:04 -0700740 *
Ira Snyder968f19a2010-09-30 11:46:46 +0000741 * However, we need to provide the function pointer to allow the
742 * device_control() method to work.
Ira Snyderbbea0b62009-09-08 17:53:04 -0700743 */
Ira Snyderbbea0b62009-09-08 17:53:04 -0700744 return NULL;
745}
746
Linus Walleijc3635c72010-03-26 16:44:01 -0700747static int fsl_dma_device_control(struct dma_chan *dchan,
Linus Walleij05827632010-05-17 16:30:42 -0700748 enum dma_ctrl_cmd cmd, unsigned long arg)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700749{
Ira Snyder968f19a2010-09-30 11:46:46 +0000750 struct dma_slave_config *config;
Ira Snydera1c03312010-01-06 13:34:05 +0000751 struct fsldma_chan *chan;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700752 unsigned long flags;
Ira Snyder968f19a2010-09-30 11:46:46 +0000753 int size;
Linus Walleijc3635c72010-03-26 16:44:01 -0700754
Ira Snydera1c03312010-01-06 13:34:05 +0000755 if (!dchan)
Linus Walleijc3635c72010-03-26 16:44:01 -0700756 return -EINVAL;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700757
Ira Snydera1c03312010-01-06 13:34:05 +0000758 chan = to_fsl_chan(dchan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700759
Ira Snyder968f19a2010-09-30 11:46:46 +0000760 switch (cmd) {
761 case DMA_TERMINATE_ALL:
762 /* Halt the DMA engine */
763 dma_halt(chan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700764
Ira Snyder968f19a2010-09-30 11:46:46 +0000765 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700766
Ira Snyder968f19a2010-09-30 11:46:46 +0000767 /* Remove and free all of the descriptors in the LD queue */
768 fsldma_free_desc_list(chan, &chan->ld_pending);
769 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700770
Ira Snyder968f19a2010-09-30 11:46:46 +0000771 spin_unlock_irqrestore(&chan->desc_lock, flags);
772 return 0;
773
774 case DMA_SLAVE_CONFIG:
775 config = (struct dma_slave_config *)arg;
776
777 /* make sure the channel supports setting burst size */
778 if (!chan->set_request_count)
779 return -ENXIO;
780
781 /* we set the controller burst size depending on direction */
782 if (config->direction == DMA_TO_DEVICE)
783 size = config->dst_addr_width * config->dst_maxburst;
784 else
785 size = config->src_addr_width * config->src_maxburst;
786
787 chan->set_request_count(chan, size);
788 return 0;
789
790 case FSLDMA_EXTERNAL_START:
791
792 /* make sure the channel supports external start */
793 if (!chan->toggle_ext_start)
794 return -ENXIO;
795
796 chan->toggle_ext_start(chan, arg);
797 return 0;
798
799 default:
800 return -ENXIO;
801 }
Linus Walleijc3635c72010-03-26 16:44:01 -0700802
803 return 0;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700804}
805
806/**
Zhang Wei173acc72008-03-01 07:42:48 -0700807 * fsl_dma_update_completed_cookie - Update the completed cookie.
Ira Snydera1c03312010-01-06 13:34:05 +0000808 * @chan : Freescale DMA channel
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000809 *
810 * CONTEXT: hardirq
Zhang Wei173acc72008-03-01 07:42:48 -0700811 */
Ira Snydera1c03312010-01-06 13:34:05 +0000812static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700813{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000814 struct fsl_desc_sw *desc;
815 unsigned long flags;
816 dma_cookie_t cookie;
Zhang Wei173acc72008-03-01 07:42:48 -0700817
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000818 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700819
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000820 if (list_empty(&chan->ld_running)) {
Ira Snyderb1584712011-03-03 07:54:55 +0000821 chan_dbg(chan, "no running descriptors\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000822 goto out_unlock;
Zhang Wei173acc72008-03-01 07:42:48 -0700823 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000824
825 /* Get the last descriptor, update the cookie to that */
826 desc = to_fsl_desc(chan->ld_running.prev);
827 if (dma_is_idle(chan))
828 cookie = desc->async_tx.cookie;
Steven J. Magnani76bd0612010-02-28 22:18:16 -0700829 else {
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000830 cookie = desc->async_tx.cookie - 1;
Steven J. Magnani76bd0612010-02-28 22:18:16 -0700831 if (unlikely(cookie < DMA_MIN_COOKIE))
832 cookie = DMA_MAX_COOKIE;
833 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000834
835 chan->completed_cookie = cookie;
836
837out_unlock:
838 spin_unlock_irqrestore(&chan->desc_lock, flags);
839}
840
841/**
842 * fsldma_desc_status - Check the status of a descriptor
843 * @chan: Freescale DMA channel
844 * @desc: DMA SW descriptor
845 *
846 * This function will return the status of the given descriptor
847 */
848static enum dma_status fsldma_desc_status(struct fsldma_chan *chan,
849 struct fsl_desc_sw *desc)
850{
851 return dma_async_is_complete(desc->async_tx.cookie,
852 chan->completed_cookie,
853 chan->common.cookie);
Zhang Wei173acc72008-03-01 07:42:48 -0700854}
855
856/**
857 * fsl_chan_ld_cleanup - Clean up link descriptors
Ira Snydera1c03312010-01-06 13:34:05 +0000858 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700859 *
860 * This function clean up the ld_queue of DMA channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700861 */
Ira Snydera1c03312010-01-06 13:34:05 +0000862static void fsl_chan_ld_cleanup(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700863{
864 struct fsl_desc_sw *desc, *_desc;
865 unsigned long flags;
866
Ira Snydera1c03312010-01-06 13:34:05 +0000867 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700868
Ira Snyderb1584712011-03-03 07:54:55 +0000869 chan_dbg(chan, "chan completed_cookie = %d\n", chan->completed_cookie);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000870 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
Zhang Wei173acc72008-03-01 07:42:48 -0700871 dma_async_tx_callback callback;
872 void *callback_param;
873
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000874 if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS)
Zhang Wei173acc72008-03-01 07:42:48 -0700875 break;
876
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000877 /* Remove from the list of running transactions */
Zhang Wei173acc72008-03-01 07:42:48 -0700878 list_del(&desc->node);
879
Zhang Wei173acc72008-03-01 07:42:48 -0700880 /* Run the link descriptor callback function */
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000881 callback = desc->async_tx.callback;
882 callback_param = desc->async_tx.callback_param;
Zhang Wei173acc72008-03-01 07:42:48 -0700883 if (callback) {
Ira Snydera1c03312010-01-06 13:34:05 +0000884 spin_unlock_irqrestore(&chan->desc_lock, flags);
Ira Snyderb1584712011-03-03 07:54:55 +0000885 chan_dbg(chan, "LD %p callback\n", desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700886 callback(callback_param);
Ira Snydera1c03312010-01-06 13:34:05 +0000887 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700888 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000889
890 /* Run any dependencies, then free the descriptor */
891 dma_run_dependencies(&desc->async_tx);
892 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700893 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000894
Ira Snydera1c03312010-01-06 13:34:05 +0000895 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700896}
897
898/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000899 * fsl_chan_xfer_ld_queue - transfer any pending transactions
Ira Snydera1c03312010-01-06 13:34:05 +0000900 * @chan : Freescale DMA channel
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000901 *
902 * This will make sure that any pending transactions will be run.
903 * If the DMA controller is idle, it will be started. Otherwise,
904 * the DMA controller's interrupt handler will start any pending
905 * transactions when it becomes idle.
Zhang Wei173acc72008-03-01 07:42:48 -0700906 */
Ira Snydera1c03312010-01-06 13:34:05 +0000907static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700908{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000909 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700910 unsigned long flags;
911
Ira Snydera1c03312010-01-06 13:34:05 +0000912 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyder138ef012009-05-19 15:42:13 -0700913
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000914 /*
915 * If the list of pending descriptors is empty, then we
916 * don't need to do any work at all
917 */
918 if (list_empty(&chan->ld_pending)) {
Ira Snyderb1584712011-03-03 07:54:55 +0000919 chan_dbg(chan, "no pending LDs\n");
Ira Snyder138ef012009-05-19 15:42:13 -0700920 goto out_unlock;
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000921 }
Zhang Wei173acc72008-03-01 07:42:48 -0700922
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000923 /*
924 * The DMA controller is not idle, which means the interrupt
925 * handler will start any queued transactions when it runs
926 * at the end of the current transaction
927 */
928 if (!dma_is_idle(chan)) {
Ira Snyderb1584712011-03-03 07:54:55 +0000929 chan_dbg(chan, "DMA controller still busy\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000930 goto out_unlock;
931 }
932
933 /*
934 * TODO:
935 * make sure the dma_halt() function really un-wedges the
936 * controller as much as possible
937 */
Ira Snydera1c03312010-01-06 13:34:05 +0000938 dma_halt(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700939
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000940 /*
941 * If there are some link descriptors which have not been
942 * transferred, we need to start the controller
Zhang Wei173acc72008-03-01 07:42:48 -0700943 */
Zhang Wei173acc72008-03-01 07:42:48 -0700944
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000945 /*
946 * Move all elements from the queue of pending transactions
947 * onto the list of running transactions
948 */
949 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
950 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
Zhang Wei173acc72008-03-01 07:42:48 -0700951
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000952 /*
953 * Program the descriptor's address into the DMA controller,
954 * then start the DMA transaction
955 */
956 set_cdar(chan, desc->async_tx.phys);
957 dma_start(chan);
Ira Snyder138ef012009-05-19 15:42:13 -0700958
959out_unlock:
Ira Snydera1c03312010-01-06 13:34:05 +0000960 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700961}
962
963/**
964 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
Ira Snydera1c03312010-01-06 13:34:05 +0000965 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700966 */
Ira Snydera1c03312010-01-06 13:34:05 +0000967static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700968{
Ira Snydera1c03312010-01-06 13:34:05 +0000969 struct fsldma_chan *chan = to_fsl_chan(dchan);
Ira Snydera1c03312010-01-06 13:34:05 +0000970 fsl_chan_xfer_ld_queue(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700971}
972
Zhang Wei173acc72008-03-01 07:42:48 -0700973/**
Linus Walleij07934482010-03-26 16:50:49 -0700974 * fsl_tx_status - Determine the DMA status
Ira Snydera1c03312010-01-06 13:34:05 +0000975 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700976 */
Linus Walleij07934482010-03-26 16:50:49 -0700977static enum dma_status fsl_tx_status(struct dma_chan *dchan,
Zhang Wei173acc72008-03-01 07:42:48 -0700978 dma_cookie_t cookie,
Linus Walleij07934482010-03-26 16:50:49 -0700979 struct dma_tx_state *txstate)
Zhang Wei173acc72008-03-01 07:42:48 -0700980{
Ira Snydera1c03312010-01-06 13:34:05 +0000981 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700982 dma_cookie_t last_used;
983 dma_cookie_t last_complete;
984
Ira Snydera1c03312010-01-06 13:34:05 +0000985 fsl_chan_ld_cleanup(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700986
Ira Snydera1c03312010-01-06 13:34:05 +0000987 last_used = dchan->cookie;
988 last_complete = chan->completed_cookie;
Zhang Wei173acc72008-03-01 07:42:48 -0700989
Dan Williamsbca34692010-03-26 16:52:10 -0700990 dma_set_tx_state(txstate, last_complete, last_used, 0);
Zhang Wei173acc72008-03-01 07:42:48 -0700991
992 return dma_async_is_complete(cookie, last_complete, last_used);
993}
994
Ira Snyderd3f620b2010-01-06 13:34:04 +0000995/*----------------------------------------------------------------------------*/
996/* Interrupt Handling */
997/*----------------------------------------------------------------------------*/
998
Ira Snydere7a29152010-01-06 13:34:03 +0000999static irqreturn_t fsldma_chan_irq(int irq, void *data)
Zhang Wei173acc72008-03-01 07:42:48 -07001000{
Ira Snydera1c03312010-01-06 13:34:05 +00001001 struct fsldma_chan *chan = data;
Zhang Wei1c629792008-04-17 20:17:25 -07001002 int update_cookie = 0;
1003 int xfer_ld_q = 0;
Ira Snydera1c03312010-01-06 13:34:05 +00001004 u32 stat;
Zhang Wei173acc72008-03-01 07:42:48 -07001005
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001006 /* save and clear the status register */
Ira Snydera1c03312010-01-06 13:34:05 +00001007 stat = get_sr(chan);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001008 set_sr(chan, stat);
Ira Snyderb1584712011-03-03 07:54:55 +00001009 chan_dbg(chan, "irq: stat = 0x%x\n", stat);
Zhang Wei173acc72008-03-01 07:42:48 -07001010
1011 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1012 if (!stat)
1013 return IRQ_NONE;
1014
1015 if (stat & FSL_DMA_SR_TE)
Ira Snyderb1584712011-03-03 07:54:55 +00001016 chan_err(chan, "Transfer Error!\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001017
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001018 /*
1019 * Programming Error
Zhang Weif79abb62008-03-18 18:45:00 -07001020 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
1021 * triger a PE interrupt.
1022 */
1023 if (stat & FSL_DMA_SR_PE) {
Ira Snyderb1584712011-03-03 07:54:55 +00001024 chan_dbg(chan, "irq: Programming Error INT\n");
Ira Snydera1c03312010-01-06 13:34:05 +00001025 if (get_bcr(chan) == 0) {
Zhang Weif79abb62008-03-18 18:45:00 -07001026 /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
1027 * Now, update the completed cookie, and continue the
1028 * next uncompleted transfer.
1029 */
Zhang Wei1c629792008-04-17 20:17:25 -07001030 update_cookie = 1;
1031 xfer_ld_q = 1;
Zhang Weif79abb62008-03-18 18:45:00 -07001032 }
1033 stat &= ~FSL_DMA_SR_PE;
1034 }
1035
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001036 /*
1037 * If the link descriptor segment transfer finishes,
Zhang Wei173acc72008-03-01 07:42:48 -07001038 * we will recycle the used descriptor.
1039 */
1040 if (stat & FSL_DMA_SR_EOSI) {
Ira Snyderb1584712011-03-03 07:54:55 +00001041 chan_dbg(chan, "irq: End-of-segments INT\n");
1042 chan_dbg(chan, "irq: clndar 0x%llx, nlndar 0x%llx\n",
Ira Snydera1c03312010-01-06 13:34:05 +00001043 (unsigned long long)get_cdar(chan),
1044 (unsigned long long)get_ndar(chan));
Zhang Wei173acc72008-03-01 07:42:48 -07001045 stat &= ~FSL_DMA_SR_EOSI;
Zhang Wei1c629792008-04-17 20:17:25 -07001046 update_cookie = 1;
1047 }
1048
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001049 /*
1050 * For MPC8349, EOCDI event need to update cookie
Zhang Wei1c629792008-04-17 20:17:25 -07001051 * and start the next transfer if it exist.
1052 */
1053 if (stat & FSL_DMA_SR_EOCDI) {
Ira Snyderb1584712011-03-03 07:54:55 +00001054 chan_dbg(chan, "irq: End-of-Chain link INT\n");
Zhang Wei1c629792008-04-17 20:17:25 -07001055 stat &= ~FSL_DMA_SR_EOCDI;
1056 update_cookie = 1;
1057 xfer_ld_q = 1;
Zhang Wei173acc72008-03-01 07:42:48 -07001058 }
1059
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001060 /*
1061 * If it current transfer is the end-of-transfer,
Zhang Wei173acc72008-03-01 07:42:48 -07001062 * we should clear the Channel Start bit for
1063 * prepare next transfer.
1064 */
Zhang Wei1c629792008-04-17 20:17:25 -07001065 if (stat & FSL_DMA_SR_EOLNI) {
Ira Snyderb1584712011-03-03 07:54:55 +00001066 chan_dbg(chan, "irq: End-of-link INT\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001067 stat &= ~FSL_DMA_SR_EOLNI;
Zhang Wei1c629792008-04-17 20:17:25 -07001068 xfer_ld_q = 1;
Zhang Wei173acc72008-03-01 07:42:48 -07001069 }
1070
Zhang Wei1c629792008-04-17 20:17:25 -07001071 if (update_cookie)
Ira Snydera1c03312010-01-06 13:34:05 +00001072 fsl_dma_update_completed_cookie(chan);
Zhang Wei1c629792008-04-17 20:17:25 -07001073 if (xfer_ld_q)
Ira Snydera1c03312010-01-06 13:34:05 +00001074 fsl_chan_xfer_ld_queue(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001075 if (stat)
Ira Snyderb1584712011-03-03 07:54:55 +00001076 chan_dbg(chan, "irq: unhandled sr 0x%08x\n", stat);
Zhang Wei173acc72008-03-01 07:42:48 -07001077
Ira Snyderb1584712011-03-03 07:54:55 +00001078 chan_dbg(chan, "irq: Exit\n");
Ira Snydera1c03312010-01-06 13:34:05 +00001079 tasklet_schedule(&chan->tasklet);
Zhang Wei173acc72008-03-01 07:42:48 -07001080 return IRQ_HANDLED;
1081}
1082
Zhang Wei173acc72008-03-01 07:42:48 -07001083static void dma_do_tasklet(unsigned long data)
1084{
Ira Snydera1c03312010-01-06 13:34:05 +00001085 struct fsldma_chan *chan = (struct fsldma_chan *)data;
1086 fsl_chan_ld_cleanup(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001087}
1088
Ira Snyderd3f620b2010-01-06 13:34:04 +00001089static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1090{
1091 struct fsldma_device *fdev = data;
1092 struct fsldma_chan *chan;
1093 unsigned int handled = 0;
1094 u32 gsr, mask;
1095 int i;
1096
1097 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1098 : in_le32(fdev->regs);
1099 mask = 0xff000000;
1100 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1101
1102 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1103 chan = fdev->chan[i];
1104 if (!chan)
1105 continue;
1106
1107 if (gsr & mask) {
1108 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1109 fsldma_chan_irq(irq, chan);
1110 handled++;
1111 }
1112
1113 gsr &= ~mask;
1114 mask >>= 8;
1115 }
1116
1117 return IRQ_RETVAL(handled);
1118}
1119
1120static void fsldma_free_irqs(struct fsldma_device *fdev)
1121{
1122 struct fsldma_chan *chan;
1123 int i;
1124
1125 if (fdev->irq != NO_IRQ) {
1126 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1127 free_irq(fdev->irq, fdev);
1128 return;
1129 }
1130
1131 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1132 chan = fdev->chan[i];
1133 if (chan && chan->irq != NO_IRQ) {
Ira Snyderb1584712011-03-03 07:54:55 +00001134 chan_dbg(chan, "free per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001135 free_irq(chan->irq, chan);
1136 }
1137 }
1138}
1139
1140static int fsldma_request_irqs(struct fsldma_device *fdev)
1141{
1142 struct fsldma_chan *chan;
1143 int ret;
1144 int i;
1145
1146 /* if we have a per-controller IRQ, use that */
1147 if (fdev->irq != NO_IRQ) {
1148 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1149 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1150 "fsldma-controller", fdev);
1151 return ret;
1152 }
1153
1154 /* no per-controller IRQ, use the per-channel IRQs */
1155 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1156 chan = fdev->chan[i];
1157 if (!chan)
1158 continue;
1159
1160 if (chan->irq == NO_IRQ) {
Ira Snyderb1584712011-03-03 07:54:55 +00001161 chan_err(chan, "interrupts property missing in device tree\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001162 ret = -ENODEV;
1163 goto out_unwind;
1164 }
1165
Ira Snyderb1584712011-03-03 07:54:55 +00001166 chan_dbg(chan, "request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001167 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1168 "fsldma-chan", chan);
1169 if (ret) {
Ira Snyderb1584712011-03-03 07:54:55 +00001170 chan_err(chan, "unable to request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001171 goto out_unwind;
1172 }
1173 }
1174
1175 return 0;
1176
1177out_unwind:
1178 for (/* none */; i >= 0; i--) {
1179 chan = fdev->chan[i];
1180 if (!chan)
1181 continue;
1182
1183 if (chan->irq == NO_IRQ)
1184 continue;
1185
1186 free_irq(chan->irq, chan);
1187 }
1188
1189 return ret;
1190}
1191
Ira Snydera4f56d42010-01-06 13:34:01 +00001192/*----------------------------------------------------------------------------*/
1193/* OpenFirmware Subsystem */
1194/*----------------------------------------------------------------------------*/
1195
1196static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
Timur Tabi77cd62e2008-09-26 17:00:11 -07001197 struct device_node *node, u32 feature, const char *compatible)
Zhang Wei173acc72008-03-01 07:42:48 -07001198{
Ira Snydera1c03312010-01-06 13:34:05 +00001199 struct fsldma_chan *chan;
Ira Snyder4ce0e952010-01-06 13:34:00 +00001200 struct resource res;
Zhang Wei173acc72008-03-01 07:42:48 -07001201 int err;
1202
Zhang Wei173acc72008-03-01 07:42:48 -07001203 /* alloc channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001204 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1205 if (!chan) {
Ira Snydere7a29152010-01-06 13:34:03 +00001206 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1207 err = -ENOMEM;
1208 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001209 }
1210
Ira Snydere7a29152010-01-06 13:34:03 +00001211 /* ioremap registers for use */
Ira Snydera1c03312010-01-06 13:34:05 +00001212 chan->regs = of_iomap(node, 0);
1213 if (!chan->regs) {
Ira Snydere7a29152010-01-06 13:34:03 +00001214 dev_err(fdev->dev, "unable to ioremap registers\n");
1215 err = -ENOMEM;
Ira Snydera1c03312010-01-06 13:34:05 +00001216 goto out_free_chan;
Ira Snydere7a29152010-01-06 13:34:03 +00001217 }
1218
Ira Snyder4ce0e952010-01-06 13:34:00 +00001219 err = of_address_to_resource(node, 0, &res);
Zhang Wei173acc72008-03-01 07:42:48 -07001220 if (err) {
Ira Snydere7a29152010-01-06 13:34:03 +00001221 dev_err(fdev->dev, "unable to find 'reg' property\n");
1222 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001223 }
1224
Ira Snydera1c03312010-01-06 13:34:05 +00001225 chan->feature = feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001226 if (!fdev->feature)
Ira Snydera1c03312010-01-06 13:34:05 +00001227 fdev->feature = chan->feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001228
Ira Snydere7a29152010-01-06 13:34:03 +00001229 /*
1230 * If the DMA device's feature is different than the feature
1231 * of its channels, report the bug
Zhang Wei173acc72008-03-01 07:42:48 -07001232 */
Ira Snydera1c03312010-01-06 13:34:05 +00001233 WARN_ON(fdev->feature != chan->feature);
Zhang Wei173acc72008-03-01 07:42:48 -07001234
Ira Snydera1c03312010-01-06 13:34:05 +00001235 chan->dev = fdev->dev;
1236 chan->id = ((res.start - 0x100) & 0xfff) >> 7;
1237 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
Ira Snydere7a29152010-01-06 13:34:03 +00001238 dev_err(fdev->dev, "too many channels for device\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001239 err = -EINVAL;
Ira Snydere7a29152010-01-06 13:34:03 +00001240 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001241 }
Zhang Wei173acc72008-03-01 07:42:48 -07001242
Ira Snydera1c03312010-01-06 13:34:05 +00001243 fdev->chan[chan->id] = chan;
1244 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
Ira Snyderb1584712011-03-03 07:54:55 +00001245 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
Ira Snydere7a29152010-01-06 13:34:03 +00001246
1247 /* Initialize the channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001248 dma_init(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001249
1250 /* Clear cdar registers */
Ira Snydera1c03312010-01-06 13:34:05 +00001251 set_cdar(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -07001252
Ira Snydera1c03312010-01-06 13:34:05 +00001253 switch (chan->feature & FSL_DMA_IP_MASK) {
Zhang Wei173acc72008-03-01 07:42:48 -07001254 case FSL_DMA_IP_85XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001255 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
Zhang Wei173acc72008-03-01 07:42:48 -07001256 case FSL_DMA_IP_83XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001257 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1258 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1259 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1260 chan->set_request_count = fsl_chan_set_request_count;
Zhang Wei173acc72008-03-01 07:42:48 -07001261 }
1262
Ira Snydera1c03312010-01-06 13:34:05 +00001263 spin_lock_init(&chan->desc_lock);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001264 INIT_LIST_HEAD(&chan->ld_pending);
1265 INIT_LIST_HEAD(&chan->ld_running);
Zhang Wei173acc72008-03-01 07:42:48 -07001266
Ira Snydera1c03312010-01-06 13:34:05 +00001267 chan->common.device = &fdev->common;
Zhang Wei173acc72008-03-01 07:42:48 -07001268
Ira Snyderd3f620b2010-01-06 13:34:04 +00001269 /* find the IRQ line, if it exists in the device tree */
Ira Snydera1c03312010-01-06 13:34:05 +00001270 chan->irq = irq_of_parse_and_map(node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001271
Zhang Wei173acc72008-03-01 07:42:48 -07001272 /* Add the channel to DMA device channel list */
Ira Snydera1c03312010-01-06 13:34:05 +00001273 list_add_tail(&chan->common.device_node, &fdev->common.channels);
Zhang Wei173acc72008-03-01 07:42:48 -07001274 fdev->common.chancnt++;
1275
Ira Snydera1c03312010-01-06 13:34:05 +00001276 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1277 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001278
1279 return 0;
Li Yang51ee87f2008-05-29 23:25:45 -07001280
Ira Snydere7a29152010-01-06 13:34:03 +00001281out_iounmap_regs:
Ira Snydera1c03312010-01-06 13:34:05 +00001282 iounmap(chan->regs);
1283out_free_chan:
1284 kfree(chan);
Ira Snydere7a29152010-01-06 13:34:03 +00001285out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001286 return err;
1287}
1288
Ira Snydera1c03312010-01-06 13:34:05 +00001289static void fsl_dma_chan_remove(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -07001290{
Ira Snydera1c03312010-01-06 13:34:05 +00001291 irq_dispose_mapping(chan->irq);
1292 list_del(&chan->common.device_node);
1293 iounmap(chan->regs);
1294 kfree(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001295}
1296
Grant Likely2dc11582010-08-06 09:25:50 -06001297static int __devinit fsldma_of_probe(struct platform_device *op,
Zhang Wei173acc72008-03-01 07:42:48 -07001298 const struct of_device_id *match)
1299{
Ira Snydera4f56d42010-01-06 13:34:01 +00001300 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001301 struct device_node *child;
Ira Snydere7a29152010-01-06 13:34:03 +00001302 int err;
Zhang Wei173acc72008-03-01 07:42:48 -07001303
Ira Snydera4f56d42010-01-06 13:34:01 +00001304 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
Zhang Wei173acc72008-03-01 07:42:48 -07001305 if (!fdev) {
Ira Snydere7a29152010-01-06 13:34:03 +00001306 dev_err(&op->dev, "No enough memory for 'priv'\n");
1307 err = -ENOMEM;
1308 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001309 }
Ira Snydere7a29152010-01-06 13:34:03 +00001310
1311 fdev->dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001312 INIT_LIST_HEAD(&fdev->common.channels);
1313
Ira Snydere7a29152010-01-06 13:34:03 +00001314 /* ioremap the registers for use */
Grant Likely61c7a082010-04-13 16:12:29 -07001315 fdev->regs = of_iomap(op->dev.of_node, 0);
Ira Snydere7a29152010-01-06 13:34:03 +00001316 if (!fdev->regs) {
1317 dev_err(&op->dev, "unable to ioremap registers\n");
1318 err = -ENOMEM;
1319 goto out_free_fdev;
Zhang Wei173acc72008-03-01 07:42:48 -07001320 }
1321
Ira Snyderd3f620b2010-01-06 13:34:04 +00001322 /* map the channel IRQ if it exists, but don't hookup the handler yet */
Grant Likely61c7a082010-04-13 16:12:29 -07001323 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001324
Zhang Wei173acc72008-03-01 07:42:48 -07001325 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1326 dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
Ira Snyderc14330412010-09-30 11:46:45 +00001327 dma_cap_set(DMA_SG, fdev->common.cap_mask);
Ira Snyderbbea0b62009-09-08 17:53:04 -07001328 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
Zhang Wei173acc72008-03-01 07:42:48 -07001329 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1330 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
Zhang Wei2187c262008-03-13 17:45:28 -07001331 fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
Zhang Wei173acc72008-03-01 07:42:48 -07001332 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
Ira Snyderc14330412010-09-30 11:46:45 +00001333 fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
Linus Walleij07934482010-03-26 16:50:49 -07001334 fdev->common.device_tx_status = fsl_tx_status;
Zhang Wei173acc72008-03-01 07:42:48 -07001335 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
Ira Snyderbbea0b62009-09-08 17:53:04 -07001336 fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
Linus Walleijc3635c72010-03-26 16:44:01 -07001337 fdev->common.device_control = fsl_dma_device_control;
Ira Snydere7a29152010-01-06 13:34:03 +00001338 fdev->common.dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001339
Li Yange2c8e4252010-11-11 20:16:29 +08001340 dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1341
Ira Snydere7a29152010-01-06 13:34:03 +00001342 dev_set_drvdata(&op->dev, fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001343
Ira Snydere7a29152010-01-06 13:34:03 +00001344 /*
1345 * We cannot use of_platform_bus_probe() because there is no
1346 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -07001347 * channel object.
1348 */
Grant Likely61c7a082010-04-13 16:12:29 -07001349 for_each_child_of_node(op->dev.of_node, child) {
Ira Snydere7a29152010-01-06 13:34:03 +00001350 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001351 fsl_dma_chan_probe(fdev, child,
1352 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1353 "fsl,eloplus-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001354 }
1355
1356 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001357 fsl_dma_chan_probe(fdev, child,
1358 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1359 "fsl,elo-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001360 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001361 }
Zhang Wei173acc72008-03-01 07:42:48 -07001362
Ira Snyderd3f620b2010-01-06 13:34:04 +00001363 /*
1364 * Hookup the IRQ handler(s)
1365 *
1366 * If we have a per-controller interrupt, we prefer that to the
1367 * per-channel interrupts to reduce the number of shared interrupt
1368 * handlers on the same IRQ line
1369 */
1370 err = fsldma_request_irqs(fdev);
1371 if (err) {
1372 dev_err(fdev->dev, "unable to request IRQs\n");
1373 goto out_free_fdev;
1374 }
1375
Zhang Wei173acc72008-03-01 07:42:48 -07001376 dma_async_device_register(&fdev->common);
1377 return 0;
1378
Ira Snydere7a29152010-01-06 13:34:03 +00001379out_free_fdev:
Ira Snyderd3f620b2010-01-06 13:34:04 +00001380 irq_dispose_mapping(fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001381 kfree(fdev);
Ira Snydere7a29152010-01-06 13:34:03 +00001382out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001383 return err;
1384}
1385
Grant Likely2dc11582010-08-06 09:25:50 -06001386static int fsldma_of_remove(struct platform_device *op)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001387{
Ira Snydera4f56d42010-01-06 13:34:01 +00001388 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001389 unsigned int i;
1390
Ira Snydere7a29152010-01-06 13:34:03 +00001391 fdev = dev_get_drvdata(&op->dev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001392 dma_async_device_unregister(&fdev->common);
1393
Ira Snyderd3f620b2010-01-06 13:34:04 +00001394 fsldma_free_irqs(fdev);
1395
Ira Snydere7a29152010-01-06 13:34:03 +00001396 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001397 if (fdev->chan[i])
1398 fsl_dma_chan_remove(fdev->chan[i]);
Ira Snydere7a29152010-01-06 13:34:03 +00001399 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001400
Ira Snydere7a29152010-01-06 13:34:03 +00001401 iounmap(fdev->regs);
1402 dev_set_drvdata(&op->dev, NULL);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001403 kfree(fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001404
1405 return 0;
1406}
1407
Márton Németh4b1cf1f2010-02-02 23:41:06 -07001408static const struct of_device_id fsldma_of_ids[] = {
Kumar Gala049c9d42008-03-31 11:13:21 -05001409 { .compatible = "fsl,eloplus-dma", },
1410 { .compatible = "fsl,elo-dma", },
Zhang Wei173acc72008-03-01 07:42:48 -07001411 {}
1412};
1413
Ira Snydera4f56d42010-01-06 13:34:01 +00001414static struct of_platform_driver fsldma_of_driver = {
Grant Likely40182942010-04-13 16:13:02 -07001415 .driver = {
1416 .name = "fsl-elo-dma",
1417 .owner = THIS_MODULE,
1418 .of_match_table = fsldma_of_ids,
1419 },
1420 .probe = fsldma_of_probe,
1421 .remove = fsldma_of_remove,
Zhang Wei173acc72008-03-01 07:42:48 -07001422};
1423
Ira Snydera4f56d42010-01-06 13:34:01 +00001424/*----------------------------------------------------------------------------*/
1425/* Module Init / Exit */
1426/*----------------------------------------------------------------------------*/
1427
1428static __init int fsldma_init(void)
Zhang Wei173acc72008-03-01 07:42:48 -07001429{
Timur Tabi77cd62e2008-09-26 17:00:11 -07001430 int ret;
1431
1432 pr_info("Freescale Elo / Elo Plus DMA driver\n");
1433
Ira Snydera4f56d42010-01-06 13:34:01 +00001434 ret = of_register_platform_driver(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001435 if (ret)
1436 pr_err("fsldma: failed to register platform driver\n");
1437
1438 return ret;
Zhang Wei173acc72008-03-01 07:42:48 -07001439}
1440
Ira Snydera4f56d42010-01-06 13:34:01 +00001441static void __exit fsldma_exit(void)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001442{
Ira Snydera4f56d42010-01-06 13:34:01 +00001443 of_unregister_platform_driver(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001444}
1445
Ira Snydera4f56d42010-01-06 13:34:01 +00001446subsys_initcall(fsldma_init);
1447module_exit(fsldma_exit);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001448
1449MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
1450MODULE_LICENSE("GPL");