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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/****************************************************************************/
2
3/*
4 * m5307sim.h -- ColdFire 5307 System Integration Module support.
5 *
6 * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd.
7 * (C) Copyright 1999, Lineo (www.lineo.com)
8 *
9 * Modified by David W. Miller for the MCF5307 Eval Board.
10 */
11
12/****************************************************************************/
13#ifndef m5307sim_h
14#define m5307sim_h
15/****************************************************************************/
16
Greg Ungerer733f31b2010-11-02 17:40:37 +100017#define CPU_NAME "COLDFIRE(m5307)"
18#define CPU_INSTR_PER_JIFFY 3
Greg Ungerer7fc82b62010-11-02 17:13:27 +100019
Greg Ungerer278c2cb2010-11-09 10:19:45 +100020#include <asm/m53xxacr.h>
21
Linus Torvalds1da177e2005-04-16 15:20:36 -070022/*
23 * Define the 5307 SIM register set addresses.
24 */
25#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
26#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
27#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
28#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
29#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
30#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
31#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/
32#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
33#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
34#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
35#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
36#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
37#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
38#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
39#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
40#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
41#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
42#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
43#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
44#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
45#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
46#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
47#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
48
49#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
50#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
51#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
52#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
53#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
54#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
55
56#ifdef CONFIG_OLDMASK
57#define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */
58#define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */
59#define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */
60#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
61#define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */
62#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
63#define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */
64#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
65#define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */
66#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
67#define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */
68#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
69#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */
70#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
71#else
Joe Perchesab690d92008-02-03 17:38:04 +020072#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
Linus Torvalds1da177e2005-04-16 15:20:36 -070073#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
74#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
Joe Perchesab690d92008-02-03 17:38:04 +020075#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
Linus Torvalds1da177e2005-04-16 15:20:36 -070076#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
77#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
Joe Perchesab690d92008-02-03 17:38:04 +020078#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
Linus Torvalds1da177e2005-04-16 15:20:36 -070079#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
80#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
Joe Perchesab690d92008-02-03 17:38:04 +020081#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */
Linus Torvalds1da177e2005-04-16 15:20:36 -070082#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
83#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
Joe Perchesab690d92008-02-03 17:38:04 +020084#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */
Linus Torvalds1da177e2005-04-16 15:20:36 -070085#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
86#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
Joe Perchesab690d92008-02-03 17:38:04 +020087#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */
Linus Torvalds1da177e2005-04-16 15:20:36 -070088#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
89#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
90#endif /* CONFIG_OLDMASK */
91
92#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
93#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
94#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
95#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
96#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
97
sfking@fdwdc.comf7a20ba2009-06-19 18:11:09 -070098#define MCFSIM_PADDR (MCF_MBAR + 0x244)
99#define MCFSIM_PADAT (MCF_MBAR + 0x248)
100
101/*
Greg Ungerer57015422010-11-03 12:50:30 +1000102 * UART module.
103 */
104#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
105#define MCFUART_BASE1 0x200 /* Base address of UART1 */
106#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */
107#else
108#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
109#define MCFUART_BASE2 0x200 /* Base address of UART2 */
110#endif
111
112/*
sfking@fdwdc.comf7a20ba2009-06-19 18:11:09 -0700113 * Generic GPIO support
114 */
115#define MCFGPIO_PIN_MAX 16
116#define MCFGPIO_IRQ_MAX -1
117#define MCFGPIO_IRQ_VECBASE -1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118
119
120/* Definition offset address for CS2-7 -- old mask 5307 */
121
122#define MCF5307_CS2 (0x400000)
123#define MCF5307_CS3 (0x600000)
124#define MCF5307_CS4 (0x800000)
125#define MCF5307_CS5 (0xA00000)
126#define MCF5307_CS6 (0xC00000)
127#define MCF5307_CS7 (0xE00000)
128
129
130/*
131 * Some symbol defines for the above...
132 */
133#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
134#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
135#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
136#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
137#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
138#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
139#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
140#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
141#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
142
Greg Ungerer04b75b12009-05-19 14:52:40 +1000143
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144/*
145 * Some symbol defines for the Parallel Port Pin Assignment Register
146 */
147#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
148 /* Clear to select par I/O */
149#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */
150 /* Clear to select par I/O */
151
152/*
153 * Defines for the IRQPAR Register
154 */
155#define IRQ5_LEVEL4 0x80
156#define IRQ3_LEVEL6 0x40
157#define IRQ1_LEVEL2 0x20
158
Greg Ungerer04b75b12009-05-19 14:52:40 +1000159/*
160 * Define system peripheral IRQ usage.
161 */
162#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
163#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165/****************************************************************************/
166#endif /* m5307sim_h */