Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP2 McSPI controller driver |
| 3 | * |
| 4 | * Copyright (C) 2005, 2006 Nokia Corporation |
| 5 | * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 6 | * Juha Yrj�l� <juha.yrjola@nokia.com> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/module.h> |
| 28 | #include <linux/device.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/dma-mapping.h> |
| 31 | #include <linux/platform_device.h> |
| 32 | #include <linux/err.h> |
| 33 | #include <linux/clk.h> |
| 34 | #include <linux/io.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 35 | #include <linux/slab.h> |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 36 | #include <linux/pm_runtime.h> |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 37 | #include <linux/of.h> |
| 38 | #include <linux/of_device.h> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 39 | |
| 40 | #include <linux/spi/spi.h> |
| 41 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 42 | #include <plat/dma.h> |
| 43 | #include <plat/clock.h> |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 44 | #include <plat/mcspi.h> |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 45 | |
| 46 | #define OMAP2_MCSPI_MAX_FREQ 48000000 |
Shubhrajyoti D | 27b5284 | 2012-03-26 17:04:22 +0530 | [diff] [blame] | 47 | #define SPI_AUTOSUSPEND_TIMEOUT 2000 |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 48 | |
| 49 | #define OMAP2_MCSPI_REVISION 0x00 |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 50 | #define OMAP2_MCSPI_SYSSTATUS 0x14 |
| 51 | #define OMAP2_MCSPI_IRQSTATUS 0x18 |
| 52 | #define OMAP2_MCSPI_IRQENABLE 0x1c |
| 53 | #define OMAP2_MCSPI_WAKEUPENABLE 0x20 |
| 54 | #define OMAP2_MCSPI_SYST 0x24 |
| 55 | #define OMAP2_MCSPI_MODULCTRL 0x28 |
| 56 | |
| 57 | /* per-channel banks, 0x14 bytes each, first is: */ |
| 58 | #define OMAP2_MCSPI_CHCONF0 0x2c |
| 59 | #define OMAP2_MCSPI_CHSTAT0 0x30 |
| 60 | #define OMAP2_MCSPI_CHCTRL0 0x34 |
| 61 | #define OMAP2_MCSPI_TX0 0x38 |
| 62 | #define OMAP2_MCSPI_RX0 0x3c |
| 63 | |
| 64 | /* per-register bitmasks: */ |
| 65 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 66 | #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) |
| 67 | #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) |
| 68 | #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 69 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 70 | #define OMAP2_MCSPI_CHCONF_PHA BIT(0) |
| 71 | #define OMAP2_MCSPI_CHCONF_POL BIT(1) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 72 | #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 73 | #define OMAP2_MCSPI_CHCONF_EPOL BIT(6) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 74 | #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 75 | #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) |
| 76 | #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 77 | #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12) |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 78 | #define OMAP2_MCSPI_CHCONF_DMAW BIT(14) |
| 79 | #define OMAP2_MCSPI_CHCONF_DMAR BIT(15) |
| 80 | #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16) |
| 81 | #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17) |
| 82 | #define OMAP2_MCSPI_CHCONF_IS BIT(18) |
| 83 | #define OMAP2_MCSPI_CHCONF_TURBO BIT(19) |
| 84 | #define OMAP2_MCSPI_CHCONF_FORCE BIT(20) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 85 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 86 | #define OMAP2_MCSPI_CHSTAT_RXS BIT(0) |
| 87 | #define OMAP2_MCSPI_CHSTAT_TXS BIT(1) |
| 88 | #define OMAP2_MCSPI_CHSTAT_EOT BIT(2) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 89 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 90 | #define OMAP2_MCSPI_CHCTRL_EN BIT(0) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 91 | |
Jouni Hogander | 7a8fa72 | 2009-09-22 16:45:58 -0700 | [diff] [blame] | 92 | #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 93 | |
| 94 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
| 95 | struct omap2_mcspi_dma { |
| 96 | int dma_tx_channel; |
| 97 | int dma_rx_channel; |
| 98 | |
| 99 | int dma_tx_sync_dev; |
| 100 | int dma_rx_sync_dev; |
| 101 | |
| 102 | struct completion dma_tx_completion; |
| 103 | struct completion dma_rx_completion; |
| 104 | }; |
| 105 | |
| 106 | /* use PIO for small transfers, avoiding DMA setup/teardown overhead and |
| 107 | * cache operations; better heuristics consider wordsize and bitrate. |
| 108 | */ |
Roman Tereshonkov | 8b66c13 | 2010-04-12 09:07:54 +0000 | [diff] [blame] | 109 | #define DMA_MIN_BYTES 160 |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 110 | |
| 111 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 112 | /* |
| 113 | * Used for context save and restore, structure members to be updated whenever |
| 114 | * corresponding registers are modified. |
| 115 | */ |
| 116 | struct omap2_mcspi_regs { |
| 117 | u32 modulctrl; |
| 118 | u32 wakeupenable; |
| 119 | struct list_head cs; |
| 120 | }; |
| 121 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 122 | struct omap2_mcspi { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 123 | struct spi_master *master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 124 | /* Virtual base address of the controller */ |
| 125 | void __iomem *base; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 126 | unsigned long phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 127 | /* SPI1 has 4 channels, while SPI2 has 2 */ |
| 128 | struct omap2_mcspi_dma *dma_channels; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 129 | struct device *dev; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 130 | struct omap2_mcspi_regs ctx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 131 | }; |
| 132 | |
| 133 | struct omap2_mcspi_cs { |
| 134 | void __iomem *base; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 135 | unsigned long phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 136 | int word_len; |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 137 | struct list_head node; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 138 | /* Context save and restore shadow register */ |
| 139 | u32 chconf0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 140 | }; |
| 141 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 142 | #define MOD_REG_BIT(val, mask, set) do { \ |
| 143 | if (set) \ |
| 144 | val |= mask; \ |
| 145 | else \ |
| 146 | val &= ~mask; \ |
| 147 | } while (0) |
| 148 | |
| 149 | static inline void mcspi_write_reg(struct spi_master *master, |
| 150 | int idx, u32 val) |
| 151 | { |
| 152 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 153 | |
| 154 | __raw_writel(val, mcspi->base + idx); |
| 155 | } |
| 156 | |
| 157 | static inline u32 mcspi_read_reg(struct spi_master *master, int idx) |
| 158 | { |
| 159 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 160 | |
| 161 | return __raw_readl(mcspi->base + idx); |
| 162 | } |
| 163 | |
| 164 | static inline void mcspi_write_cs_reg(const struct spi_device *spi, |
| 165 | int idx, u32 val) |
| 166 | { |
| 167 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 168 | |
| 169 | __raw_writel(val, cs->base + idx); |
| 170 | } |
| 171 | |
| 172 | static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx) |
| 173 | { |
| 174 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 175 | |
| 176 | return __raw_readl(cs->base + idx); |
| 177 | } |
| 178 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 179 | static inline u32 mcspi_cached_chconf0(const struct spi_device *spi) |
| 180 | { |
| 181 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 182 | |
| 183 | return cs->chconf0; |
| 184 | } |
| 185 | |
| 186 | static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val) |
| 187 | { |
| 188 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 189 | |
| 190 | cs->chconf0 = val; |
| 191 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val); |
Roman Tereshonkov | a330ce2 | 2010-03-15 09:06:28 +0000 | [diff] [blame] | 192 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 193 | } |
| 194 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 195 | static void omap2_mcspi_set_dma_req(const struct spi_device *spi, |
| 196 | int is_read, int enable) |
| 197 | { |
| 198 | u32 l, rw; |
| 199 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 200 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 201 | |
| 202 | if (is_read) /* 1 is read, 0 write */ |
| 203 | rw = OMAP2_MCSPI_CHCONF_DMAR; |
| 204 | else |
| 205 | rw = OMAP2_MCSPI_CHCONF_DMAW; |
| 206 | |
| 207 | MOD_REG_BIT(l, rw, enable); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 208 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 209 | } |
| 210 | |
| 211 | static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) |
| 212 | { |
| 213 | u32 l; |
| 214 | |
| 215 | l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0; |
| 216 | mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 217 | /* Flash post-writes */ |
| 218 | mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 219 | } |
| 220 | |
| 221 | static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) |
| 222 | { |
| 223 | u32 l; |
| 224 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 225 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 226 | MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 227 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 228 | } |
| 229 | |
| 230 | static void omap2_mcspi_set_master_mode(struct spi_master *master) |
| 231 | { |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 232 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 233 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 234 | u32 l; |
| 235 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 236 | /* |
| 237 | * Setup when switching from (reset default) slave mode |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 238 | * to single-channel master mode |
| 239 | */ |
| 240 | l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL); |
| 241 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0); |
| 242 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0); |
| 243 | MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1); |
| 244 | mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 245 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 246 | ctx->modulctrl = l; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 247 | } |
| 248 | |
| 249 | static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi) |
| 250 | { |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 251 | struct spi_master *spi_cntrl = mcspi->master; |
| 252 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
| 253 | struct omap2_mcspi_cs *cs; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 254 | |
| 255 | /* McSPI: context restore */ |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 256 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); |
| 257 | mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 258 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 259 | list_for_each_entry(cs, &ctx->cs, node) |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 260 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 261 | } |
| 262 | static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) |
| 263 | { |
Shubhrajyoti D | 27b5284 | 2012-03-26 17:04:22 +0530 | [diff] [blame] | 264 | pm_runtime_mark_last_busy(mcspi->dev); |
| 265 | pm_runtime_put_autosuspend(mcspi->dev); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 266 | } |
| 267 | |
| 268 | static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) |
| 269 | { |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 270 | return pm_runtime_get_sync(mcspi->dev); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 271 | } |
| 272 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 273 | static int omap2_prepare_transfer(struct spi_master *master) |
| 274 | { |
| 275 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 276 | |
| 277 | pm_runtime_get_sync(mcspi->dev); |
| 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | static int omap2_unprepare_transfer(struct spi_master *master) |
| 282 | { |
| 283 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
| 284 | |
| 285 | pm_runtime_mark_last_busy(mcspi->dev); |
| 286 | pm_runtime_put_autosuspend(mcspi->dev); |
| 287 | return 0; |
| 288 | } |
| 289 | |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 290 | static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) |
| 291 | { |
| 292 | unsigned long timeout; |
| 293 | |
| 294 | timeout = jiffies + msecs_to_jiffies(1000); |
| 295 | while (!(__raw_readl(reg) & bit)) { |
| 296 | if (time_after(jiffies, timeout)) |
| 297 | return -1; |
| 298 | cpu_relax(); |
| 299 | } |
| 300 | return 0; |
| 301 | } |
| 302 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 303 | static unsigned |
| 304 | omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) |
| 305 | { |
| 306 | struct omap2_mcspi *mcspi; |
| 307 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 308 | struct omap2_mcspi_dma *mcspi_dma; |
| 309 | unsigned int count, c; |
| 310 | unsigned long base, tx_reg, rx_reg; |
| 311 | int word_len, data_type, element_count; |
Govindraj.R | 8b20c8c | 2011-06-01 11:31:24 +0530 | [diff] [blame] | 312 | int elements = 0; |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 313 | u32 l; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 314 | u8 * rx; |
| 315 | const u8 * tx; |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 316 | void __iomem *chstat_reg; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 317 | |
| 318 | mcspi = spi_master_get_devdata(spi->master); |
| 319 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 320 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 321 | |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 322 | chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; |
| 323 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 324 | count = xfer->len; |
| 325 | c = count; |
| 326 | word_len = cs->word_len; |
| 327 | |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 328 | base = cs->phys; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 329 | tx_reg = base + OMAP2_MCSPI_TX0; |
| 330 | rx_reg = base + OMAP2_MCSPI_RX0; |
| 331 | rx = xfer->rx_buf; |
| 332 | tx = xfer->tx_buf; |
| 333 | |
| 334 | if (word_len <= 8) { |
| 335 | data_type = OMAP_DMA_DATA_TYPE_S8; |
| 336 | element_count = count; |
| 337 | } else if (word_len <= 16) { |
| 338 | data_type = OMAP_DMA_DATA_TYPE_S16; |
| 339 | element_count = count >> 1; |
| 340 | } else /* word_len <= 32 */ { |
| 341 | data_type = OMAP_DMA_DATA_TYPE_S32; |
| 342 | element_count = count >> 2; |
| 343 | } |
| 344 | |
| 345 | if (tx != NULL) { |
| 346 | omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel, |
| 347 | data_type, element_count, 1, |
| 348 | OMAP_DMA_SYNC_ELEMENT, |
| 349 | mcspi_dma->dma_tx_sync_dev, 0); |
| 350 | |
| 351 | omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0, |
| 352 | OMAP_DMA_AMODE_CONSTANT, |
| 353 | tx_reg, 0, 0); |
| 354 | |
| 355 | omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0, |
| 356 | OMAP_DMA_AMODE_POST_INC, |
| 357 | xfer->tx_dma, 0, 0); |
| 358 | } |
| 359 | |
| 360 | if (rx != NULL) { |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 361 | elements = element_count - 1; |
| 362 | if (l & OMAP2_MCSPI_CHCONF_TURBO) |
| 363 | elements--; |
| 364 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 365 | omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel, |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 366 | data_type, elements, 1, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 367 | OMAP_DMA_SYNC_ELEMENT, |
| 368 | mcspi_dma->dma_rx_sync_dev, 1); |
| 369 | |
| 370 | omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0, |
| 371 | OMAP_DMA_AMODE_CONSTANT, |
| 372 | rx_reg, 0, 0); |
| 373 | |
| 374 | omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0, |
| 375 | OMAP_DMA_AMODE_POST_INC, |
| 376 | xfer->rx_dma, 0, 0); |
| 377 | } |
| 378 | |
| 379 | if (tx != NULL) { |
| 380 | omap_start_dma(mcspi_dma->dma_tx_channel); |
| 381 | omap2_mcspi_set_dma_req(spi, 0, 1); |
| 382 | } |
| 383 | |
| 384 | if (rx != NULL) { |
| 385 | omap_start_dma(mcspi_dma->dma_rx_channel); |
| 386 | omap2_mcspi_set_dma_req(spi, 1, 1); |
| 387 | } |
| 388 | |
| 389 | if (tx != NULL) { |
| 390 | wait_for_completion(&mcspi_dma->dma_tx_completion); |
Russell King - ARM Linux | 07fe035 | 2011-01-07 15:49:20 +0000 | [diff] [blame] | 391 | dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE); |
Ilkka Koskinen | 2764c50 | 2010-10-19 17:07:31 +0300 | [diff] [blame] | 392 | |
| 393 | /* for TX_ONLY mode, be sure all words have shifted out */ |
| 394 | if (rx == NULL) { |
| 395 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 396 | OMAP2_MCSPI_CHSTAT_TXS) < 0) |
| 397 | dev_err(&spi->dev, "TXS timed out\n"); |
| 398 | else if (mcspi_wait_for_reg_bit(chstat_reg, |
| 399 | OMAP2_MCSPI_CHSTAT_EOT) < 0) |
| 400 | dev_err(&spi->dev, "EOT timed out\n"); |
| 401 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 402 | } |
| 403 | |
| 404 | if (rx != NULL) { |
| 405 | wait_for_completion(&mcspi_dma->dma_rx_completion); |
Russell King - ARM Linux | 07fe035 | 2011-01-07 15:49:20 +0000 | [diff] [blame] | 406 | dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE); |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 407 | omap2_mcspi_set_enable(spi, 0); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 408 | |
| 409 | if (l & OMAP2_MCSPI_CHCONF_TURBO) { |
| 410 | |
| 411 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
| 412 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
| 413 | u32 w; |
| 414 | |
| 415 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); |
| 416 | if (word_len <= 8) |
| 417 | ((u8 *)xfer->rx_buf)[elements++] = w; |
| 418 | else if (word_len <= 16) |
| 419 | ((u16 *)xfer->rx_buf)[elements++] = w; |
| 420 | else /* word_len <= 32 */ |
| 421 | ((u32 *)xfer->rx_buf)[elements++] = w; |
| 422 | } else { |
| 423 | dev_err(&spi->dev, |
| 424 | "DMA RX penultimate word empty"); |
| 425 | count -= (word_len <= 8) ? 2 : |
| 426 | (word_len <= 16) ? 4 : |
| 427 | /* word_len <= 32 */ 8; |
| 428 | omap2_mcspi_set_enable(spi, 1); |
| 429 | return count; |
| 430 | } |
| 431 | } |
| 432 | |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 433 | if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0) |
| 434 | & OMAP2_MCSPI_CHSTAT_RXS)) { |
| 435 | u32 w; |
| 436 | |
| 437 | w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0); |
| 438 | if (word_len <= 8) |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 439 | ((u8 *)xfer->rx_buf)[elements] = w; |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 440 | else if (word_len <= 16) |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 441 | ((u16 *)xfer->rx_buf)[elements] = w; |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 442 | else /* word_len <= 32 */ |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 443 | ((u32 *)xfer->rx_buf)[elements] = w; |
Eero Nurkkala | 57c5c28d | 2009-07-29 15:02:12 -0700 | [diff] [blame] | 444 | } else { |
| 445 | dev_err(&spi->dev, "DMA RX last word empty"); |
| 446 | count -= (word_len <= 8) ? 1 : |
| 447 | (word_len <= 16) ? 2 : |
| 448 | /* word_len <= 32 */ 4; |
| 449 | } |
| 450 | omap2_mcspi_set_enable(spi, 1); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 451 | } |
| 452 | return count; |
| 453 | } |
| 454 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 455 | static unsigned |
| 456 | omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) |
| 457 | { |
| 458 | struct omap2_mcspi *mcspi; |
| 459 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 460 | unsigned int count, c; |
| 461 | u32 l; |
| 462 | void __iomem *base = cs->base; |
| 463 | void __iomem *tx_reg; |
| 464 | void __iomem *rx_reg; |
| 465 | void __iomem *chstat_reg; |
| 466 | int word_len; |
| 467 | |
| 468 | mcspi = spi_master_get_devdata(spi->master); |
| 469 | count = xfer->len; |
| 470 | c = count; |
| 471 | word_len = cs->word_len; |
| 472 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 473 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 474 | |
| 475 | /* We store the pre-calculated register addresses on stack to speed |
| 476 | * up the transfer loop. */ |
| 477 | tx_reg = base + OMAP2_MCSPI_TX0; |
| 478 | rx_reg = base + OMAP2_MCSPI_RX0; |
| 479 | chstat_reg = base + OMAP2_MCSPI_CHSTAT0; |
| 480 | |
Michael Jones | adef658 | 2011-02-25 16:55:11 +0100 | [diff] [blame] | 481 | if (c < (word_len>>3)) |
| 482 | return 0; |
| 483 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 484 | if (word_len <= 8) { |
| 485 | u8 *rx; |
| 486 | const u8 *tx; |
| 487 | |
| 488 | rx = xfer->rx_buf; |
| 489 | tx = xfer->tx_buf; |
| 490 | |
| 491 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 492 | c -= 1; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 493 | if (tx != NULL) { |
| 494 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 495 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 496 | dev_err(&spi->dev, "TXS timed out\n"); |
| 497 | goto out; |
| 498 | } |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 499 | dev_vdbg(&spi->dev, "write-%d %02x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 500 | word_len, *tx); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 501 | __raw_writel(*tx++, tx_reg); |
| 502 | } |
| 503 | if (rx != NULL) { |
| 504 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 505 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 506 | dev_err(&spi->dev, "RXS timed out\n"); |
| 507 | goto out; |
| 508 | } |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 509 | |
| 510 | if (c == 1 && tx == NULL && |
| 511 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
| 512 | omap2_mcspi_set_enable(spi, 0); |
| 513 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 514 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 515 | word_len, *(rx - 1)); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 516 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 517 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 518 | dev_err(&spi->dev, |
| 519 | "RXS timed out\n"); |
| 520 | goto out; |
| 521 | } |
| 522 | c = 0; |
| 523 | } else if (c == 0 && tx == NULL) { |
| 524 | omap2_mcspi_set_enable(spi, 0); |
| 525 | } |
| 526 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 527 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 528 | dev_vdbg(&spi->dev, "read-%d %02x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 529 | word_len, *(rx - 1)); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 530 | } |
Jarkko Nikula | 95c5c3a | 2011-03-21 16:27:30 +0200 | [diff] [blame] | 531 | } while (c); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 532 | } else if (word_len <= 16) { |
| 533 | u16 *rx; |
| 534 | const u16 *tx; |
| 535 | |
| 536 | rx = xfer->rx_buf; |
| 537 | tx = xfer->tx_buf; |
| 538 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 539 | c -= 2; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 540 | if (tx != NULL) { |
| 541 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 542 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 543 | dev_err(&spi->dev, "TXS timed out\n"); |
| 544 | goto out; |
| 545 | } |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 546 | dev_vdbg(&spi->dev, "write-%d %04x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 547 | word_len, *tx); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 548 | __raw_writel(*tx++, tx_reg); |
| 549 | } |
| 550 | if (rx != NULL) { |
| 551 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 552 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 553 | dev_err(&spi->dev, "RXS timed out\n"); |
| 554 | goto out; |
| 555 | } |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 556 | |
| 557 | if (c == 2 && tx == NULL && |
| 558 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
| 559 | omap2_mcspi_set_enable(spi, 0); |
| 560 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 561 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 562 | word_len, *(rx - 1)); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 563 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 564 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 565 | dev_err(&spi->dev, |
| 566 | "RXS timed out\n"); |
| 567 | goto out; |
| 568 | } |
| 569 | c = 0; |
| 570 | } else if (c == 0 && tx == NULL) { |
| 571 | omap2_mcspi_set_enable(spi, 0); |
| 572 | } |
| 573 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 574 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 575 | dev_vdbg(&spi->dev, "read-%d %04x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 576 | word_len, *(rx - 1)); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 577 | } |
Jarkko Nikula | 95c5c3a | 2011-03-21 16:27:30 +0200 | [diff] [blame] | 578 | } while (c >= 2); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 579 | } else if (word_len <= 32) { |
| 580 | u32 *rx; |
| 581 | const u32 *tx; |
| 582 | |
| 583 | rx = xfer->rx_buf; |
| 584 | tx = xfer->tx_buf; |
| 585 | do { |
Kalle Valo | feed9ba | 2008-01-24 14:00:40 -0800 | [diff] [blame] | 586 | c -= 4; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 587 | if (tx != NULL) { |
| 588 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 589 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 590 | dev_err(&spi->dev, "TXS timed out\n"); |
| 591 | goto out; |
| 592 | } |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 593 | dev_vdbg(&spi->dev, "write-%d %08x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 594 | word_len, *tx); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 595 | __raw_writel(*tx++, tx_reg); |
| 596 | } |
| 597 | if (rx != NULL) { |
| 598 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 599 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 600 | dev_err(&spi->dev, "RXS timed out\n"); |
| 601 | goto out; |
| 602 | } |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 603 | |
| 604 | if (c == 4 && tx == NULL && |
| 605 | (l & OMAP2_MCSPI_CHCONF_TURBO)) { |
| 606 | omap2_mcspi_set_enable(spi, 0); |
| 607 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 608 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 609 | word_len, *(rx - 1)); |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 610 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 611 | OMAP2_MCSPI_CHSTAT_RXS) < 0) { |
| 612 | dev_err(&spi->dev, |
| 613 | "RXS timed out\n"); |
| 614 | goto out; |
| 615 | } |
| 616 | c = 0; |
| 617 | } else if (c == 0 && tx == NULL) { |
| 618 | omap2_mcspi_set_enable(spi, 0); |
| 619 | } |
| 620 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 621 | *rx++ = __raw_readl(rx_reg); |
Felipe Balbi | 079a176 | 2010-09-29 17:31:29 +0900 | [diff] [blame] | 622 | dev_vdbg(&spi->dev, "read-%d %08x\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 623 | word_len, *(rx - 1)); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 624 | } |
Jarkko Nikula | 95c5c3a | 2011-03-21 16:27:30 +0200 | [diff] [blame] | 625 | } while (c >= 4); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 626 | } |
| 627 | |
| 628 | /* for TX_ONLY mode, be sure all words have shifted out */ |
| 629 | if (xfer->rx_buf == NULL) { |
| 630 | if (mcspi_wait_for_reg_bit(chstat_reg, |
| 631 | OMAP2_MCSPI_CHSTAT_TXS) < 0) { |
| 632 | dev_err(&spi->dev, "TXS timed out\n"); |
| 633 | } else if (mcspi_wait_for_reg_bit(chstat_reg, |
| 634 | OMAP2_MCSPI_CHSTAT_EOT) < 0) |
| 635 | dev_err(&spi->dev, "EOT timed out\n"); |
Jason Wang | e1993ed | 2010-10-19 18:03:27 +0800 | [diff] [blame] | 636 | |
| 637 | /* disable chan to purge rx datas received in TX_ONLY transfer, |
| 638 | * otherwise these rx datas will affect the direct following |
| 639 | * RX_ONLY transfer. |
| 640 | */ |
| 641 | omap2_mcspi_set_enable(spi, 0); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 642 | } |
| 643 | out: |
Roman Tereshonkov | 4743a0f | 2010-04-13 10:41:51 +0000 | [diff] [blame] | 644 | omap2_mcspi_set_enable(spi, 1); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 645 | return count - c; |
| 646 | } |
| 647 | |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 648 | static u32 omap2_mcspi_calc_divisor(u32 speed_hz) |
| 649 | { |
| 650 | u32 div; |
| 651 | |
| 652 | for (div = 0; div < 15; div++) |
| 653 | if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div)) |
| 654 | return div; |
| 655 | |
| 656 | return 15; |
| 657 | } |
| 658 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 659 | /* called only when no transfer is active to this device */ |
| 660 | static int omap2_mcspi_setup_transfer(struct spi_device *spi, |
| 661 | struct spi_transfer *t) |
| 662 | { |
| 663 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 664 | struct omap2_mcspi *mcspi; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 665 | struct spi_master *spi_cntrl; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 666 | u32 l = 0, div = 0; |
| 667 | u8 word_len = spi->bits_per_word; |
Scott Ellis | 9bd4517 | 2010-03-10 14:23:13 -0700 | [diff] [blame] | 668 | u32 speed_hz = spi->max_speed_hz; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 669 | |
| 670 | mcspi = spi_master_get_devdata(spi->master); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 671 | spi_cntrl = mcspi->master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 672 | |
| 673 | if (t != NULL && t->bits_per_word) |
| 674 | word_len = t->bits_per_word; |
| 675 | |
| 676 | cs->word_len = word_len; |
| 677 | |
Scott Ellis | 9bd4517 | 2010-03-10 14:23:13 -0700 | [diff] [blame] | 678 | if (t && t->speed_hz) |
| 679 | speed_hz = t->speed_hz; |
| 680 | |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 681 | speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ); |
| 682 | div = omap2_mcspi_calc_divisor(speed_hz); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 683 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 684 | l = mcspi_cached_chconf0(spi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 685 | |
| 686 | /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS |
| 687 | * REVISIT: this controller could support SPI_3WIRE mode. |
| 688 | */ |
| 689 | l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1); |
| 690 | l |= OMAP2_MCSPI_CHCONF_DPE0; |
| 691 | |
| 692 | /* wordlength */ |
| 693 | l &= ~OMAP2_MCSPI_CHCONF_WL_MASK; |
| 694 | l |= (word_len - 1) << 7; |
| 695 | |
| 696 | /* set chipselect polarity; manage with FORCE */ |
| 697 | if (!(spi->mode & SPI_CS_HIGH)) |
| 698 | l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ |
| 699 | else |
| 700 | l &= ~OMAP2_MCSPI_CHCONF_EPOL; |
| 701 | |
| 702 | /* set clock divisor */ |
| 703 | l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK; |
| 704 | l |= div << 2; |
| 705 | |
| 706 | /* set SPI mode 0..3 */ |
| 707 | if (spi->mode & SPI_CPOL) |
| 708 | l |= OMAP2_MCSPI_CHCONF_POL; |
| 709 | else |
| 710 | l &= ~OMAP2_MCSPI_CHCONF_POL; |
| 711 | if (spi->mode & SPI_CPHA) |
| 712 | l |= OMAP2_MCSPI_CHCONF_PHA; |
| 713 | else |
| 714 | l &= ~OMAP2_MCSPI_CHCONF_PHA; |
| 715 | |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 716 | mcspi_write_chconf0(spi, l); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 717 | |
| 718 | dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 719 | OMAP2_MCSPI_MAX_FREQ >> div, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 720 | (spi->mode & SPI_CPHA) ? "trailing" : "leading", |
| 721 | (spi->mode & SPI_CPOL) ? "inverted" : "normal"); |
| 722 | |
| 723 | return 0; |
| 724 | } |
| 725 | |
| 726 | static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data) |
| 727 | { |
| 728 | struct spi_device *spi = data; |
| 729 | struct omap2_mcspi *mcspi; |
| 730 | struct omap2_mcspi_dma *mcspi_dma; |
| 731 | |
| 732 | mcspi = spi_master_get_devdata(spi->master); |
| 733 | mcspi_dma = &(mcspi->dma_channels[spi->chip_select]); |
| 734 | |
| 735 | complete(&mcspi_dma->dma_rx_completion); |
| 736 | |
| 737 | /* We must disable the DMA RX request */ |
| 738 | omap2_mcspi_set_dma_req(spi, 1, 0); |
| 739 | } |
| 740 | |
| 741 | static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data) |
| 742 | { |
| 743 | struct spi_device *spi = data; |
| 744 | struct omap2_mcspi *mcspi; |
| 745 | struct omap2_mcspi_dma *mcspi_dma; |
| 746 | |
| 747 | mcspi = spi_master_get_devdata(spi->master); |
| 748 | mcspi_dma = &(mcspi->dma_channels[spi->chip_select]); |
| 749 | |
| 750 | complete(&mcspi_dma->dma_tx_completion); |
| 751 | |
| 752 | /* We must disable the DMA TX request */ |
| 753 | omap2_mcspi_set_dma_req(spi, 0, 0); |
| 754 | } |
| 755 | |
| 756 | static int omap2_mcspi_request_dma(struct spi_device *spi) |
| 757 | { |
| 758 | struct spi_master *master = spi->master; |
| 759 | struct omap2_mcspi *mcspi; |
| 760 | struct omap2_mcspi_dma *mcspi_dma; |
| 761 | |
| 762 | mcspi = spi_master_get_devdata(master); |
| 763 | mcspi_dma = mcspi->dma_channels + spi->chip_select; |
| 764 | |
| 765 | if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX", |
| 766 | omap2_mcspi_dma_rx_callback, spi, |
| 767 | &mcspi_dma->dma_rx_channel)) { |
| 768 | dev_err(&spi->dev, "no RX DMA channel for McSPI\n"); |
| 769 | return -EAGAIN; |
| 770 | } |
| 771 | |
| 772 | if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX", |
| 773 | omap2_mcspi_dma_tx_callback, spi, |
| 774 | &mcspi_dma->dma_tx_channel)) { |
| 775 | omap_free_dma(mcspi_dma->dma_rx_channel); |
| 776 | mcspi_dma->dma_rx_channel = -1; |
| 777 | dev_err(&spi->dev, "no TX DMA channel for McSPI\n"); |
| 778 | return -EAGAIN; |
| 779 | } |
| 780 | |
| 781 | init_completion(&mcspi_dma->dma_rx_completion); |
| 782 | init_completion(&mcspi_dma->dma_tx_completion); |
| 783 | |
| 784 | return 0; |
| 785 | } |
| 786 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 787 | static int omap2_mcspi_setup(struct spi_device *spi) |
| 788 | { |
| 789 | int ret; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 790 | struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); |
| 791 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 792 | struct omap2_mcspi_dma *mcspi_dma; |
| 793 | struct omap2_mcspi_cs *cs = spi->controller_state; |
| 794 | |
David Brownell | 7d07719 | 2009-06-17 16:26:03 -0700 | [diff] [blame] | 795 | if (spi->bits_per_word < 4 || spi->bits_per_word > 32) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 796 | dev_dbg(&spi->dev, "setup: unsupported %d bit words\n", |
| 797 | spi->bits_per_word); |
| 798 | return -EINVAL; |
| 799 | } |
| 800 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 801 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 802 | |
| 803 | if (!cs) { |
Russell King | 10aa5a3 | 2012-06-18 11:27:04 +0100 | [diff] [blame] | 804 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 805 | if (!cs) |
| 806 | return -ENOMEM; |
| 807 | cs->base = mcspi->base + spi->chip_select * 0x14; |
Russell King | e5480b73 | 2008-09-01 21:51:50 +0100 | [diff] [blame] | 808 | cs->phys = mcspi->phys + spi->chip_select * 0x14; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 809 | cs->chconf0 = 0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 810 | spi->controller_state = cs; |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 811 | /* Link this to context save list */ |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 812 | list_add_tail(&cs->node, &ctx->cs); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 813 | } |
| 814 | |
| 815 | if (mcspi_dma->dma_rx_channel == -1 |
| 816 | || mcspi_dma->dma_tx_channel == -1) { |
| 817 | ret = omap2_mcspi_request_dma(spi); |
| 818 | if (ret < 0) |
| 819 | return ret; |
| 820 | } |
| 821 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 822 | ret = omap2_mcspi_enable_clocks(mcspi); |
| 823 | if (ret < 0) |
| 824 | return ret; |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 825 | |
Kyungmin Park | 86eeb6f | 2007-10-16 01:27:45 -0700 | [diff] [blame] | 826 | ret = omap2_mcspi_setup_transfer(spi, NULL); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 827 | omap2_mcspi_disable_clocks(mcspi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 828 | |
| 829 | return ret; |
| 830 | } |
| 831 | |
| 832 | static void omap2_mcspi_cleanup(struct spi_device *spi) |
| 833 | { |
| 834 | struct omap2_mcspi *mcspi; |
| 835 | struct omap2_mcspi_dma *mcspi_dma; |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 836 | struct omap2_mcspi_cs *cs; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 837 | |
| 838 | mcspi = spi_master_get_devdata(spi->master); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 839 | |
Scott Ellis | 5e77494 | 2010-03-10 14:22:45 -0700 | [diff] [blame] | 840 | if (spi->controller_state) { |
| 841 | /* Unlink controller state from context save list */ |
| 842 | cs = spi->controller_state; |
| 843 | list_del(&cs->node); |
Tero Kristo | 89c0537 | 2009-09-22 16:46:17 -0700 | [diff] [blame] | 844 | |
Russell King | 10aa5a3 | 2012-06-18 11:27:04 +0100 | [diff] [blame] | 845 | kfree(cs); |
Scott Ellis | 5e77494 | 2010-03-10 14:22:45 -0700 | [diff] [blame] | 846 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 847 | |
Scott Ellis | 99f1a43 | 2010-05-24 14:20:27 +0000 | [diff] [blame] | 848 | if (spi->chip_select < spi->master->num_chipselect) { |
| 849 | mcspi_dma = &mcspi->dma_channels[spi->chip_select]; |
| 850 | |
| 851 | if (mcspi_dma->dma_rx_channel != -1) { |
| 852 | omap_free_dma(mcspi_dma->dma_rx_channel); |
| 853 | mcspi_dma->dma_rx_channel = -1; |
| 854 | } |
| 855 | if (mcspi_dma->dma_tx_channel != -1) { |
| 856 | omap_free_dma(mcspi_dma->dma_tx_channel); |
| 857 | mcspi_dma->dma_tx_channel = -1; |
| 858 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 859 | } |
| 860 | } |
| 861 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 862 | static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 863 | { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 864 | |
| 865 | /* We only enable one channel at a time -- the one whose message is |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 866 | * -- although this controller would gladly |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 867 | * arbitrate among multiple channels. This corresponds to "single |
| 868 | * channel" master mode. As a side effect, we need to manage the |
| 869 | * chipselect with the FORCE bit ... CS != channel enable. |
| 870 | */ |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 871 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 872 | struct spi_device *spi; |
| 873 | struct spi_transfer *t = NULL; |
| 874 | int cs_active = 0; |
| 875 | struct omap2_mcspi_cs *cs; |
| 876 | struct omap2_mcspi_device_config *cd; |
| 877 | int par_override = 0; |
| 878 | int status = 0; |
| 879 | u32 chconf; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 880 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 881 | spi = m->spi; |
| 882 | cs = spi->controller_state; |
| 883 | cd = spi->controller_data; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 884 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 885 | omap2_mcspi_set_enable(spi, 1); |
| 886 | list_for_each_entry(t, &m->transfers, transfer_list) { |
| 887 | if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { |
| 888 | status = -EINVAL; |
| 889 | break; |
| 890 | } |
| 891 | if (par_override || t->speed_hz || t->bits_per_word) { |
| 892 | par_override = 1; |
| 893 | status = omap2_mcspi_setup_transfer(spi, t); |
| 894 | if (status < 0) |
| 895 | break; |
| 896 | if (!t->speed_hz && !t->bits_per_word) |
| 897 | par_override = 0; |
| 898 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 899 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 900 | if (!cs_active) { |
| 901 | omap2_mcspi_force_cs(spi, 1); |
| 902 | cs_active = 1; |
| 903 | } |
| 904 | |
| 905 | chconf = mcspi_cached_chconf0(spi); |
| 906 | chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; |
| 907 | chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; |
| 908 | |
| 909 | if (t->tx_buf == NULL) |
| 910 | chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY; |
| 911 | else if (t->rx_buf == NULL) |
| 912 | chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY; |
| 913 | |
| 914 | if (cd && cd->turbo_mode && t->tx_buf == NULL) { |
| 915 | /* Turbo mode is for more than one word */ |
| 916 | if (t->len > ((cs->word_len + 7) >> 3)) |
| 917 | chconf |= OMAP2_MCSPI_CHCONF_TURBO; |
| 918 | } |
| 919 | |
| 920 | mcspi_write_chconf0(spi, chconf); |
| 921 | |
| 922 | if (t->len) { |
| 923 | unsigned count; |
| 924 | |
| 925 | /* RX_ONLY mode needs dummy data in TX reg */ |
| 926 | if (t->tx_buf == NULL) |
| 927 | __raw_writel(0, cs->base |
| 928 | + OMAP2_MCSPI_TX0); |
| 929 | |
| 930 | if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES) |
| 931 | count = omap2_mcspi_txrx_dma(spi, t); |
| 932 | else |
| 933 | count = omap2_mcspi_txrx_pio(spi, t); |
| 934 | m->actual_length += count; |
| 935 | |
| 936 | if (count != t->len) { |
| 937 | status = -EIO; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 938 | break; |
| 939 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 940 | } |
| 941 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 942 | if (t->delay_usecs) |
| 943 | udelay(t->delay_usecs); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 944 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 945 | /* ignore the "leave it on after last xfer" hint */ |
| 946 | if (t->cs_change) { |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 947 | omap2_mcspi_force_cs(spi, 0); |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 948 | cs_active = 0; |
| 949 | } |
| 950 | } |
| 951 | /* Restore defaults if they were overriden */ |
| 952 | if (par_override) { |
| 953 | par_override = 0; |
| 954 | status = omap2_mcspi_setup_transfer(spi, NULL); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 955 | } |
| 956 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 957 | if (cs_active) |
| 958 | omap2_mcspi_force_cs(spi, 0); |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 959 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 960 | omap2_mcspi_set_enable(spi, 0); |
| 961 | |
| 962 | m->status = status; |
| 963 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 964 | } |
| 965 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 966 | static int omap2_mcspi_transfer_one_message(struct spi_master *master, |
| 967 | struct spi_message *m) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 968 | { |
| 969 | struct omap2_mcspi *mcspi; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 970 | struct spi_transfer *t; |
| 971 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 972 | mcspi = spi_master_get_devdata(master); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 973 | m->actual_length = 0; |
| 974 | m->status = 0; |
| 975 | |
| 976 | /* reject invalid messages and transfers */ |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 977 | if (list_empty(&m->transfers)) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 978 | return -EINVAL; |
| 979 | list_for_each_entry(t, &m->transfers, transfer_list) { |
| 980 | const void *tx_buf = t->tx_buf; |
| 981 | void *rx_buf = t->rx_buf; |
| 982 | unsigned len = t->len; |
| 983 | |
| 984 | if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ |
| 985 | || (len && !(rx_buf || tx_buf)) |
| 986 | || (t->bits_per_word && |
| 987 | ( t->bits_per_word < 4 |
| 988 | || t->bits_per_word > 32))) { |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 989 | dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 990 | t->speed_hz, |
| 991 | len, |
| 992 | tx_buf ? "tx" : "", |
| 993 | rx_buf ? "rx" : "", |
| 994 | t->bits_per_word); |
| 995 | return -EINVAL; |
| 996 | } |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 997 | if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) { |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 998 | dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n", |
Hannu Heikkinen | 57d9c10 | 2011-02-24 21:31:33 +0200 | [diff] [blame] | 999 | t->speed_hz, |
| 1000 | OMAP2_MCSPI_MAX_FREQ >> 15); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1001 | return -EINVAL; |
| 1002 | } |
| 1003 | |
| 1004 | if (m->is_dma_mapped || len < DMA_MIN_BYTES) |
| 1005 | continue; |
| 1006 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1007 | if (tx_buf != NULL) { |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1008 | t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1009 | len, DMA_TO_DEVICE); |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1010 | if (dma_mapping_error(mcspi->dev, t->tx_dma)) { |
| 1011 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1012 | 'T', len); |
| 1013 | return -EINVAL; |
| 1014 | } |
| 1015 | } |
| 1016 | if (rx_buf != NULL) { |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1017 | t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1018 | DMA_FROM_DEVICE); |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1019 | if (dma_mapping_error(mcspi->dev, t->rx_dma)) { |
| 1020 | dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1021 | 'R', len); |
| 1022 | if (tx_buf != NULL) |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1023 | dma_unmap_single(mcspi->dev, t->tx_dma, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1024 | len, DMA_TO_DEVICE); |
| 1025 | return -EINVAL; |
| 1026 | } |
| 1027 | } |
| 1028 | } |
| 1029 | |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1030 | omap2_mcspi_work(mcspi, m); |
| 1031 | spi_finalize_current_message(master); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1032 | return 0; |
| 1033 | } |
| 1034 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1035 | static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1036 | { |
| 1037 | struct spi_master *master = mcspi->master; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1038 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1039 | int ret = 0; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1040 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1041 | ret = omap2_mcspi_enable_clocks(mcspi); |
| 1042 | if (ret < 0) |
| 1043 | return ret; |
Jouni Hogander | ddb2219 | 2009-07-29 15:02:11 -0700 | [diff] [blame] | 1044 | |
Shubhrajyoti D | 39f8052 | 2012-03-29 22:11:07 +0530 | [diff] [blame] | 1045 | mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, |
| 1046 | OMAP2_MCSPI_WAKEUPENABLE_WKEN); |
| 1047 | ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1048 | |
| 1049 | omap2_mcspi_set_master_mode(master); |
Hemanth V | a41ae1a | 2009-09-22 16:46:16 -0700 | [diff] [blame] | 1050 | omap2_mcspi_disable_clocks(mcspi); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1051 | return 0; |
| 1052 | } |
| 1053 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1054 | static int omap_mcspi_runtime_resume(struct device *dev) |
| 1055 | { |
| 1056 | struct omap2_mcspi *mcspi; |
| 1057 | struct spi_master *master; |
| 1058 | |
| 1059 | master = dev_get_drvdata(dev); |
| 1060 | mcspi = spi_master_get_devdata(master); |
| 1061 | omap2_mcspi_restore_ctx(mcspi); |
| 1062 | |
| 1063 | return 0; |
| 1064 | } |
| 1065 | |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1066 | static struct omap2_mcspi_platform_config omap2_pdata = { |
| 1067 | .regs_offset = 0, |
| 1068 | }; |
| 1069 | |
| 1070 | static struct omap2_mcspi_platform_config omap4_pdata = { |
| 1071 | .regs_offset = OMAP4_MCSPI_REG_OFFSET, |
| 1072 | }; |
| 1073 | |
| 1074 | static const struct of_device_id omap_mcspi_of_match[] = { |
| 1075 | { |
| 1076 | .compatible = "ti,omap2-mcspi", |
| 1077 | .data = &omap2_pdata, |
| 1078 | }, |
| 1079 | { |
| 1080 | .compatible = "ti,omap4-mcspi", |
| 1081 | .data = &omap4_pdata, |
| 1082 | }, |
| 1083 | { }, |
| 1084 | }; |
| 1085 | MODULE_DEVICE_TABLE(of, omap_mcspi_of_match); |
Girish | ccc7bae | 2008-02-06 01:38:16 -0800 | [diff] [blame] | 1086 | |
Felipe Balbi | 7d6b6d8 | 2012-03-14 11:18:30 +0200 | [diff] [blame] | 1087 | static int __devinit omap2_mcspi_probe(struct platform_device *pdev) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1088 | { |
| 1089 | struct spi_master *master; |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1090 | struct omap2_mcspi_platform_config *pdata; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1091 | struct omap2_mcspi *mcspi; |
| 1092 | struct resource *r; |
| 1093 | int status = 0, i; |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1094 | u32 regs_offset = 0; |
| 1095 | static int bus_num = 1; |
| 1096 | struct device_node *node = pdev->dev.of_node; |
| 1097 | const struct of_device_id *match; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1098 | |
| 1099 | master = spi_alloc_master(&pdev->dev, sizeof *mcspi); |
| 1100 | if (master == NULL) { |
| 1101 | dev_dbg(&pdev->dev, "master allocation failed\n"); |
| 1102 | return -ENOMEM; |
| 1103 | } |
| 1104 | |
David Brownell | e7db06b | 2009-06-17 16:26:04 -0700 | [diff] [blame] | 1105 | /* the spi->mode bits understood by this driver: */ |
| 1106 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
| 1107 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1108 | master->setup = omap2_mcspi_setup; |
Shubhrajyoti D | 5fda88f | 2012-05-10 18:27:45 +0530 | [diff] [blame] | 1109 | master->prepare_transfer_hardware = omap2_prepare_transfer; |
| 1110 | master->unprepare_transfer_hardware = omap2_unprepare_transfer; |
| 1111 | master->transfer_one_message = omap2_mcspi_transfer_one_message; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1112 | master->cleanup = omap2_mcspi_cleanup; |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1113 | master->dev.of_node = node; |
| 1114 | |
| 1115 | match = of_match_device(omap_mcspi_of_match, &pdev->dev); |
| 1116 | if (match) { |
| 1117 | u32 num_cs = 1; /* default number of chipselect */ |
| 1118 | pdata = match->data; |
| 1119 | |
| 1120 | of_property_read_u32(node, "ti,spi-num-cs", &num_cs); |
| 1121 | master->num_chipselect = num_cs; |
| 1122 | master->bus_num = bus_num++; |
| 1123 | } else { |
| 1124 | pdata = pdev->dev.platform_data; |
| 1125 | master->num_chipselect = pdata->num_cs; |
| 1126 | if (pdev->id != -1) |
| 1127 | master->bus_num = pdev->id; |
| 1128 | } |
| 1129 | regs_offset = pdata->regs_offset; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1130 | |
| 1131 | dev_set_drvdata(&pdev->dev, master); |
| 1132 | |
| 1133 | mcspi = spi_master_get_devdata(master); |
| 1134 | mcspi->master = master; |
| 1135 | |
| 1136 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1137 | if (r == NULL) { |
| 1138 | status = -ENODEV; |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1139 | goto free_master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1140 | } |
Shubhrajyoti D | 1458d16 | 2011-10-24 15:54:24 +0530 | [diff] [blame] | 1141 | |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1142 | r->start += regs_offset; |
| 1143 | r->end += regs_offset; |
Shubhrajyoti D | 1458d16 | 2011-10-24 15:54:24 +0530 | [diff] [blame] | 1144 | mcspi->phys = r->start; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1145 | |
Shubhrajyoti D | 1a77b12 | 2012-03-17 12:44:01 +0530 | [diff] [blame] | 1146 | mcspi->base = devm_request_and_ioremap(&pdev->dev, r); |
Russell King | 55c381e | 2008-09-04 14:07:22 +0100 | [diff] [blame] | 1147 | if (!mcspi->base) { |
| 1148 | dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); |
| 1149 | status = -ENOMEM; |
Shubhrajyoti D | 1a77b12 | 2012-03-17 12:44:01 +0530 | [diff] [blame] | 1150 | goto free_master; |
Russell King | 55c381e | 2008-09-04 14:07:22 +0100 | [diff] [blame] | 1151 | } |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1152 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1153 | mcspi->dev = &pdev->dev; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1154 | |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1155 | INIT_LIST_HEAD(&mcspi->ctx.cs); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1156 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1157 | mcspi->dma_channels = kcalloc(master->num_chipselect, |
| 1158 | sizeof(struct omap2_mcspi_dma), |
| 1159 | GFP_KERNEL); |
| 1160 | |
| 1161 | if (mcspi->dma_channels == NULL) |
Shubhrajyoti D | 1a77b12 | 2012-03-17 12:44:01 +0530 | [diff] [blame] | 1162 | goto free_master; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1163 | |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1164 | for (i = 0; i < master->num_chipselect; i++) { |
| 1165 | char dma_ch_name[14]; |
| 1166 | struct resource *dma_res; |
| 1167 | |
| 1168 | sprintf(dma_ch_name, "rx%d", i); |
| 1169 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, |
| 1170 | dma_ch_name); |
| 1171 | if (!dma_res) { |
| 1172 | dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); |
| 1173 | status = -ENODEV; |
| 1174 | break; |
| 1175 | } |
| 1176 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1177 | mcspi->dma_channels[i].dma_rx_channel = -1; |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1178 | mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; |
| 1179 | sprintf(dma_ch_name, "tx%d", i); |
| 1180 | dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, |
| 1181 | dma_ch_name); |
| 1182 | if (!dma_res) { |
| 1183 | dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); |
| 1184 | status = -ENODEV; |
| 1185 | break; |
| 1186 | } |
| 1187 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1188 | mcspi->dma_channels[i].dma_tx_channel = -1; |
Charulatha V | 1a5d819 | 2011-02-02 17:52:14 +0530 | [diff] [blame] | 1189 | mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1190 | } |
| 1191 | |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1192 | if (status < 0) |
| 1193 | goto dma_chnl_free; |
| 1194 | |
Shubhrajyoti D | 27b5284 | 2012-03-26 17:04:22 +0530 | [diff] [blame] | 1195 | pm_runtime_use_autosuspend(&pdev->dev); |
| 1196 | pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1197 | pm_runtime_enable(&pdev->dev); |
| 1198 | |
| 1199 | if (status || omap2_mcspi_master_setup(mcspi) < 0) |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1200 | goto disable_pm; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1201 | |
| 1202 | status = spi_register_master(master); |
| 1203 | if (status < 0) |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1204 | goto err_spi_register; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1205 | |
| 1206 | return status; |
| 1207 | |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1208 | err_spi_register: |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1209 | spi_master_put(master); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1210 | disable_pm: |
Shubhrajyoti D | 751c925 | 2011-10-28 17:14:18 +0530 | [diff] [blame] | 1211 | pm_runtime_disable(&pdev->dev); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1212 | dma_chnl_free: |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1213 | kfree(mcspi->dma_channels); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1214 | free_master: |
| 1215 | kfree(master); |
| 1216 | platform_set_drvdata(pdev, NULL); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1217 | return status; |
| 1218 | } |
| 1219 | |
Felipe Balbi | 7d6b6d8 | 2012-03-14 11:18:30 +0200 | [diff] [blame] | 1220 | static int __devexit omap2_mcspi_remove(struct platform_device *pdev) |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1221 | { |
| 1222 | struct spi_master *master; |
| 1223 | struct omap2_mcspi *mcspi; |
| 1224 | struct omap2_mcspi_dma *dma_channels; |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1225 | |
| 1226 | master = dev_get_drvdata(&pdev->dev); |
| 1227 | mcspi = spi_master_get_devdata(master); |
| 1228 | dma_channels = mcspi->dma_channels; |
| 1229 | |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1230 | omap2_mcspi_disable_clocks(mcspi); |
Shubhrajyoti D | 751c925 | 2011-10-28 17:14:18 +0530 | [diff] [blame] | 1231 | pm_runtime_disable(&pdev->dev); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1232 | |
| 1233 | spi_unregister_master(master); |
| 1234 | kfree(dma_channels); |
Shubhrajyoti D | 39f1b56 | 2011-10-28 17:14:19 +0530 | [diff] [blame] | 1235 | platform_set_drvdata(pdev, NULL); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1236 | |
| 1237 | return 0; |
| 1238 | } |
| 1239 | |
Kay Sievers | 7e38c3c | 2008-04-10 21:29:20 -0700 | [diff] [blame] | 1240 | /* work with hotplug and coldplug */ |
| 1241 | MODULE_ALIAS("platform:omap2_mcspi"); |
| 1242 | |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1243 | #ifdef CONFIG_SUSPEND |
| 1244 | /* |
| 1245 | * When SPI wake up from off-mode, CS is in activate state. If it was in |
| 1246 | * unactive state when driver was suspend, then force it to unactive state at |
| 1247 | * wake up. |
| 1248 | */ |
| 1249 | static int omap2_mcspi_resume(struct device *dev) |
| 1250 | { |
| 1251 | struct spi_master *master = dev_get_drvdata(dev); |
| 1252 | struct omap2_mcspi *mcspi = spi_master_get_devdata(master); |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1253 | struct omap2_mcspi_regs *ctx = &mcspi->ctx; |
| 1254 | struct omap2_mcspi_cs *cs; |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1255 | |
| 1256 | omap2_mcspi_enable_clocks(mcspi); |
Benoit Cousson | 1bd897f8 | 2012-03-26 15:32:33 +0530 | [diff] [blame] | 1257 | list_for_each_entry(cs, &ctx->cs, node) { |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1258 | if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1259 | /* |
| 1260 | * We need to toggle CS state for OMAP take this |
| 1261 | * change in account. |
| 1262 | */ |
| 1263 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1); |
| 1264 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
| 1265 | MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0); |
| 1266 | __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0); |
| 1267 | } |
| 1268 | } |
| 1269 | omap2_mcspi_disable_clocks(mcspi); |
| 1270 | return 0; |
| 1271 | } |
| 1272 | #else |
| 1273 | #define omap2_mcspi_resume NULL |
| 1274 | #endif |
| 1275 | |
| 1276 | static const struct dev_pm_ops omap2_mcspi_pm_ops = { |
| 1277 | .resume = omap2_mcspi_resume, |
Govindraj.R | 1f1a438 | 2011-02-02 17:52:15 +0530 | [diff] [blame] | 1278 | .runtime_resume = omap_mcspi_runtime_resume, |
Gregory CLEMENT | 42ce7fd | 2010-12-29 11:52:53 +0100 | [diff] [blame] | 1279 | }; |
| 1280 | |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1281 | static struct platform_driver omap2_mcspi_driver = { |
| 1282 | .driver = { |
| 1283 | .name = "omap2_mcspi", |
| 1284 | .owner = THIS_MODULE, |
Benoit Cousson | d5a8003 | 2012-02-15 18:37:34 +0100 | [diff] [blame] | 1285 | .pm = &omap2_mcspi_pm_ops, |
| 1286 | .of_match_table = omap_mcspi_of_match, |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1287 | }, |
Felipe Balbi | 7d6b6d8 | 2012-03-14 11:18:30 +0200 | [diff] [blame] | 1288 | .probe = omap2_mcspi_probe, |
| 1289 | .remove = __devexit_p(omap2_mcspi_remove), |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1290 | }; |
| 1291 | |
Felipe Balbi | 9fdca9d | 2012-03-14 11:18:31 +0200 | [diff] [blame] | 1292 | module_platform_driver(omap2_mcspi_driver); |
Samuel Ortiz | ccdc7bf | 2007-07-17 04:04:13 -0700 | [diff] [blame] | 1293 | MODULE_LICENSE("GPL"); |