blob: 5e3f1d8a4fb881138f63a56fa8ea6bf0c9b8c144 [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -07001/*
Michael Hennerich14b03202008-05-07 11:41:26 +08002 * Copyright 2004-2008 Analog Devices Inc.
Bryan Wu1394f032007-05-06 14:50:22 -07003 *
Michael Hennerich14b03202008-05-07 11:41:26 +08004 * Licensed under the GPL-2 or later.
Bryan Wu1394f032007-05-06 14:50:22 -07005 */
6
7#include <linux/linkage.h>
8#include <asm/blackfin.h>
9#include <asm/mach/irq.h>
Michael Hennerich1efc80b2008-07-19 16:57:32 +080010#include <asm/dpmc.h>
Bryan Wu1394f032007-05-06 14:50:22 -070011
12.section .l1.text
13
14ENTRY(_sleep_mode)
15 [--SP] = ( R7:0, P5:0 );
16 [--SP] = RETS;
17
18 call _set_sic_iwr;
19
20 R0 = 0xFFFF (Z);
Michael Hennerich4521ef42008-01-11 17:21:41 +080021 call _set_rtc_istat;
Bryan Wu1394f032007-05-06 14:50:22 -070022
23 P0.H = hi(PLL_CTL);
24 P0.L = lo(PLL_CTL);
25 R1 = W[P0](z);
26 BITSET (R1, 3);
27 W[P0] = R1.L;
28
29 CLI R2;
30 SSYNC;
31 IDLE;
32 STI R2;
33
34 call _test_pll_locked;
35
36 R0 = IWR_ENABLE(0);
Michael Hennerichcfefe3c2008-02-09 04:12:37 +080037 R1 = IWR_DISABLE_ALL;
38 R2 = IWR_DISABLE_ALL;
39
Bryan Wu1394f032007-05-06 14:50:22 -070040 call _set_sic_iwr;
41
42 P0.H = hi(PLL_CTL);
43 P0.L = lo(PLL_CTL);
44 R7 = w[p0](z);
45 BITCLR (R7, 3);
46 BITCLR (R7, 5);
47 w[p0] = R7.L;
48 IDLE;
49 call _test_pll_locked;
50
51 RETS = [SP++];
52 ( R7:0, P5:0 ) = [SP++];
53 RTS;
Mike Frysinger1a8caee2008-07-16 17:07:26 +080054ENDPROC(_sleep_mode)
Bryan Wu1394f032007-05-06 14:50:22 -070055
56ENTRY(_hibernate_mode)
57 [--SP] = ( R7:0, P5:0 );
58 [--SP] = RETS;
59
Michael Hennerich1efc80b2008-07-19 16:57:32 +080060 R3 = R0;
61 R0 = IWR_DISABLE_ALL;
62 R1 = IWR_DISABLE_ALL;
63 R2 = IWR_DISABLE_ALL;
Bryan Wu1394f032007-05-06 14:50:22 -070064 call _set_sic_iwr;
Michael Hennerich1efc80b2008-07-19 16:57:32 +080065 call _set_dram_srfs;
66 SSYNC;
Bryan Wu1394f032007-05-06 14:50:22 -070067
68 R0 = 0xFFFF (Z);
Michael Hennerich4521ef42008-01-11 17:21:41 +080069 call _set_rtc_istat;
Bryan Wu1394f032007-05-06 14:50:22 -070070
71 P0.H = hi(VR_CTL);
72 P0.L = lo(VR_CTL);
Bryan Wu1394f032007-05-06 14:50:22 -070073
Michael Hennerich1efc80b2008-07-19 16:57:32 +080074 W[P0] = R3.L;
Bryan Wu1394f032007-05-06 14:50:22 -070075 CLI R2;
76 IDLE;
Michael Hennerich1efc80b2008-07-19 16:57:32 +080077.Lforever:
78 jump .Lforever;
Mike Frysinger1a8caee2008-07-16 17:07:26 +080079ENDPROC(_hibernate_mode)
Bryan Wu1394f032007-05-06 14:50:22 -070080
81ENTRY(_deep_sleep)
82 [--SP] = ( R7:0, P5:0 );
83 [--SP] = RETS;
84
85 CLI R4;
86
Michael Hennerichcfefe3c2008-02-09 04:12:37 +080087 R0 = IWR_ENABLE(0);
88 R1 = IWR_DISABLE_ALL;
89 R2 = IWR_DISABLE_ALL;
90
Bryan Wu1394f032007-05-06 14:50:22 -070091 call _set_sic_iwr;
92
Sonic Zhangfb5f0042007-12-23 23:02:13 +080093 call _set_dram_srfs;
Bryan Wu1394f032007-05-06 14:50:22 -070094
95 /* Clear all the interrupts,bits sticky */
96 R0 = 0xFFFF (Z);
97 call _set_rtc_istat
98
99 P0.H = hi(PLL_CTL);
100 P0.L = lo(PLL_CTL);
101 R0 = W[P0](z);
102 BITSET (R0, 5);
103 W[P0] = R0.L;
104
105 call _test_pll_locked;
106
107 SSYNC;
108 IDLE;
109
Sonic Zhangfb5f0042007-12-23 23:02:13 +0800110 call _unset_dram_srfs;
Bryan Wu1394f032007-05-06 14:50:22 -0700111
112 call _test_pll_locked;
113
114 R0 = IWR_ENABLE(0);
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800115 R1 = IWR_DISABLE_ALL;
116 R2 = IWR_DISABLE_ALL;
117
Bryan Wu1394f032007-05-06 14:50:22 -0700118 call _set_sic_iwr;
119
120 P0.H = hi(PLL_CTL);
121 P0.L = lo(PLL_CTL);
122 R0 = w[p0](z);
123 BITCLR (R0, 3);
124 BITCLR (R0, 5);
125 BITCLR (R0, 8);
126 w[p0] = R0;
127 IDLE;
128 call _test_pll_locked;
129
130 STI R4;
131
132 RETS = [SP++];
133 ( R7:0, P5:0 ) = [SP++];
134 RTS;
Mike Frysinger1a8caee2008-07-16 17:07:26 +0800135ENDPROC(_deep_sleep)
Bryan Wu1394f032007-05-06 14:50:22 -0700136
137ENTRY(_sleep_deeper)
138 [--SP] = ( R7:0, P5:0 );
139 [--SP] = RETS;
140
141 CLI R4;
142
143 P3 = R0;
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800144 P4 = R1;
145 P5 = R2;
146
Bryan Wu1394f032007-05-06 14:50:22 -0700147 R0 = IWR_ENABLE(0);
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800148 R1 = IWR_DISABLE_ALL;
149 R2 = IWR_DISABLE_ALL;
150
Bryan Wu1394f032007-05-06 14:50:22 -0700151 call _set_sic_iwr;
Michael Hennerich4521ef42008-01-11 17:21:41 +0800152 call _set_dram_srfs; /* Set SDRAM Self Refresh */
Bryan Wu1394f032007-05-06 14:50:22 -0700153
154 /* Clear all the interrupts,bits sticky */
155 R0 = 0xFFFF (Z);
Michael Hennerich4521ef42008-01-11 17:21:41 +0800156 call _set_rtc_istat;
Bryan Wu1394f032007-05-06 14:50:22 -0700157 P0.H = hi(PLL_DIV);
158 P0.L = lo(PLL_DIV);
159 R6 = W[P0](z);
160 R0.L = 0xF;
Michael Hennerich4521ef42008-01-11 17:21:41 +0800161 W[P0] = R0.l; /* Set Max VCO to SCLK divider */
Bryan Wu1394f032007-05-06 14:50:22 -0700162
163 P0.H = hi(PLL_CTL);
164 P0.L = lo(PLL_CTL);
165 R5 = W[P0](z);
Robin Getzf16295e2007-08-03 18:07:17 +0800166 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
Michael Hennerich4521ef42008-01-11 17:21:41 +0800167 W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
Bryan Wu1394f032007-05-06 14:50:22 -0700168
169 SSYNC;
170 IDLE;
171
172 call _test_pll_locked;
173
174 P0.H = hi(VR_CTL);
175 P0.L = lo(VR_CTL);
176 R7 = W[P0](z);
177 R1 = 0x6;
178 R1 <<= 16;
179 R2 = 0x0404(Z);
180 R1 = R1|R2;
181
182 R2 = DEPOSIT(R7, R1);
Michael Hennerich4521ef42008-01-11 17:21:41 +0800183 W[P0] = R2; /* Set Min Core Voltage */
Bryan Wu1394f032007-05-06 14:50:22 -0700184
185 SSYNC;
186 IDLE;
187
188 call _test_pll_locked;
189
Michael Hennerich4521ef42008-01-11 17:21:41 +0800190 R0 = P3;
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800191 R1 = P4;
192 R3 = P5;
Michael Hennerich4521ef42008-01-11 17:21:41 +0800193 call _set_sic_iwr; /* Set Awake from IDLE */
194
Bryan Wu1394f032007-05-06 14:50:22 -0700195 P0.H = hi(PLL_CTL);
196 P0.L = lo(PLL_CTL);
197 R0 = W[P0](z);
198 BITSET (R0, 3);
Michael Hennerich4521ef42008-01-11 17:21:41 +0800199 W[P0] = R0.L; /* Turn CCLK OFF */
Bryan Wu1394f032007-05-06 14:50:22 -0700200 SSYNC;
201 IDLE;
202
203 call _test_pll_locked;
204
205 R0 = IWR_ENABLE(0);
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800206 R1 = IWR_DISABLE_ALL;
207 R2 = IWR_DISABLE_ALL;
208
Michael Hennerich4521ef42008-01-11 17:21:41 +0800209 call _set_sic_iwr; /* Set Awake from IDLE PLL */
Bryan Wu1394f032007-05-06 14:50:22 -0700210
211 P0.H = hi(VR_CTL);
212 P0.L = lo(VR_CTL);
213 W[P0]= R7;
214
215 SSYNC;
216 IDLE;
217
218 call _test_pll_locked;
219
220 P0.H = hi(PLL_DIV);
221 P0.L = lo(PLL_DIV);
Michael Hennerich4521ef42008-01-11 17:21:41 +0800222 W[P0]= R6; /* Restore CCLK and SCLK divider */
Bryan Wu1394f032007-05-06 14:50:22 -0700223
224 P0.H = hi(PLL_CTL);
225 P0.L = lo(PLL_CTL);
Michael Hennerich4521ef42008-01-11 17:21:41 +0800226 w[p0] = R5; /* Restore VCO multiplier */
Bryan Wu1394f032007-05-06 14:50:22 -0700227 IDLE;
228 call _test_pll_locked;
229
Michael Hennerich4521ef42008-01-11 17:21:41 +0800230 call _unset_dram_srfs; /* SDRAM Self Refresh Off */
Bryan Wu1394f032007-05-06 14:50:22 -0700231
232 STI R4;
233
234 RETS = [SP++];
235 ( R7:0, P5:0 ) = [SP++];
236 RTS;
Mike Frysinger1a8caee2008-07-16 17:07:26 +0800237ENDPROC(_sleep_deeper)
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800238
Sonic Zhangfb5f0042007-12-23 23:02:13 +0800239ENTRY(_set_dram_srfs)
240 /* set the dram to self refresh mode */
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800241 SSYNC;
242#if defined(EBIU_RSTCTL) /* DDR */
Sonic Zhangfb5f0042007-12-23 23:02:13 +0800243 P0.H = hi(EBIU_RSTCTL);
244 P0.L = lo(EBIU_RSTCTL);
245 R2 = [P0];
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800246 BITSET(R2, 3); /* SRREQ enter self-refresh mode */
Bryan Wu1394f032007-05-06 14:50:22 -0700247 [P0] = R2;
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800248 SSYNC;
2491:
Sonic Zhangfb5f0042007-12-23 23:02:13 +0800250 R2 = [P0];
251 CC = BITTST(R2, 4);
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800252 if !CC JUMP 1b;
253#else /* SDRAM */
254 P0.L = lo(EBIU_SDGCTL);
255 P0.H = hi(EBIU_SDGCTL);
256 R2 = [P0];
257 BITSET(R2, 24); /* SRFS enter self-refresh mode */
258 [P0] = R2;
259 SSYNC;
260
261 P0.L = lo(EBIU_SDSTAT);
262 P0.H = hi(EBIU_SDSTAT);
2631:
264 R2 = w[P0];
265 SSYNC;
266 cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
267 if !cc jump 1b;
268
269 P0.L = lo(EBIU_SDGCTL);
270 P0.H = hi(EBIU_SDGCTL);
271 R2 = [P0];
272 BITCLR(R2, 0); /* SCTLE disable CLKOUT */
273 [P0] = R2;
Sonic Zhangfb5f0042007-12-23 23:02:13 +0800274#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700275 RTS;
Mike Frysinger1a8caee2008-07-16 17:07:26 +0800276ENDPROC(_set_dram_srfs)
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800277
Sonic Zhangfb5f0042007-12-23 23:02:13 +0800278ENTRY(_unset_dram_srfs)
279 /* set the dram out of self refresh mode */
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800280#if defined(EBIU_RSTCTL) /* DDR */
Sonic Zhangfb5f0042007-12-23 23:02:13 +0800281 P0.H = hi(EBIU_RSTCTL);
282 P0.L = lo(EBIU_RSTCTL);
283 R2 = [P0];
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800284 BITCLR(R2, 3); /* clear SRREQ bit */
Bryan Wu1394f032007-05-06 14:50:22 -0700285 [P0] = R2;
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800286#elif defined(EBIU_SDGCTL) /* SDRAM */
287
288 P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
289 P0.H = hi(EBIU_SDGCTL);
290 R2 = [P0];
291 BITSET(R2, 0); /* SCTLE enable CLKOUT */
292 [P0] = R2
293 SSYNC;
294
295 P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
296 P0.H = hi(EBIU_SDGCTL);
297 R2 = [P0];
298 BITCLR(R2, 24); /* clear SRFS bit */
299 [P0] = R2
300#endif
301 SSYNC;
Bryan Wu1394f032007-05-06 14:50:22 -0700302 RTS;
Mike Frysinger1a8caee2008-07-16 17:07:26 +0800303ENDPROC(_unset_dram_srfs)
Bryan Wu1394f032007-05-06 14:50:22 -0700304
305ENTRY(_set_sic_iwr)
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800306#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
Sonic Zhangfb5f0042007-12-23 23:02:13 +0800307 P0.H = hi(SIC_IWR0);
308 P0.L = lo(SIC_IWR0);
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800309 P1.H = hi(SIC_IWR1);
310 P1.L = lo(SIC_IWR1);
311 [P1] = R1;
312#if defined(CONFIG_BF54x)
313 P1.H = hi(SIC_IWR2);
314 P1.L = lo(SIC_IWR2);
315 [P1] = R2;
316#endif
Sonic Zhangfb5f0042007-12-23 23:02:13 +0800317#else
Bryan Wu1394f032007-05-06 14:50:22 -0700318 P0.H = hi(SIC_IWR);
319 P0.L = lo(SIC_IWR);
Sonic Zhangfb5f0042007-12-23 23:02:13 +0800320#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700321 [P0] = R0;
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800322
Bryan Wu1394f032007-05-06 14:50:22 -0700323 SSYNC;
324 RTS;
Mike Frysinger1a8caee2008-07-16 17:07:26 +0800325ENDPROC(_set_sic_iwr)
Bryan Wu1394f032007-05-06 14:50:22 -0700326
327ENTRY(_set_rtc_istat)
Michael Hennerich39278192008-02-25 14:39:50 +0800328#ifndef CONFIG_BF561
Bryan Wu1394f032007-05-06 14:50:22 -0700329 P0.H = hi(RTC_ISTAT);
330 P0.L = lo(RTC_ISTAT);
331 w[P0] = R0.L;
332 SSYNC;
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800333#elif (ANOMALY_05000371)
334 nop;
335 nop;
336 nop;
337 nop;
Michael Hennerich39278192008-02-25 14:39:50 +0800338#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700339 RTS;
Mike Frysinger1a8caee2008-07-16 17:07:26 +0800340ENDPROC(_set_rtc_istat)
Bryan Wu1394f032007-05-06 14:50:22 -0700341
342ENTRY(_test_pll_locked)
343 P0.H = hi(PLL_STAT);
344 P0.L = lo(PLL_STAT);
3451:
346 R0 = W[P0] (Z);
347 CC = BITTST(R0,5);
348 IF !CC JUMP 1b;
349 RTS;
Mike Frysinger1a8caee2008-07-16 17:07:26 +0800350ENDPROC(_test_pll_locked)
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800351
352.section .text
353
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800354ENTRY(_do_hibernate)
355 [--SP] = ( R7:0, P5:0 );
356 [--SP] = RETS;
357 /* Save System MMRs */
358 R2 = R0;
359 P0.H = hi(PLL_CTL);
360 P0.L = lo(PLL_CTL);
361
362#ifdef SIC_IMASK0
363 PM_SYS_PUSH(SIC_IMASK0)
364#endif
365#ifdef SIC_IMASK1
366 PM_SYS_PUSH(SIC_IMASK1)
367#endif
368#ifdef SIC_IMASK2
369 PM_SYS_PUSH(SIC_IMASK2)
370#endif
371#ifdef SIC_IMASK
372 PM_SYS_PUSH(SIC_IMASK)
373#endif
374#ifdef SICA_IMASK0
375 PM_SYS_PUSH(SICA_IMASK0)
376#endif
377#ifdef SICA_IMASK1
378 PM_SYS_PUSH(SICA_IMASK1)
379#endif
380#ifdef SIC_IAR2
381 PM_SYS_PUSH(SIC_IAR0)
382 PM_SYS_PUSH(SIC_IAR1)
383 PM_SYS_PUSH(SIC_IAR2)
384#endif
385#ifdef SIC_IAR3
386 PM_SYS_PUSH(SIC_IAR3)
387#endif
388#ifdef SIC_IAR4
389 PM_SYS_PUSH(SIC_IAR4)
390 PM_SYS_PUSH(SIC_IAR5)
391 PM_SYS_PUSH(SIC_IAR6)
392#endif
393#ifdef SIC_IAR7
394 PM_SYS_PUSH(SIC_IAR7)
395#endif
396#ifdef SIC_IAR8
397 PM_SYS_PUSH(SIC_IAR8)
398 PM_SYS_PUSH(SIC_IAR9)
399 PM_SYS_PUSH(SIC_IAR10)
400 PM_SYS_PUSH(SIC_IAR11)
401#endif
402
403#ifdef SICA_IAR0
404 PM_SYS_PUSH(SICA_IAR0)
405 PM_SYS_PUSH(SICA_IAR1)
406 PM_SYS_PUSH(SICA_IAR2)
407 PM_SYS_PUSH(SICA_IAR3)
408 PM_SYS_PUSH(SICA_IAR4)
409 PM_SYS_PUSH(SICA_IAR5)
410 PM_SYS_PUSH(SICA_IAR6)
411 PM_SYS_PUSH(SICA_IAR7)
412#endif
413
414#ifdef SIC_IWR
415 PM_SYS_PUSH(SIC_IWR)
416#endif
417#ifdef SIC_IWR0
418 PM_SYS_PUSH(SIC_IWR0)
419#endif
420#ifdef SIC_IWR1
421 PM_SYS_PUSH(SIC_IWR1)
422#endif
423#ifdef SIC_IWR2
424 PM_SYS_PUSH(SIC_IWR2)
425#endif
426#ifdef SICA_IWR0
427 PM_SYS_PUSH(SICA_IWR0)
428#endif
429#ifdef SICA_IWR1
430 PM_SYS_PUSH(SICA_IWR1)
431#endif
432
433#ifdef PINT0_ASSIGN
434 PM_SYS_PUSH(PINT0_ASSIGN)
435 PM_SYS_PUSH(PINT1_ASSIGN)
436 PM_SYS_PUSH(PINT2_ASSIGN)
437 PM_SYS_PUSH(PINT3_ASSIGN)
438#endif
439
440 PM_SYS_PUSH(EBIU_AMBCTL0)
441 PM_SYS_PUSH(EBIU_AMBCTL1)
442 PM_SYS_PUSH16(EBIU_AMGCTL)
443
444#ifdef EBIU_FCTL
445 PM_SYS_PUSH(EBIU_MBSCTL)
446 PM_SYS_PUSH(EBIU_MODE)
447 PM_SYS_PUSH(EBIU_FCTL)
448#endif
449
450 PM_SYS_PUSH16(SYSCR)
451
452 /* Save Core MMRs */
453 P0.H = hi(SRAM_BASE_ADDRESS);
454 P0.L = lo(SRAM_BASE_ADDRESS);
455
456 PM_PUSH(DMEM_CONTROL)
457 PM_PUSH(DCPLB_ADDR0)
458 PM_PUSH(DCPLB_ADDR1)
459 PM_PUSH(DCPLB_ADDR2)
460 PM_PUSH(DCPLB_ADDR3)
461 PM_PUSH(DCPLB_ADDR4)
462 PM_PUSH(DCPLB_ADDR5)
463 PM_PUSH(DCPLB_ADDR6)
464 PM_PUSH(DCPLB_ADDR7)
465 PM_PUSH(DCPLB_ADDR8)
466 PM_PUSH(DCPLB_ADDR9)
467 PM_PUSH(DCPLB_ADDR10)
468 PM_PUSH(DCPLB_ADDR11)
469 PM_PUSH(DCPLB_ADDR12)
470 PM_PUSH(DCPLB_ADDR13)
471 PM_PUSH(DCPLB_ADDR14)
472 PM_PUSH(DCPLB_ADDR15)
473 PM_PUSH(DCPLB_DATA0)
474 PM_PUSH(DCPLB_DATA1)
475 PM_PUSH(DCPLB_DATA2)
476 PM_PUSH(DCPLB_DATA3)
477 PM_PUSH(DCPLB_DATA4)
478 PM_PUSH(DCPLB_DATA5)
479 PM_PUSH(DCPLB_DATA6)
480 PM_PUSH(DCPLB_DATA7)
481 PM_PUSH(DCPLB_DATA8)
482 PM_PUSH(DCPLB_DATA9)
483 PM_PUSH(DCPLB_DATA10)
484 PM_PUSH(DCPLB_DATA11)
485 PM_PUSH(DCPLB_DATA12)
486 PM_PUSH(DCPLB_DATA13)
487 PM_PUSH(DCPLB_DATA14)
488 PM_PUSH(DCPLB_DATA15)
489 PM_PUSH(IMEM_CONTROL)
490 PM_PUSH(ICPLB_ADDR0)
491 PM_PUSH(ICPLB_ADDR1)
492 PM_PUSH(ICPLB_ADDR2)
493 PM_PUSH(ICPLB_ADDR3)
494 PM_PUSH(ICPLB_ADDR4)
495 PM_PUSH(ICPLB_ADDR5)
496 PM_PUSH(ICPLB_ADDR6)
497 PM_PUSH(ICPLB_ADDR7)
498 PM_PUSH(ICPLB_ADDR8)
499 PM_PUSH(ICPLB_ADDR9)
500 PM_PUSH(ICPLB_ADDR10)
501 PM_PUSH(ICPLB_ADDR11)
502 PM_PUSH(ICPLB_ADDR12)
503 PM_PUSH(ICPLB_ADDR13)
504 PM_PUSH(ICPLB_ADDR14)
505 PM_PUSH(ICPLB_ADDR15)
506 PM_PUSH(ICPLB_DATA0)
507 PM_PUSH(ICPLB_DATA1)
508 PM_PUSH(ICPLB_DATA2)
509 PM_PUSH(ICPLB_DATA3)
510 PM_PUSH(ICPLB_DATA4)
511 PM_PUSH(ICPLB_DATA5)
512 PM_PUSH(ICPLB_DATA6)
513 PM_PUSH(ICPLB_DATA7)
514 PM_PUSH(ICPLB_DATA8)
515 PM_PUSH(ICPLB_DATA9)
516 PM_PUSH(ICPLB_DATA10)
517 PM_PUSH(ICPLB_DATA11)
518 PM_PUSH(ICPLB_DATA12)
519 PM_PUSH(ICPLB_DATA13)
520 PM_PUSH(ICPLB_DATA14)
521 PM_PUSH(ICPLB_DATA15)
522 PM_PUSH(EVT0)
523 PM_PUSH(EVT1)
524 PM_PUSH(EVT2)
525 PM_PUSH(EVT3)
526 PM_PUSH(EVT4)
527 PM_PUSH(EVT5)
528 PM_PUSH(EVT6)
529 PM_PUSH(EVT7)
530 PM_PUSH(EVT8)
531 PM_PUSH(EVT9)
532 PM_PUSH(EVT10)
533 PM_PUSH(EVT11)
534 PM_PUSH(EVT12)
535 PM_PUSH(EVT13)
536 PM_PUSH(EVT14)
537 PM_PUSH(EVT15)
538 PM_PUSH(IMASK)
539 PM_PUSH(ILAT)
540 PM_PUSH(IPRIO)
541 PM_PUSH(TCNTL)
542 PM_PUSH(TPERIOD)
543 PM_PUSH(TSCALE)
544 PM_PUSH(TCOUNT)
545 PM_PUSH(TBUFCTL)
546
547 /* Save Core Registers */
548 [--sp] = SYSCFG;
549 [--sp] = ( R7:0, P5:0 );
550 [--sp] = fp;
551 [--sp] = usp;
552
553 [--sp] = i0;
554 [--sp] = i1;
555 [--sp] = i2;
556 [--sp] = i3;
557
558 [--sp] = m0;
559 [--sp] = m1;
560 [--sp] = m2;
561 [--sp] = m3;
562
563 [--sp] = l0;
564 [--sp] = l1;
565 [--sp] = l2;
566 [--sp] = l3;
567
568 [--sp] = b0;
569 [--sp] = b1;
570 [--sp] = b2;
571 [--sp] = b3;
572 [--sp] = a0.x;
573 [--sp] = a0.w;
574 [--sp] = a1.x;
575 [--sp] = a1.w;
576
577 [--sp] = LC0;
578 [--sp] = LC1;
579 [--sp] = LT0;
580 [--sp] = LT1;
581 [--sp] = LB0;
582 [--sp] = LB1;
583
584 [--sp] = ASTAT;
585 [--sp] = CYCLES;
586 [--sp] = CYCLES2;
587
588 [--sp] = RETS;
589 r0 = RETI;
590 [--sp] = r0;
591 [--sp] = RETX;
592 [--sp] = RETN;
593 [--sp] = RETE;
594 [--sp] = SEQSTAT;
595
596 /* Save Magic, return address and Stack Pointer */
597 P0.H = 0;
598 P0.L = 0;
599 R0.H = 0xDEAD; /* Hibernate Magic */
600 R0.L = 0xBEEF;
601 [P0++] = R0; /* Store Hibernate Magic */
Mike Frysinger1a8caee2008-07-16 17:07:26 +0800602 R0.H = .Lpm_resume_here;
603 R0.L = .Lpm_resume_here;
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800604 [P0++] = R0; /* Save Return Address */
605 [P0++] = SP; /* Save Stack Pointer */
606 P0.H = _hibernate_mode;
607 P0.L = _hibernate_mode;
608 R0 = R2;
609 call (P0); /* Goodbye */
610
Mike Frysinger1a8caee2008-07-16 17:07:26 +0800611.Lpm_resume_here:
Michael Hennerich1efc80b2008-07-19 16:57:32 +0800612
613 /* Restore Core Registers */
614 SEQSTAT = [sp++];
615 RETE = [sp++];
616 RETN = [sp++];
617 RETX = [sp++];
618 r0 = [sp++];
619 RETI = r0;
620 RETS = [sp++];
621
622 CYCLES2 = [sp++];
623 CYCLES = [sp++];
624 ASTAT = [sp++];
625
626 LB1 = [sp++];
627 LB0 = [sp++];
628 LT1 = [sp++];
629 LT0 = [sp++];
630 LC1 = [sp++];
631 LC0 = [sp++];
632
633 a1.w = [sp++];
634 a1.x = [sp++];
635 a0.w = [sp++];
636 a0.x = [sp++];
637 b3 = [sp++];
638 b2 = [sp++];
639 b1 = [sp++];
640 b0 = [sp++];
641
642 l3 = [sp++];
643 l2 = [sp++];
644 l1 = [sp++];
645 l0 = [sp++];
646
647 m3 = [sp++];
648 m2 = [sp++];
649 m1 = [sp++];
650 m0 = [sp++];
651
652 i3 = [sp++];
653 i2 = [sp++];
654 i1 = [sp++];
655 i0 = [sp++];
656
657 usp = [sp++];
658 fp = [sp++];
659
660 ( R7 : 0, P5 : 0) = [ SP ++ ];
661 SYSCFG = [sp++];
662
663 /* Restore Core MMRs */
664
665 PM_POP(TBUFCTL)
666 PM_POP(TCOUNT)
667 PM_POP(TSCALE)
668 PM_POP(TPERIOD)
669 PM_POP(TCNTL)
670 PM_POP(IPRIO)
671 PM_POP(ILAT)
672 PM_POP(IMASK)
673 PM_POP(EVT15)
674 PM_POP(EVT14)
675 PM_POP(EVT13)
676 PM_POP(EVT12)
677 PM_POP(EVT11)
678 PM_POP(EVT10)
679 PM_POP(EVT9)
680 PM_POP(EVT8)
681 PM_POP(EVT7)
682 PM_POP(EVT6)
683 PM_POP(EVT5)
684 PM_POP(EVT4)
685 PM_POP(EVT3)
686 PM_POP(EVT2)
687 PM_POP(EVT1)
688 PM_POP(EVT0)
689 PM_POP(ICPLB_DATA15)
690 PM_POP(ICPLB_DATA14)
691 PM_POP(ICPLB_DATA13)
692 PM_POP(ICPLB_DATA12)
693 PM_POP(ICPLB_DATA11)
694 PM_POP(ICPLB_DATA10)
695 PM_POP(ICPLB_DATA9)
696 PM_POP(ICPLB_DATA8)
697 PM_POP(ICPLB_DATA7)
698 PM_POP(ICPLB_DATA6)
699 PM_POP(ICPLB_DATA5)
700 PM_POP(ICPLB_DATA4)
701 PM_POP(ICPLB_DATA3)
702 PM_POP(ICPLB_DATA2)
703 PM_POP(ICPLB_DATA1)
704 PM_POP(ICPLB_DATA0)
705 PM_POP(ICPLB_ADDR15)
706 PM_POP(ICPLB_ADDR14)
707 PM_POP(ICPLB_ADDR13)
708 PM_POP(ICPLB_ADDR12)
709 PM_POP(ICPLB_ADDR11)
710 PM_POP(ICPLB_ADDR10)
711 PM_POP(ICPLB_ADDR9)
712 PM_POP(ICPLB_ADDR8)
713 PM_POP(ICPLB_ADDR7)
714 PM_POP(ICPLB_ADDR6)
715 PM_POP(ICPLB_ADDR5)
716 PM_POP(ICPLB_ADDR4)
717 PM_POP(ICPLB_ADDR3)
718 PM_POP(ICPLB_ADDR2)
719 PM_POP(ICPLB_ADDR1)
720 PM_POP(ICPLB_ADDR0)
721 PM_POP(IMEM_CONTROL)
722 PM_POP(DCPLB_DATA15)
723 PM_POP(DCPLB_DATA14)
724 PM_POP(DCPLB_DATA13)
725 PM_POP(DCPLB_DATA12)
726 PM_POP(DCPLB_DATA11)
727 PM_POP(DCPLB_DATA10)
728 PM_POP(DCPLB_DATA9)
729 PM_POP(DCPLB_DATA8)
730 PM_POP(DCPLB_DATA7)
731 PM_POP(DCPLB_DATA6)
732 PM_POP(DCPLB_DATA5)
733 PM_POP(DCPLB_DATA4)
734 PM_POP(DCPLB_DATA3)
735 PM_POP(DCPLB_DATA2)
736 PM_POP(DCPLB_DATA1)
737 PM_POP(DCPLB_DATA0)
738 PM_POP(DCPLB_ADDR15)
739 PM_POP(DCPLB_ADDR14)
740 PM_POP(DCPLB_ADDR13)
741 PM_POP(DCPLB_ADDR12)
742 PM_POP(DCPLB_ADDR11)
743 PM_POP(DCPLB_ADDR10)
744 PM_POP(DCPLB_ADDR9)
745 PM_POP(DCPLB_ADDR8)
746 PM_POP(DCPLB_ADDR7)
747 PM_POP(DCPLB_ADDR6)
748 PM_POP(DCPLB_ADDR5)
749 PM_POP(DCPLB_ADDR4)
750 PM_POP(DCPLB_ADDR3)
751 PM_POP(DCPLB_ADDR2)
752 PM_POP(DCPLB_ADDR1)
753 PM_POP(DCPLB_ADDR0)
754 PM_POP(DMEM_CONTROL)
755
756 /* Restore System MMRs */
757
758 P0.H = hi(PLL_CTL);
759 P0.L = lo(PLL_CTL);
760 PM_SYS_POP16(SYSCR)
761
762#ifdef EBIU_FCTL
763 PM_SYS_POP(EBIU_FCTL)
764 PM_SYS_POP(EBIU_MODE)
765 PM_SYS_POP(EBIU_MBSCTL)
766#endif
767 PM_SYS_POP16(EBIU_AMGCTL)
768 PM_SYS_POP(EBIU_AMBCTL1)
769 PM_SYS_POP(EBIU_AMBCTL0)
770
771#ifdef PINT0_ASSIGN
772 PM_SYS_POP(PINT3_ASSIGN)
773 PM_SYS_POP(PINT2_ASSIGN)
774 PM_SYS_POP(PINT1_ASSIGN)
775 PM_SYS_POP(PINT0_ASSIGN)
776#endif
777
778#ifdef SICA_IWR1
779 PM_SYS_POP(SICA_IWR1)
780#endif
781#ifdef SICA_IWR0
782 PM_SYS_POP(SICA_IWR0)
783#endif
784#ifdef SIC_IWR2
785 PM_SYS_POP(SIC_IWR2)
786#endif
787#ifdef SIC_IWR1
788 PM_SYS_POP(SIC_IWR1)
789#endif
790#ifdef SIC_IWR0
791 PM_SYS_POP(SIC_IWR0)
792#endif
793#ifdef SIC_IWR
794 PM_SYS_POP(SIC_IWR)
795#endif
796
797#ifdef SICA_IAR0
798 PM_SYS_POP(SICA_IAR7)
799 PM_SYS_POP(SICA_IAR6)
800 PM_SYS_POP(SICA_IAR5)
801 PM_SYS_POP(SICA_IAR4)
802 PM_SYS_POP(SICA_IAR3)
803 PM_SYS_POP(SICA_IAR2)
804 PM_SYS_POP(SICA_IAR1)
805 PM_SYS_POP(SICA_IAR0)
806#endif
807
808#ifdef SIC_IAR8
809 PM_SYS_POP(SIC_IAR11)
810 PM_SYS_POP(SIC_IAR10)
811 PM_SYS_POP(SIC_IAR9)
812 PM_SYS_POP(SIC_IAR8)
813#endif
814#ifdef SIC_IAR7
815 PM_SYS_POP(SIC_IAR7)
816#endif
817#ifdef SIC_IAR6
818 PM_SYS_POP(SIC_IAR6)
819 PM_SYS_POP(SIC_IAR5)
820 PM_SYS_POP(SIC_IAR4)
821#endif
822#ifdef SIC_IAR3
823 PM_SYS_POP(SIC_IAR3)
824#endif
825#ifdef SIC_IAR2
826 PM_SYS_POP(SIC_IAR2)
827 PM_SYS_POP(SIC_IAR1)
828 PM_SYS_POP(SIC_IAR0)
829#endif
830#ifdef SICA_IMASK1
831 PM_SYS_POP(SICA_IMASK1)
832#endif
833#ifdef SICA_IMASK0
834 PM_SYS_POP(SICA_IMASK0)
835#endif
836#ifdef SIC_IMASK
837 PM_SYS_POP(SIC_IMASK)
838#endif
839#ifdef SIC_IMASK2
840 PM_SYS_POP(SIC_IMASK2)
841#endif
842#ifdef SIC_IMASK1
843 PM_SYS_POP(SIC_IMASK1)
844#endif
845#ifdef SIC_IMASK0
846 PM_SYS_POP(SIC_IMASK0)
847#endif
848
849 [--sp] = RETI; /* Clear Global Interrupt Disable */
850 SP += 4;
851
852 RETS = [SP++];
853 ( R7:0, P5:0 ) = [SP++];
854 RTS;
Mike Frysinger1a8caee2008-07-16 17:07:26 +0800855ENDPROC(_do_hibernate)