dmitry pervushin | 34acb09 | 2009-04-22 23:54:05 +0100 | [diff] [blame] | 1 | /* |
dmitry pervushin | 3f52326 | 2009-05-31 13:31:55 +0100 | [diff] [blame] | 2 | * stmp37xx: APBH register definitions |
dmitry pervushin | 34acb09 | 2009-04-22 23:54:05 +0100 | [diff] [blame] | 3 | * |
| 4 | * Copyright (c) 2008 Freescale Semiconductor |
| 5 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 20 | */ |
dmitry pervushin | 3f52326 | 2009-05-31 13:31:55 +0100 | [diff] [blame] | 21 | #ifndef _MACH_REGS_APBH |
| 22 | #define _MACH_REGS_APBH |
dmitry pervushin | 34acb09 | 2009-04-22 23:54:05 +0100 | [diff] [blame] | 23 | |
dmitry pervushin | 3f52326 | 2009-05-31 13:31:55 +0100 | [diff] [blame] | 24 | #define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000) |
dmitry pervushin | 34acb09 | 2009-04-22 23:54:05 +0100 | [diff] [blame] | 25 | |
dmitry pervushin | 3f52326 | 2009-05-31 13:31:55 +0100 | [diff] [blame] | 26 | #define HW_APBH_CTRL0 0x0 |
| 27 | #define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 |
| 28 | #define BP_APBH_CTRL0_RESET_CHANNEL 16 |
| 29 | #define BM_APBH_CTRL0_CLKGATE 0x40000000 |
| 30 | #define BM_APBH_CTRL0_SFTRST 0x80000000 |
dmitry pervushin | 34acb09 | 2009-04-22 23:54:05 +0100 | [diff] [blame] | 31 | |
dmitry pervushin | 3f52326 | 2009-05-31 13:31:55 +0100 | [diff] [blame] | 32 | #define HW_APBH_CTRL1 0x10 |
| 33 | #define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 |
| 34 | #define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0 |
| 35 | |
| 36 | #define HW_APBH_DEVSEL 0x20 |
| 37 | |
| 38 | #define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70) |
| 39 | #define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70) |
| 40 | #define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70) |
| 41 | #define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70) |
| 42 | #define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70) |
| 43 | #define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70) |
| 44 | #define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70) |
| 45 | #define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70) |
| 46 | #define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70) |
| 47 | #define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70) |
| 48 | #define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70) |
| 49 | #define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70) |
| 50 | #define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70) |
| 51 | #define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70) |
| 52 | #define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70) |
| 53 | #define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70) |
| 54 | |
| 55 | #define HW_APBH_CHn_NXTCMDAR 0x50 |
| 56 | |
| 57 | #define BM_APBH_CHn_CMD_MODE 0x00000003 |
| 58 | #define BP_APBH_CHn_CMD_MODE 0x00000001 |
| 59 | #define BV_APBH_CHn_CMD_MODE_NOOP 0 |
| 60 | #define BV_APBH_CHn_CMD_MODE_WRITE 1 |
| 61 | #define BV_APBH_CHn_CMD_MODE_READ 2 |
| 62 | #define BV_APBH_CHn_CMD_MODE_SENSE 3 |
dmitry pervushin | 34acb09 | 2009-04-22 23:54:05 +0100 | [diff] [blame] | 63 | #define BM_APBH_CHn_CMD_CHAIN 0x00000004 |
dmitry pervushin | 3f52326 | 2009-05-31 13:31:55 +0100 | [diff] [blame] | 64 | #define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 |
| 65 | #define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 |
| 66 | #define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 |
| 67 | #define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 |
| 68 | #define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 |
| 69 | #define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 |
| 70 | #define BP_APBH_CHn_CMD_CMDWORDS 12 |
| 71 | #define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 |
| 72 | #define BP_APBH_CHn_CMD_XFER_COUNT 16 |
dmitry pervushin | 34acb09 | 2009-04-22 23:54:05 +0100 | [diff] [blame] | 73 | |
dmitry pervushin | 3f52326 | 2009-05-31 13:31:55 +0100 | [diff] [blame] | 74 | #define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70) |
| 75 | #define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70) |
| 76 | #define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70) |
| 77 | #define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70) |
| 78 | #define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70) |
| 79 | #define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70) |
| 80 | #define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70) |
| 81 | #define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70) |
| 82 | #define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70) |
| 83 | #define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70) |
| 84 | #define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70) |
| 85 | #define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70) |
| 86 | #define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70) |
| 87 | #define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70) |
| 88 | #define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70) |
| 89 | #define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70) |
| 90 | |
| 91 | #define HW_APBH_CHn_SEMA 0x80 |
| 92 | #define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF |
| 93 | #define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 |
| 94 | #define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 |
| 95 | #define BP_APBH_CHn_SEMA_PHORE 16 |
| 96 | |
| 97 | #endif |