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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* $Id: pci.c,v 1.6 2000/01/29 00:12:05 grundler Exp $
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 1997, 1998 Ralf Baechle
8 * Copyright (C) 1999 SuSE GmbH
9 * Copyright (C) 1999-2001 Hewlett-Packard Company
10 * Copyright (C) 1999-2001 Grant Grundler
11 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/eisa.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/pci.h>
17#include <linux/slab.h>
18#include <linux/types.h>
19
20#include <asm/io.h>
21#include <asm/system.h>
22#include <asm/cache.h> /* for L1_CACHE_BYTES */
23#include <asm/superio.h>
24
25#define DEBUG_RESOURCES 0
26#define DEBUG_CONFIG 0
27
28#if DEBUG_CONFIG
29# define DBGC(x...) printk(KERN_DEBUG x)
30#else
31# define DBGC(x...)
32#endif
33
34
35#if DEBUG_RESOURCES
36#define DBG_RES(x...) printk(KERN_DEBUG x)
37#else
38#define DBG_RES(x...)
39#endif
40
41/* To be used as: mdelay(pci_post_reset_delay);
42 *
43 * post_reset is the time the kernel should stall to prevent anyone from
44 * accessing the PCI bus once #RESET is de-asserted.
45 * PCI spec somewhere says 1 second but with multi-PCI bus systems,
46 * this makes the boot time much longer than necessary.
47 * 20ms seems to work for all the HP PCI implementations to date.
48 *
Helge Dellercb6fc182006-01-17 12:40:40 -070049 * #define pci_post_reset_delay 50
Linus Torvalds1da177e2005-04-16 15:20:36 -070050 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
Helge Dellercb6fc182006-01-17 12:40:40 -070052struct pci_port_ops *pci_port __read_mostly;
53struct pci_bios_ops *pci_bios __read_mostly;
Linus Torvalds1da177e2005-04-16 15:20:36 -070054
Helge Dellercb6fc182006-01-17 12:40:40 -070055static int pci_hba_count __read_mostly;
Linus Torvalds1da177e2005-04-16 15:20:36 -070056
57/* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */
58#define PCI_HBA_MAX 32
Grant Grundler2c9aada2006-01-19 23:38:03 -070059static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __read_mostly;
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
61
62/********************************************************************
63**
64** I/O port space support
65**
66*********************************************************************/
67
68/* EISA port numbers and PCI port numbers share the same interface. Some
69 * machines have both EISA and PCI adapters installed. Rather than turn
70 * pci_port into an array, we reserve bus 0 for EISA and call the EISA
71 * routines if the access is to a port on bus 0. We don't want to fix
72 * EISA and ISA drivers which assume port space is <= 0xffff.
73 */
74
75#ifdef CONFIG_EISA
76#define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr)
77#define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr)
78#else
79#define EISA_IN(size)
80#define EISA_OUT(size)
81#endif
82
83#define PCI_PORT_IN(type, size) \
84u##size in##type (int addr) \
85{ \
86 int b = PCI_PORT_HBA(addr); \
87 EISA_IN(size); \
88 if (!parisc_pci_hba[b]) return (u##size) -1; \
89 return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
90} \
91EXPORT_SYMBOL(in##type);
92
93PCI_PORT_IN(b, 8)
94PCI_PORT_IN(w, 16)
95PCI_PORT_IN(l, 32)
96
97
98#define PCI_PORT_OUT(type, size) \
99void out##type (u##size d, int addr) \
100{ \
101 int b = PCI_PORT_HBA(addr); \
102 EISA_OUT(size); \
103 if (!parisc_pci_hba[b]) return; \
104 pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \
105} \
106EXPORT_SYMBOL(out##type);
107
108PCI_PORT_OUT(b, 8)
109PCI_PORT_OUT(w, 16)
110PCI_PORT_OUT(l, 32)
111
112
113
114/*
115 * BIOS32 replacement.
116 */
117static int __init pcibios_init(void)
118{
119 if (!pci_bios)
120 return -1;
121
122 if (pci_bios->init) {
123 pci_bios->init();
124 } else {
125 printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
126 }
127 return 0;
128}
129
130
131/* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */
132void pcibios_fixup_bus(struct pci_bus *bus)
133{
134 if (pci_bios->fixup_bus) {
135 pci_bios->fixup_bus(bus);
136 } else {
137 printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n");
138 }
139}
140
141
142char *pcibios_setup(char *str)
143{
144 return str;
145}
146
147/*
148 * Called by pci_set_master() - a driver interface.
149 *
150 * Legacy PDC guarantees to set:
151 * Map Memory BAR's into PA IO space.
152 * Map Expansion ROM BAR into one common PA IO space per bus.
153 * Map IO BAR's into PCI IO space.
154 * Command (see below)
155 * Cache Line Size
156 * Latency Timer
157 * Interrupt Line
158 * PPB: secondary latency timer, io/mmio base/limit,
159 * bus numbers, bridge control
160 *
161 */
162void pcibios_set_master(struct pci_dev *dev)
163{
164 u8 lat;
165
166 /* If someone already mucked with this, don't touch it. */
167 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
168 if (lat >= 16) return;
169
170 /*
171 ** HP generally has fewer devices on the bus than other architectures.
172 ** upper byte is PCI_LATENCY_TIMER.
173 */
174 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
175 (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32)));
176}
177
178
179void __init pcibios_init_bus(struct pci_bus *bus)
180{
181 struct pci_dev *dev = bus->self;
182 unsigned short bridge_ctl;
183
184 /* We deal only with pci controllers and pci-pci bridges. */
185 if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
186 return;
187
188 /* PCI-PCI bridge - set the cache line and default latency
189 (32) for primary and secondary buses. */
190 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
191
192 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
193 bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
194 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl);
195}
196
197
198/* KLUGE: Link the child and parent resources - generic PCI didn't */
199static void
200pcibios_link_hba_resources( struct resource *hba_res, struct resource *r)
201{
202 if (!r->parent) {
Grant Grundler8054f032005-10-21 22:50:33 -0400203 printk(KERN_EMERG "PCI: resource not parented! [%lx-%lx]\n",
204 r->start, r->end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205 r->parent = hba_res;
206
207 /* reverse link is harder *sigh* */
208 if (r->parent->child) {
209 if (r->parent->sibling) {
210 struct resource *next = r->parent->sibling;
211 while (next->sibling)
212 next = next->sibling;
213 next->sibling = r;
214 } else {
215 r->parent->sibling = r;
216 }
217 } else
218 r->parent->child = r;
219 }
220}
221
222/* called by drivers/pci/setup-bus.c:pci_setup_bridge(). */
223void __devinit pcibios_resource_to_bus(struct pci_dev *dev,
224 struct pci_bus_region *region, struct resource *res)
225{
226 struct pci_bus *bus = dev->bus;
227 struct pci_hba_data *hba = HBA_DATA(bus->bridge->platform_data);
228
229 if (res->flags & IORESOURCE_IO) {
230 /*
231 ** I/O space may see busnumbers here. Something
232 ** in the form of 0xbbxxxx where bb is the bus num
233 ** and xxxx is the I/O port space address.
234 ** Remaining address translation are done in the
235 ** PCI Host adapter specific code - ie dino_out8.
236 */
237 region->start = PCI_PORT_ADDR(res->start);
238 region->end = PCI_PORT_ADDR(res->end);
239 } else if (res->flags & IORESOURCE_MEM) {
240 /* Convert MMIO addr to PCI addr (undo global virtualization) */
241 region->start = PCI_BUS_ADDR(hba, res->start);
242 region->end = PCI_BUS_ADDR(hba, res->end);
243 }
244
245 DBG_RES("pcibios_resource_to_bus(%02x %s [%lx,%lx])\n",
246 bus->number, res->flags & IORESOURCE_IO ? "IO" : "MEM",
247 region->start, region->end);
248
249 /* KLUGE ALERT
250 ** if this resource isn't linked to a "parent", then it seems
251 ** to be a child of the HBA - lets link it in.
252 */
253 pcibios_link_hba_resources(&hba->io_space, bus->resource[0]);
254 pcibios_link_hba_resources(&hba->lmmio_space, bus->resource[1]);
255}
256
Dominik Brodowski0f94c8e2005-07-27 11:43:44 -0700257void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
258 struct pci_bus_region *region)
259{
Helge Deller96629c02006-01-15 11:52:22 -0700260#ifdef CONFIG_64BIT
Dominik Brodowski0f94c8e2005-07-27 11:43:44 -0700261 struct pci_bus *bus = dev->bus;
262 struct pci_hba_data *hba = HBA_DATA(bus->bridge->platform_data);
Helge Deller96629c02006-01-15 11:52:22 -0700263#endif
Dominik Brodowski0f94c8e2005-07-27 11:43:44 -0700264
265 if (res->flags & IORESOURCE_MEM) {
266 res->start = PCI_HOST_ADDR(hba, region->start);
267 res->end = PCI_HOST_ADDR(hba, region->end);
268 }
269
270 if (res->flags & IORESOURCE_IO) {
271 res->start = region->start;
272 res->end = region->end;
273 }
274}
275
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276#ifdef CONFIG_HOTPLUG
277EXPORT_SYMBOL(pcibios_resource_to_bus);
Dominik Brodowski0f94c8e2005-07-27 11:43:44 -0700278EXPORT_SYMBOL(pcibios_bus_to_resource);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279#endif
280
281/*
282 * pcibios align resources() is called every time generic PCI code
283 * wants to generate a new address. The process of looking for
284 * an available address, each candidate is first "aligned" and
285 * then checked if the resource is available until a match is found.
286 *
287 * Since we are just checking candidates, don't use any fields other
288 * than res->start.
289 */
290void pcibios_align_resource(void *data, struct resource *res,
Greg Kroah-Hartmane31dd6e2006-06-12 17:06:02 -0700291 resource_size_t size, resource_size_t alignment)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292{
293 unsigned long mask, align;
294
295 DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
296 pci_name(((struct pci_dev *) data)),
297 res->parent, res->start, res->end,
298 (int) res->flags, size, alignment);
299
300 /* If it's not IO, then it's gotta be MEM */
301 align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
302
303 /* Align to largest of MIN or input size */
304 mask = max(alignment, align) - 1;
305 res->start += mask;
306 res->start &= ~mask;
307
308 /* The caller updates the end field, we don't. */
309}
310
311
312/*
313 * A driver is enabling the device. We make sure that all the appropriate
314 * bits are set to allow the device to operate as the driver is expecting.
315 * We enable the port IO and memory IO bits if the device has any BARs of
316 * that type, and we enable the PERR and SERR bits unconditionally.
317 * Drivers that do not need parity (eg graphics and possibly networking)
318 * can clear these bits if they want.
319 */
320int pcibios_enable_device(struct pci_dev *dev, int mask)
321{
322 u16 cmd;
323 int idx;
324
325 pci_read_config_word(dev, PCI_COMMAND, &cmd);
326
327 for (idx = 0; idx < DEVICE_COUNT_RESOURCE; idx++) {
328 struct resource *r = &dev->resource[idx];
329
330 /* only setup requested resources */
331 if (!(mask & (1<<idx)))
332 continue;
333
334 if (r->flags & IORESOURCE_IO)
335 cmd |= PCI_COMMAND_IO;
336 if (r->flags & IORESOURCE_MEM)
337 cmd |= PCI_COMMAND_MEMORY;
338 }
339
340 cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
341
342#if 0
343 /* If bridge/bus controller has FBB enabled, child must too. */
344 if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
345 cmd |= PCI_COMMAND_FAST_BACK;
346#endif
347 DBGC("PCIBIOS: Enabling device %s cmd 0x%04x\n", pci_name(dev), cmd);
348 pci_write_config_word(dev, PCI_COMMAND, cmd);
349 return 0;
350}
351
352
353/* PA-RISC specific */
354void pcibios_register_hba(struct pci_hba_data *hba)
355{
356 if (pci_hba_count >= PCI_HBA_MAX) {
357 printk(KERN_ERR "PCI: Too many Host Bus Adapters\n");
358 return;
359 }
360
361 parisc_pci_hba[pci_hba_count] = hba;
362 hba->hba_num = pci_hba_count++;
363}
364
365subsys_initcall(pcibios_init);