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Ingo Molnarcdd6c482009-09-21 12:02:48 +02001#ifndef _ASM_X86_PERF_EVENT_H
2#define _ASM_X86_PERF_EVENT_H
Thomas Gleixner003a46c2007-10-15 13:57:47 +02003
Ingo Molnareb2b8612008-12-17 09:09:13 +01004/*
Ingo Molnarcdd6c482009-09-21 12:02:48 +02005 * Performance event hw details:
Ingo Molnareb2b8612008-12-17 09:09:13 +01006 */
7
Cyrill Gorcunova0727382010-03-11 19:54:39 +03008#define X86_PMC_MAX_GENERIC 32
Ingo Molnareb2b8612008-12-17 09:09:13 +01009#define X86_PMC_MAX_FIXED 3
10
Ingo Molnar862a1a52008-12-17 13:09:20 +010011#define X86_PMC_IDX_GENERIC 0
12#define X86_PMC_IDX_FIXED 32
13#define X86_PMC_IDX_MAX 64
14
Ingo Molnar241771e2008-12-03 10:39:53 +010015#define MSR_ARCH_PERFMON_PERFCTR0 0xc1
16#define MSR_ARCH_PERFMON_PERFCTR1 0xc2
Thomas Gleixner003a46c2007-10-15 13:57:47 +020017
Ingo Molnar241771e2008-12-03 10:39:53 +010018#define MSR_ARCH_PERFMON_EVENTSEL0 0x186
19#define MSR_ARCH_PERFMON_EVENTSEL1 0x187
Thomas Gleixner003a46c2007-10-15 13:57:47 +020020
Robert Richtera098f442010-03-30 11:28:21 +020021#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
22#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
23#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
24#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
25#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
26#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
27#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
28#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
29#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
30#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
Thomas Gleixner003a46c2007-10-15 13:57:47 +020031
Robert Richtera098f442010-03-30 11:28:21 +020032#define AMD64_EVENTSEL_EVENT \
33 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
34#define INTEL_ARCH_EVENT_MASK \
35 (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
Stephane Eranian1da53e02010-01-18 10:58:01 +020036
Robert Richtera098f442010-03-30 11:28:21 +020037#define X86_RAW_EVENT_MASK \
38 (ARCH_PERFMON_EVENTSEL_EVENT | \
39 ARCH_PERFMON_EVENTSEL_UMASK | \
40 ARCH_PERFMON_EVENTSEL_EDGE | \
41 ARCH_PERFMON_EVENTSEL_INV | \
42 ARCH_PERFMON_EVENTSEL_CMASK)
43#define AMD64_RAW_EVENT_MASK \
44 (X86_RAW_EVENT_MASK | \
45 AMD64_EVENTSEL_EVENT)
Stephane Eranian04a705df2009-10-06 16:42:08 +020046
Ingo Molnar241771e2008-12-03 10:39:53 +010047#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
48#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
Stephane Eranian04a705df2009-10-06 16:42:08 +020049#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
Thomas Gleixner003a46c2007-10-15 13:57:47 +020050#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
Ingo Molnar241771e2008-12-03 10:39:53 +010051 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
52
53#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
Thomas Gleixner003a46c2007-10-15 13:57:47 +020054
Ingo Molnareb2b8612008-12-17 09:09:13 +010055/*
56 * Intel "Architectural Performance Monitoring" CPUID
57 * detection/enumeration details:
58 */
Thomas Gleixner003a46c2007-10-15 13:57:47 +020059union cpuid10_eax {
60 struct {
61 unsigned int version_id:8;
Robert Richter948b1bb2010-03-29 18:36:50 +020062 unsigned int num_counters:8;
Thomas Gleixner003a46c2007-10-15 13:57:47 +020063 unsigned int bit_width:8;
64 unsigned int mask_length:8;
65 } split;
66 unsigned int full;
67};
68
Ingo Molnar703e9372008-12-17 10:51:15 +010069union cpuid10_edx {
70 struct {
Livio Soarese768aee2010-06-03 15:00:31 -040071 unsigned int num_counters_fixed:5;
72 unsigned int bit_width_fixed:8;
73 unsigned int reserved:19;
Ingo Molnar703e9372008-12-17 10:51:15 +010074 } split;
75 unsigned int full;
76};
77
78
79/*
Ingo Molnarcdd6c482009-09-21 12:02:48 +020080 * Fixed-purpose performance events:
Ingo Molnar703e9372008-12-17 10:51:15 +010081 */
82
Ingo Molnar862a1a52008-12-17 13:09:20 +010083/*
84 * All 3 fixed-mode PMCs are configured via this single MSR:
85 */
86#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
87
88/*
89 * The counts are available in three separate MSRs:
90 */
91
Ingo Molnar703e9372008-12-17 10:51:15 +010092/* Instr_Retired.Any: */
93#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
Ingo Molnar2f18d1e2008-12-22 11:10:42 +010094#define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0)
Ingo Molnar703e9372008-12-17 10:51:15 +010095
96/* CPU_CLK_Unhalted.Core: */
97#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
Ingo Molnar2f18d1e2008-12-22 11:10:42 +010098#define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1)
Ingo Molnar703e9372008-12-17 10:51:15 +010099
100/* CPU_CLK_Unhalted.Ref: */
101#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
Ingo Molnar2f18d1e2008-12-22 11:10:42 +0100102#define X86_PMC_IDX_FIXED_BUS_CYCLES (X86_PMC_IDX_FIXED + 2)
Ingo Molnar703e9372008-12-17 10:51:15 +0100103
Markus Metzger30dd5682009-07-21 15:56:48 +0200104/*
105 * We model BTS tracing as another fixed-mode PMC.
106 *
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200107 * We choose a value in the middle of the fixed event range, since lower
108 * values are used by actual fixed events and higher values are used
Markus Metzger30dd5682009-07-21 15:56:48 +0200109 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
110 */
111#define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16)
112
Robert Richter1d6040f2010-02-25 19:40:46 +0100113/* IbsFetchCtl bits/masks */
Robert Richterb47fad32010-09-22 17:45:39 +0200114#define IBS_FETCH_RAND_EN (1ULL<<57)
115#define IBS_FETCH_VAL (1ULL<<49)
116#define IBS_FETCH_ENABLE (1ULL<<48)
117#define IBS_FETCH_CNT 0xFFFF0000ULL
118#define IBS_FETCH_MAX_CNT 0x0000FFFFULL
Robert Richter1d6040f2010-02-25 19:40:46 +0100119
120/* IbsOpCtl bits */
Robert Richterb47fad32010-09-22 17:45:39 +0200121#define IBS_OP_CNT_CTL (1ULL<<19)
122#define IBS_OP_VAL (1ULL<<18)
123#define IBS_OP_ENABLE (1ULL<<17)
124#define IBS_OP_MAX_CNT 0x0000FFFFULL
125#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
Markus Metzger30dd5682009-07-21 15:56:48 +0200126
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200127#ifdef CONFIG_PERF_EVENTS
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200128extern void perf_events_lapic_init(void);
Peter Zijlstra194002b2009-06-22 16:35:24 +0200129
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200130#define PERF_EVENT_INDEX_OFFSET 0
Peter Zijlstra194002b2009-06-22 16:35:24 +0200131
Peter Zijlstraef21f682010-03-03 13:12:23 +0100132/*
133 * Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
134 * This flag is otherwise unused and ABI specified to be 0, so nobody should
135 * care what we do with it.
136 */
137#define PERF_EFLAGS_EXACT (1UL << 3)
138
Zhang, Yanmin39447b32010-04-19 13:32:41 +0800139struct pt_regs;
140extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
141extern unsigned long perf_misc_flags(struct pt_regs *regs);
142#define perf_misc_flags(regs) perf_misc_flags(regs)
Peter Zijlstraef21f682010-03-03 13:12:23 +0100143
Frederic Weisbeckerb0f82b82010-05-20 07:47:21 +0200144#include <asm/stacktrace.h>
145
146/*
147 * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
148 * and the comment with PERF_EFLAGS_EXACT.
149 */
150#define perf_arch_fetch_caller_regs(regs, __ip) { \
151 (regs)->ip = (__ip); \
152 (regs)->bp = caller_frame_pointer(); \
153 (regs)->cs = __KERNEL_CS; \
154 regs->flags = 0; \
155}
156
Ingo Molnar241771e2008-12-03 10:39:53 +0100157#else
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200158static inline void perf_events_lapic_init(void) { }
Ingo Molnar241771e2008-12-03 10:39:53 +0100159#endif
160
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200161#endif /* _ASM_X86_PERF_EVENT_H */