Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1 | #include "drmP.h" |
| 2 | #include "drm.h" |
| 3 | #include "nouveau_drv.h" |
| 4 | #include "nouveau_drm.h" |
| 5 | |
| 6 | /* |
| 7 | * NV20 |
| 8 | * ----- |
| 9 | * There are 3 families : |
| 10 | * NV20 is 0x10de:0x020* |
| 11 | * NV25/28 is 0x10de:0x025* / 0x10de:0x028* |
| 12 | * NV2A is 0x10de:0x02A0 |
| 13 | * |
| 14 | * NV30 |
| 15 | * ----- |
| 16 | * There are 3 families : |
| 17 | * NV30/31 is 0x10de:0x030* / 0x10de:0x031* |
| 18 | * NV34 is 0x10de:0x032* |
| 19 | * NV35/36 is 0x10de:0x033* / 0x10de:0x034* |
| 20 | * |
| 21 | * Not seen in the wild, no dumps (probably NV35) : |
| 22 | * NV37 is 0x10de:0x00fc, 0x10de:0x00fd |
| 23 | * NV38 is 0x10de:0x0333, 0x10de:0x00fe |
| 24 | * |
| 25 | */ |
| 26 | |
| 27 | #define NV20_GRCTX_SIZE (3580*4) |
| 28 | #define NV25_GRCTX_SIZE (3529*4) |
| 29 | #define NV2A_GRCTX_SIZE (3500*4) |
| 30 | |
| 31 | #define NV30_31_GRCTX_SIZE (24392) |
| 32 | #define NV34_GRCTX_SIZE (18140) |
| 33 | #define NV35_36_GRCTX_SIZE (22396) |
| 34 | |
| 35 | static void |
| 36 | nv20_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) |
| 37 | { |
| 38 | int i; |
| 39 | |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 40 | nv_wo32(ctx, 0x033c, 0xffff0000); |
| 41 | nv_wo32(ctx, 0x03a0, 0x0fff0000); |
| 42 | nv_wo32(ctx, 0x03a4, 0x0fff0000); |
| 43 | nv_wo32(ctx, 0x047c, 0x00000101); |
| 44 | nv_wo32(ctx, 0x0490, 0x00000111); |
| 45 | nv_wo32(ctx, 0x04a8, 0x44400000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 46 | for (i = 0x04d4; i <= 0x04e0; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 47 | nv_wo32(ctx, i, 0x00030303); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 48 | for (i = 0x04f4; i <= 0x0500; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 49 | nv_wo32(ctx, i, 0x00080000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 50 | for (i = 0x050c; i <= 0x0518; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 51 | nv_wo32(ctx, i, 0x01012000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 52 | for (i = 0x051c; i <= 0x0528; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 53 | nv_wo32(ctx, i, 0x000105b8); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 54 | for (i = 0x052c; i <= 0x0538; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 55 | nv_wo32(ctx, i, 0x00080008); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 56 | for (i = 0x055c; i <= 0x0598; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 57 | nv_wo32(ctx, i, 0x07ff0000); |
| 58 | nv_wo32(ctx, 0x05a4, 0x4b7fffff); |
| 59 | nv_wo32(ctx, 0x05fc, 0x00000001); |
| 60 | nv_wo32(ctx, 0x0604, 0x00004000); |
| 61 | nv_wo32(ctx, 0x0610, 0x00000001); |
| 62 | nv_wo32(ctx, 0x0618, 0x00040000); |
| 63 | nv_wo32(ctx, 0x061c, 0x00010000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 64 | for (i = 0x1c1c; i <= 0x248c; i += 16) { |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 65 | nv_wo32(ctx, (i + 0), 0x10700ff9); |
| 66 | nv_wo32(ctx, (i + 4), 0x0436086c); |
| 67 | nv_wo32(ctx, (i + 8), 0x000c001b); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 68 | } |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 69 | nv_wo32(ctx, 0x281c, 0x3f800000); |
| 70 | nv_wo32(ctx, 0x2830, 0x3f800000); |
| 71 | nv_wo32(ctx, 0x285c, 0x40000000); |
| 72 | nv_wo32(ctx, 0x2860, 0x3f800000); |
| 73 | nv_wo32(ctx, 0x2864, 0x3f000000); |
| 74 | nv_wo32(ctx, 0x286c, 0x40000000); |
| 75 | nv_wo32(ctx, 0x2870, 0x3f800000); |
| 76 | nv_wo32(ctx, 0x2878, 0xbf800000); |
| 77 | nv_wo32(ctx, 0x2880, 0xbf800000); |
| 78 | nv_wo32(ctx, 0x34a4, 0x000fe000); |
| 79 | nv_wo32(ctx, 0x3530, 0x000003f8); |
| 80 | nv_wo32(ctx, 0x3540, 0x002fe000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 81 | for (i = 0x355c; i <= 0x3578; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 82 | nv_wo32(ctx, i, 0x001c527c); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 83 | } |
| 84 | |
| 85 | static void |
| 86 | nv25_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) |
| 87 | { |
| 88 | int i; |
| 89 | |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 90 | nv_wo32(ctx, 0x035c, 0xffff0000); |
| 91 | nv_wo32(ctx, 0x03c0, 0x0fff0000); |
| 92 | nv_wo32(ctx, 0x03c4, 0x0fff0000); |
| 93 | nv_wo32(ctx, 0x049c, 0x00000101); |
| 94 | nv_wo32(ctx, 0x04b0, 0x00000111); |
| 95 | nv_wo32(ctx, 0x04c8, 0x00000080); |
| 96 | nv_wo32(ctx, 0x04cc, 0xffff0000); |
| 97 | nv_wo32(ctx, 0x04d0, 0x00000001); |
| 98 | nv_wo32(ctx, 0x04e4, 0x44400000); |
| 99 | nv_wo32(ctx, 0x04fc, 0x4b800000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 100 | for (i = 0x0510; i <= 0x051c; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 101 | nv_wo32(ctx, i, 0x00030303); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 102 | for (i = 0x0530; i <= 0x053c; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 103 | nv_wo32(ctx, i, 0x00080000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 104 | for (i = 0x0548; i <= 0x0554; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 105 | nv_wo32(ctx, i, 0x01012000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 106 | for (i = 0x0558; i <= 0x0564; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 107 | nv_wo32(ctx, i, 0x000105b8); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 108 | for (i = 0x0568; i <= 0x0574; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 109 | nv_wo32(ctx, i, 0x00080008); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 110 | for (i = 0x0598; i <= 0x05d4; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 111 | nv_wo32(ctx, i, 0x07ff0000); |
| 112 | nv_wo32(ctx, 0x05e0, 0x4b7fffff); |
| 113 | nv_wo32(ctx, 0x0620, 0x00000080); |
| 114 | nv_wo32(ctx, 0x0624, 0x30201000); |
| 115 | nv_wo32(ctx, 0x0628, 0x70605040); |
| 116 | nv_wo32(ctx, 0x062c, 0xb0a09080); |
| 117 | nv_wo32(ctx, 0x0630, 0xf0e0d0c0); |
| 118 | nv_wo32(ctx, 0x0664, 0x00000001); |
| 119 | nv_wo32(ctx, 0x066c, 0x00004000); |
| 120 | nv_wo32(ctx, 0x0678, 0x00000001); |
| 121 | nv_wo32(ctx, 0x0680, 0x00040000); |
| 122 | nv_wo32(ctx, 0x0684, 0x00010000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 123 | for (i = 0x1b04; i <= 0x2374; i += 16) { |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 124 | nv_wo32(ctx, (i + 0), 0x10700ff9); |
| 125 | nv_wo32(ctx, (i + 4), 0x0436086c); |
| 126 | nv_wo32(ctx, (i + 8), 0x000c001b); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 127 | } |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 128 | nv_wo32(ctx, 0x2704, 0x3f800000); |
| 129 | nv_wo32(ctx, 0x2718, 0x3f800000); |
| 130 | nv_wo32(ctx, 0x2744, 0x40000000); |
| 131 | nv_wo32(ctx, 0x2748, 0x3f800000); |
| 132 | nv_wo32(ctx, 0x274c, 0x3f000000); |
| 133 | nv_wo32(ctx, 0x2754, 0x40000000); |
| 134 | nv_wo32(ctx, 0x2758, 0x3f800000); |
| 135 | nv_wo32(ctx, 0x2760, 0xbf800000); |
| 136 | nv_wo32(ctx, 0x2768, 0xbf800000); |
| 137 | nv_wo32(ctx, 0x308c, 0x000fe000); |
| 138 | nv_wo32(ctx, 0x3108, 0x000003f8); |
| 139 | nv_wo32(ctx, 0x3468, 0x002fe000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 140 | for (i = 0x3484; i <= 0x34a0; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 141 | nv_wo32(ctx, i, 0x001c527c); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 142 | } |
| 143 | |
| 144 | static void |
| 145 | nv2a_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) |
| 146 | { |
| 147 | int i; |
| 148 | |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 149 | nv_wo32(ctx, 0x033c, 0xffff0000); |
| 150 | nv_wo32(ctx, 0x03a0, 0x0fff0000); |
| 151 | nv_wo32(ctx, 0x03a4, 0x0fff0000); |
| 152 | nv_wo32(ctx, 0x047c, 0x00000101); |
| 153 | nv_wo32(ctx, 0x0490, 0x00000111); |
| 154 | nv_wo32(ctx, 0x04a8, 0x44400000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 155 | for (i = 0x04d4; i <= 0x04e0; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 156 | nv_wo32(ctx, i, 0x00030303); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 157 | for (i = 0x04f4; i <= 0x0500; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 158 | nv_wo32(ctx, i, 0x00080000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 159 | for (i = 0x050c; i <= 0x0518; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 160 | nv_wo32(ctx, i, 0x01012000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 161 | for (i = 0x051c; i <= 0x0528; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 162 | nv_wo32(ctx, i, 0x000105b8); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 163 | for (i = 0x052c; i <= 0x0538; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 164 | nv_wo32(ctx, i, 0x00080008); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 165 | for (i = 0x055c; i <= 0x0598; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 166 | nv_wo32(ctx, i, 0x07ff0000); |
| 167 | nv_wo32(ctx, 0x05a4, 0x4b7fffff); |
| 168 | nv_wo32(ctx, 0x05fc, 0x00000001); |
| 169 | nv_wo32(ctx, 0x0604, 0x00004000); |
| 170 | nv_wo32(ctx, 0x0610, 0x00000001); |
| 171 | nv_wo32(ctx, 0x0618, 0x00040000); |
| 172 | nv_wo32(ctx, 0x061c, 0x00010000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 173 | for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */ |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 174 | nv_wo32(ctx, (i + 0), 0x10700ff9); |
| 175 | nv_wo32(ctx, (i + 4), 0x0436086c); |
| 176 | nv_wo32(ctx, (i + 8), 0x000c001b); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 177 | } |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 178 | nv_wo32(ctx, 0x269c, 0x3f800000); |
| 179 | nv_wo32(ctx, 0x26b0, 0x3f800000); |
| 180 | nv_wo32(ctx, 0x26dc, 0x40000000); |
| 181 | nv_wo32(ctx, 0x26e0, 0x3f800000); |
| 182 | nv_wo32(ctx, 0x26e4, 0x3f000000); |
| 183 | nv_wo32(ctx, 0x26ec, 0x40000000); |
| 184 | nv_wo32(ctx, 0x26f0, 0x3f800000); |
| 185 | nv_wo32(ctx, 0x26f8, 0xbf800000); |
| 186 | nv_wo32(ctx, 0x2700, 0xbf800000); |
| 187 | nv_wo32(ctx, 0x3024, 0x000fe000); |
| 188 | nv_wo32(ctx, 0x30a0, 0x000003f8); |
| 189 | nv_wo32(ctx, 0x33fc, 0x002fe000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 190 | for (i = 0x341c; i <= 0x3438; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 191 | nv_wo32(ctx, i, 0x001c527c); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 192 | } |
| 193 | |
| 194 | static void |
| 195 | nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) |
| 196 | { |
| 197 | int i; |
| 198 | |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 199 | nv_wo32(ctx, 0x0410, 0x00000101); |
| 200 | nv_wo32(ctx, 0x0424, 0x00000111); |
| 201 | nv_wo32(ctx, 0x0428, 0x00000060); |
| 202 | nv_wo32(ctx, 0x0444, 0x00000080); |
| 203 | nv_wo32(ctx, 0x0448, 0xffff0000); |
| 204 | nv_wo32(ctx, 0x044c, 0x00000001); |
| 205 | nv_wo32(ctx, 0x0460, 0x44400000); |
| 206 | nv_wo32(ctx, 0x048c, 0xffff0000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 207 | for (i = 0x04e0; i < 0x04e8; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 208 | nv_wo32(ctx, i, 0x0fff0000); |
| 209 | nv_wo32(ctx, 0x04ec, 0x00011100); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 210 | for (i = 0x0508; i < 0x0548; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 211 | nv_wo32(ctx, i, 0x07ff0000); |
| 212 | nv_wo32(ctx, 0x0550, 0x4b7fffff); |
| 213 | nv_wo32(ctx, 0x058c, 0x00000080); |
| 214 | nv_wo32(ctx, 0x0590, 0x30201000); |
| 215 | nv_wo32(ctx, 0x0594, 0x70605040); |
| 216 | nv_wo32(ctx, 0x0598, 0xb8a89888); |
| 217 | nv_wo32(ctx, 0x059c, 0xf8e8d8c8); |
| 218 | nv_wo32(ctx, 0x05b0, 0xb0000000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 219 | for (i = 0x0600; i < 0x0640; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 220 | nv_wo32(ctx, i, 0x00010588); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 221 | for (i = 0x0640; i < 0x0680; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 222 | nv_wo32(ctx, i, 0x00030303); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 223 | for (i = 0x06c0; i < 0x0700; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 224 | nv_wo32(ctx, i, 0x0008aae4); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 225 | for (i = 0x0700; i < 0x0740; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 226 | nv_wo32(ctx, i, 0x01012000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 227 | for (i = 0x0740; i < 0x0780; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 228 | nv_wo32(ctx, i, 0x00080008); |
| 229 | nv_wo32(ctx, 0x085c, 0x00040000); |
| 230 | nv_wo32(ctx, 0x0860, 0x00010000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 231 | for (i = 0x0864; i < 0x0874; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 232 | nv_wo32(ctx, i, 0x00040004); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 233 | for (i = 0x1f18; i <= 0x3088 ; i += 16) { |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 234 | nv_wo32(ctx, i + 0, 0x10700ff9); |
| 235 | nv_wo32(ctx, i + 1, 0x0436086c); |
| 236 | nv_wo32(ctx, i + 2, 0x000c001b); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 237 | } |
| 238 | for (i = 0x30b8; i < 0x30c8; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 239 | nv_wo32(ctx, i, 0x0000ffff); |
| 240 | nv_wo32(ctx, 0x344c, 0x3f800000); |
| 241 | nv_wo32(ctx, 0x3808, 0x3f800000); |
| 242 | nv_wo32(ctx, 0x381c, 0x3f800000); |
| 243 | nv_wo32(ctx, 0x3848, 0x40000000); |
| 244 | nv_wo32(ctx, 0x384c, 0x3f800000); |
| 245 | nv_wo32(ctx, 0x3850, 0x3f000000); |
| 246 | nv_wo32(ctx, 0x3858, 0x40000000); |
| 247 | nv_wo32(ctx, 0x385c, 0x3f800000); |
| 248 | nv_wo32(ctx, 0x3864, 0xbf800000); |
| 249 | nv_wo32(ctx, 0x386c, 0xbf800000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 250 | } |
| 251 | |
| 252 | static void |
| 253 | nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) |
| 254 | { |
| 255 | int i; |
| 256 | |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 257 | nv_wo32(ctx, 0x040c, 0x01000101); |
| 258 | nv_wo32(ctx, 0x0420, 0x00000111); |
| 259 | nv_wo32(ctx, 0x0424, 0x00000060); |
| 260 | nv_wo32(ctx, 0x0440, 0x00000080); |
| 261 | nv_wo32(ctx, 0x0444, 0xffff0000); |
| 262 | nv_wo32(ctx, 0x0448, 0x00000001); |
| 263 | nv_wo32(ctx, 0x045c, 0x44400000); |
| 264 | nv_wo32(ctx, 0x0480, 0xffff0000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 265 | for (i = 0x04d4; i < 0x04dc; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 266 | nv_wo32(ctx, i, 0x0fff0000); |
| 267 | nv_wo32(ctx, 0x04e0, 0x00011100); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 268 | for (i = 0x04fc; i < 0x053c; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 269 | nv_wo32(ctx, i, 0x07ff0000); |
| 270 | nv_wo32(ctx, 0x0544, 0x4b7fffff); |
| 271 | nv_wo32(ctx, 0x057c, 0x00000080); |
| 272 | nv_wo32(ctx, 0x0580, 0x30201000); |
| 273 | nv_wo32(ctx, 0x0584, 0x70605040); |
| 274 | nv_wo32(ctx, 0x0588, 0xb8a89888); |
| 275 | nv_wo32(ctx, 0x058c, 0xf8e8d8c8); |
| 276 | nv_wo32(ctx, 0x05a0, 0xb0000000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 277 | for (i = 0x05f0; i < 0x0630; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 278 | nv_wo32(ctx, i, 0x00010588); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 279 | for (i = 0x0630; i < 0x0670; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 280 | nv_wo32(ctx, i, 0x00030303); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 281 | for (i = 0x06b0; i < 0x06f0; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 282 | nv_wo32(ctx, i, 0x0008aae4); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 283 | for (i = 0x06f0; i < 0x0730; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 284 | nv_wo32(ctx, i, 0x01012000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 285 | for (i = 0x0730; i < 0x0770; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 286 | nv_wo32(ctx, i, 0x00080008); |
| 287 | nv_wo32(ctx, 0x0850, 0x00040000); |
| 288 | nv_wo32(ctx, 0x0854, 0x00010000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 289 | for (i = 0x0858; i < 0x0868; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 290 | nv_wo32(ctx, i, 0x00040004); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 291 | for (i = 0x15ac; i <= 0x271c ; i += 16) { |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 292 | nv_wo32(ctx, i + 0, 0x10700ff9); |
| 293 | nv_wo32(ctx, i + 1, 0x0436086c); |
| 294 | nv_wo32(ctx, i + 2, 0x000c001b); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 295 | } |
| 296 | for (i = 0x274c; i < 0x275c; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 297 | nv_wo32(ctx, i, 0x0000ffff); |
| 298 | nv_wo32(ctx, 0x2ae0, 0x3f800000); |
| 299 | nv_wo32(ctx, 0x2e9c, 0x3f800000); |
| 300 | nv_wo32(ctx, 0x2eb0, 0x3f800000); |
| 301 | nv_wo32(ctx, 0x2edc, 0x40000000); |
| 302 | nv_wo32(ctx, 0x2ee0, 0x3f800000); |
| 303 | nv_wo32(ctx, 0x2ee4, 0x3f000000); |
| 304 | nv_wo32(ctx, 0x2eec, 0x40000000); |
| 305 | nv_wo32(ctx, 0x2ef0, 0x3f800000); |
| 306 | nv_wo32(ctx, 0x2ef8, 0xbf800000); |
| 307 | nv_wo32(ctx, 0x2f00, 0xbf800000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 308 | } |
| 309 | |
| 310 | static void |
| 311 | nv35_36_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) |
| 312 | { |
| 313 | int i; |
| 314 | |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 315 | nv_wo32(ctx, 0x040c, 0x00000101); |
| 316 | nv_wo32(ctx, 0x0420, 0x00000111); |
| 317 | nv_wo32(ctx, 0x0424, 0x00000060); |
| 318 | nv_wo32(ctx, 0x0440, 0x00000080); |
| 319 | nv_wo32(ctx, 0x0444, 0xffff0000); |
| 320 | nv_wo32(ctx, 0x0448, 0x00000001); |
| 321 | nv_wo32(ctx, 0x045c, 0x44400000); |
| 322 | nv_wo32(ctx, 0x0488, 0xffff0000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 323 | for (i = 0x04dc; i < 0x04e4; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 324 | nv_wo32(ctx, i, 0x0fff0000); |
| 325 | nv_wo32(ctx, 0x04e8, 0x00011100); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 326 | for (i = 0x0504; i < 0x0544; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 327 | nv_wo32(ctx, i, 0x07ff0000); |
| 328 | nv_wo32(ctx, 0x054c, 0x4b7fffff); |
| 329 | nv_wo32(ctx, 0x0588, 0x00000080); |
| 330 | nv_wo32(ctx, 0x058c, 0x30201000); |
| 331 | nv_wo32(ctx, 0x0590, 0x70605040); |
| 332 | nv_wo32(ctx, 0x0594, 0xb8a89888); |
| 333 | nv_wo32(ctx, 0x0598, 0xf8e8d8c8); |
| 334 | nv_wo32(ctx, 0x05ac, 0xb0000000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 335 | for (i = 0x0604; i < 0x0644; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 336 | nv_wo32(ctx, i, 0x00010588); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 337 | for (i = 0x0644; i < 0x0684; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 338 | nv_wo32(ctx, i, 0x00030303); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 339 | for (i = 0x06c4; i < 0x0704; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 340 | nv_wo32(ctx, i, 0x0008aae4); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 341 | for (i = 0x0704; i < 0x0744; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 342 | nv_wo32(ctx, i, 0x01012000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 343 | for (i = 0x0744; i < 0x0784; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 344 | nv_wo32(ctx, i, 0x00080008); |
| 345 | nv_wo32(ctx, 0x0860, 0x00040000); |
| 346 | nv_wo32(ctx, 0x0864, 0x00010000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 347 | for (i = 0x0868; i < 0x0878; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 348 | nv_wo32(ctx, i, 0x00040004); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 349 | for (i = 0x1f1c; i <= 0x308c ; i += 16) { |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 350 | nv_wo32(ctx, i + 0, 0x10700ff9); |
| 351 | nv_wo32(ctx, i + 4, 0x0436086c); |
| 352 | nv_wo32(ctx, i + 8, 0x000c001b); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 353 | } |
| 354 | for (i = 0x30bc; i < 0x30cc; i += 4) |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 355 | nv_wo32(ctx, i, 0x0000ffff); |
| 356 | nv_wo32(ctx, 0x3450, 0x3f800000); |
| 357 | nv_wo32(ctx, 0x380c, 0x3f800000); |
| 358 | nv_wo32(ctx, 0x3820, 0x3f800000); |
| 359 | nv_wo32(ctx, 0x384c, 0x40000000); |
| 360 | nv_wo32(ctx, 0x3850, 0x3f800000); |
| 361 | nv_wo32(ctx, 0x3854, 0x3f000000); |
| 362 | nv_wo32(ctx, 0x385c, 0x40000000); |
| 363 | nv_wo32(ctx, 0x3860, 0x3f800000); |
| 364 | nv_wo32(ctx, 0x3868, 0xbf800000); |
| 365 | nv_wo32(ctx, 0x3870, 0xbf800000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 366 | } |
| 367 | |
| 368 | int |
| 369 | nv20_graph_create_context(struct nouveau_channel *chan) |
| 370 | { |
| 371 | struct drm_device *dev = chan->dev; |
| 372 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | 816544b | 2010-07-08 13:15:05 +1000 | [diff] [blame] | 373 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 374 | void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *); |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 375 | unsigned int idoffs = 0x28; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 376 | int ret; |
| 377 | |
| 378 | switch (dev_priv->chipset) { |
| 379 | case 0x20: |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 380 | ctx_init = nv20_graph_context_init; |
| 381 | idoffs = 0; |
| 382 | break; |
| 383 | case 0x25: |
| 384 | case 0x28: |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 385 | ctx_init = nv25_graph_context_init; |
| 386 | break; |
| 387 | case 0x2a: |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 388 | ctx_init = nv2a_graph_context_init; |
| 389 | idoffs = 0; |
| 390 | break; |
| 391 | case 0x30: |
| 392 | case 0x31: |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 393 | ctx_init = nv30_31_graph_context_init; |
| 394 | break; |
| 395 | case 0x34: |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 396 | ctx_init = nv34_graph_context_init; |
| 397 | break; |
| 398 | case 0x35: |
| 399 | case 0x36: |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 400 | ctx_init = nv35_36_graph_context_init; |
| 401 | break; |
| 402 | default: |
Ben Skeggs | 816544b | 2010-07-08 13:15:05 +1000 | [diff] [blame] | 403 | BUG_ON(1); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 404 | } |
| 405 | |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 406 | ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16, |
| 407 | NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 408 | if (ret) |
| 409 | return ret; |
| 410 | |
| 411 | /* Initialise default context values */ |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 412 | ctx_init(dev, chan->ramin_grctx); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 413 | |
| 414 | /* nv20: nv_wo32(dev, chan->ramin_grctx->gpuobj, 10, chan->id<<24); */ |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 415 | nv_wo32(chan->ramin_grctx, idoffs, |
Ben Skeggs | b3beb16 | 2010-09-01 15:24:29 +1000 | [diff] [blame] | 416 | (chan->id << 24) | 0x1); /* CTX_USER */ |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 417 | |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 418 | nv_wo32(pgraph->ctx_table, chan->id * 4, chan->ramin_grctx->pinst >> 4); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 419 | return 0; |
| 420 | } |
| 421 | |
| 422 | void |
| 423 | nv20_graph_destroy_context(struct nouveau_channel *chan) |
| 424 | { |
| 425 | struct drm_device *dev = chan->dev; |
| 426 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | c50a568 | 2010-07-08 15:40:18 +1000 | [diff] [blame] | 427 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 428 | |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 429 | nouveau_gpuobj_ref(NULL, &chan->ramin_grctx); |
| 430 | nv_wo32(pgraph->ctx_table, chan->id * 4, 0); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 431 | } |
| 432 | |
| 433 | int |
| 434 | nv20_graph_load_context(struct nouveau_channel *chan) |
| 435 | { |
| 436 | struct drm_device *dev = chan->dev; |
| 437 | uint32_t inst; |
| 438 | |
| 439 | if (!chan->ramin_grctx) |
| 440 | return -EINVAL; |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 441 | inst = chan->ramin_grctx->pinst >> 4; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 442 | |
| 443 | nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); |
| 444 | nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER, |
| 445 | NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD); |
| 446 | nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100); |
| 447 | |
| 448 | nouveau_wait_for_idle(dev); |
| 449 | return 0; |
| 450 | } |
| 451 | |
| 452 | int |
| 453 | nv20_graph_unload_context(struct drm_device *dev) |
| 454 | { |
| 455 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 456 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; |
| 457 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; |
| 458 | struct nouveau_channel *chan; |
| 459 | uint32_t inst, tmp; |
| 460 | |
| 461 | chan = pgraph->channel(dev); |
| 462 | if (!chan) |
| 463 | return 0; |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 464 | inst = chan->ramin_grctx->pinst >> 4; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 465 | |
| 466 | nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); |
| 467 | nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER, |
| 468 | NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE); |
| 469 | |
| 470 | nouveau_wait_for_idle(dev); |
| 471 | |
| 472 | nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000); |
| 473 | tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff; |
| 474 | tmp |= (pfifo->channels - 1) << 24; |
| 475 | nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp); |
| 476 | return 0; |
| 477 | } |
| 478 | |
| 479 | static void |
| 480 | nv20_graph_rdi(struct drm_device *dev) |
| 481 | { |
| 482 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 483 | int i, writecount = 32; |
| 484 | uint32_t rdi_index = 0x2c80000; |
| 485 | |
| 486 | if (dev_priv->chipset == 0x20) { |
| 487 | rdi_index = 0x3d0000; |
| 488 | writecount = 15; |
| 489 | } |
| 490 | |
| 491 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, rdi_index); |
| 492 | for (i = 0; i < writecount; i++) |
| 493 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA, 0); |
| 494 | |
| 495 | nouveau_wait_for_idle(dev); |
| 496 | } |
| 497 | |
Francisco Jerez | 0d87c10 | 2009-12-16 12:12:27 +0100 | [diff] [blame] | 498 | void |
| 499 | nv20_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, |
| 500 | uint32_t size, uint32_t pitch) |
| 501 | { |
| 502 | uint32_t limit = max(1u, addr + size) - 1; |
| 503 | |
| 504 | if (pitch) |
| 505 | addr |= 1; |
| 506 | |
| 507 | nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit); |
| 508 | nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch); |
| 509 | nv_wr32(dev, NV20_PGRAPH_TILE(i), addr); |
| 510 | |
| 511 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); |
| 512 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA, limit); |
| 513 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); |
| 514 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA, pitch); |
| 515 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); |
| 516 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA, addr); |
| 517 | } |
| 518 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 519 | int |
| 520 | nv20_graph_init(struct drm_device *dev) |
| 521 | { |
Ben Skeggs | c50a568 | 2010-07-08 15:40:18 +1000 | [diff] [blame] | 522 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | 816544b | 2010-07-08 13:15:05 +1000 | [diff] [blame] | 523 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 524 | uint32_t tmp, vramsz; |
| 525 | int ret, i; |
| 526 | |
Ben Skeggs | 816544b | 2010-07-08 13:15:05 +1000 | [diff] [blame] | 527 | switch (dev_priv->chipset) { |
| 528 | case 0x20: |
| 529 | pgraph->grctx_size = NV20_GRCTX_SIZE; |
| 530 | break; |
| 531 | case 0x25: |
| 532 | case 0x28: |
| 533 | pgraph->grctx_size = NV25_GRCTX_SIZE; |
| 534 | break; |
| 535 | case 0x2a: |
| 536 | pgraph->grctx_size = NV2A_GRCTX_SIZE; |
| 537 | break; |
| 538 | default: |
| 539 | NV_ERROR(dev, "unknown chipset, disabling acceleration\n"); |
| 540 | pgraph->accel_blocked = true; |
| 541 | return 0; |
| 542 | } |
| 543 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 544 | nv_wr32(dev, NV03_PMC_ENABLE, |
| 545 | nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); |
| 546 | nv_wr32(dev, NV03_PMC_ENABLE, |
| 547 | nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH); |
| 548 | |
Ben Skeggs | c50a568 | 2010-07-08 15:40:18 +1000 | [diff] [blame] | 549 | if (!pgraph->ctx_table) { |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 550 | /* Create Context Pointer Table */ |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 551 | ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16, |
| 552 | NVOBJ_FLAG_ZERO_ALLOC, |
| 553 | &pgraph->ctx_table); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 554 | if (ret) |
| 555 | return ret; |
| 556 | } |
| 557 | |
| 558 | nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 559 | pgraph->ctx_table->pinst >> 4); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 560 | |
| 561 | nv20_graph_rdi(dev); |
| 562 | |
| 563 | nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF); |
| 564 | nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); |
| 565 | |
| 566 | nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); |
| 567 | nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000); |
| 568 | nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x00118700); |
| 569 | nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ |
| 570 | nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00000000); |
| 571 | nv_wr32(dev, 0x40009C , 0x00000040); |
| 572 | |
| 573 | if (dev_priv->chipset >= 0x25) { |
| 574 | nv_wr32(dev, 0x400890, 0x00080000); |
| 575 | nv_wr32(dev, 0x400610, 0x304B1FB6); |
| 576 | nv_wr32(dev, 0x400B80, 0x18B82880); |
| 577 | nv_wr32(dev, 0x400B84, 0x44000000); |
| 578 | nv_wr32(dev, 0x400098, 0x40000080); |
| 579 | nv_wr32(dev, 0x400B88, 0x000000ff); |
| 580 | } else { |
| 581 | nv_wr32(dev, 0x400880, 0x00080000); /* 0x0008c7df */ |
| 582 | nv_wr32(dev, 0x400094, 0x00000005); |
| 583 | nv_wr32(dev, 0x400B80, 0x45CAA208); /* 0x45eae20e */ |
| 584 | nv_wr32(dev, 0x400B84, 0x24000000); |
| 585 | nv_wr32(dev, 0x400098, 0x00000040); |
| 586 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E00038); |
| 587 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030); |
| 588 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E10038); |
| 589 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000030); |
| 590 | } |
| 591 | |
Francisco Jerez | 0d87c10 | 2009-12-16 12:12:27 +0100 | [diff] [blame] | 592 | /* Turn all the tiling regions off. */ |
| 593 | for (i = 0; i < NV10_PFB_TILE__SIZE; i++) |
| 594 | nv20_graph_set_region_tiling(dev, i, 0, 0, 0); |
| 595 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 596 | for (i = 0; i < 8; i++) { |
| 597 | nv_wr32(dev, 0x400980 + i * 4, nv_rd32(dev, 0x100300 + i * 4)); |
| 598 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0090 + i * 4); |
| 599 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA, |
| 600 | nv_rd32(dev, 0x100300 + i * 4)); |
| 601 | } |
| 602 | nv_wr32(dev, 0x4009a0, nv_rd32(dev, 0x100324)); |
| 603 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); |
| 604 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA, nv_rd32(dev, 0x100324)); |
| 605 | |
| 606 | nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100); |
| 607 | nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF); |
| 608 | |
| 609 | tmp = nv_rd32(dev, NV10_PGRAPH_SURFACE) & 0x0007ff00; |
| 610 | nv_wr32(dev, NV10_PGRAPH_SURFACE, tmp); |
| 611 | tmp = nv_rd32(dev, NV10_PGRAPH_SURFACE) | 0x00020100; |
| 612 | nv_wr32(dev, NV10_PGRAPH_SURFACE, tmp); |
| 613 | |
| 614 | /* begin RAM config */ |
Jordan Crouse | 01d73a6 | 2010-05-27 13:40:24 -0600 | [diff] [blame] | 615 | vramsz = pci_resource_len(dev->pdev, 0) - 1; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 616 | nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0)); |
| 617 | nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1)); |
| 618 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); |
| 619 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA , nv_rd32(dev, NV04_PFB_CFG0)); |
| 620 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); |
| 621 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA , nv_rd32(dev, NV04_PFB_CFG1)); |
| 622 | nv_wr32(dev, 0x400820, 0); |
| 623 | nv_wr32(dev, 0x400824, 0); |
| 624 | nv_wr32(dev, 0x400864, vramsz - 1); |
| 625 | nv_wr32(dev, 0x400868, vramsz - 1); |
| 626 | |
| 627 | /* interesting.. the below overwrites some of the tile setup above.. */ |
| 628 | nv_wr32(dev, 0x400B20, 0x00000000); |
| 629 | nv_wr32(dev, 0x400B04, 0xFFFFFFFF); |
| 630 | |
| 631 | nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_XMIN, 0); |
| 632 | nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_YMIN, 0); |
| 633 | nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); |
| 634 | nv_wr32(dev, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); |
| 635 | |
| 636 | return 0; |
| 637 | } |
| 638 | |
| 639 | void |
| 640 | nv20_graph_takedown(struct drm_device *dev) |
| 641 | { |
| 642 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | c50a568 | 2010-07-08 15:40:18 +1000 | [diff] [blame] | 643 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 644 | |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 645 | nouveau_gpuobj_ref(NULL, &pgraph->ctx_table); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 646 | } |
| 647 | |
| 648 | int |
| 649 | nv30_graph_init(struct drm_device *dev) |
| 650 | { |
| 651 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | 816544b | 2010-07-08 13:15:05 +1000 | [diff] [blame] | 652 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 653 | int ret, i; |
| 654 | |
Ben Skeggs | 816544b | 2010-07-08 13:15:05 +1000 | [diff] [blame] | 655 | switch (dev_priv->chipset) { |
| 656 | case 0x30: |
| 657 | case 0x31: |
| 658 | pgraph->grctx_size = NV30_31_GRCTX_SIZE; |
| 659 | break; |
| 660 | case 0x34: |
| 661 | pgraph->grctx_size = NV34_GRCTX_SIZE; |
| 662 | break; |
| 663 | case 0x35: |
| 664 | case 0x36: |
| 665 | pgraph->grctx_size = NV35_36_GRCTX_SIZE; |
| 666 | break; |
| 667 | default: |
| 668 | NV_ERROR(dev, "unknown chipset, disabling acceleration\n"); |
| 669 | pgraph->accel_blocked = true; |
| 670 | return 0; |
| 671 | } |
| 672 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 673 | nv_wr32(dev, NV03_PMC_ENABLE, |
| 674 | nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); |
| 675 | nv_wr32(dev, NV03_PMC_ENABLE, |
| 676 | nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH); |
| 677 | |
Ben Skeggs | c50a568 | 2010-07-08 15:40:18 +1000 | [diff] [blame] | 678 | if (!pgraph->ctx_table) { |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 679 | /* Create Context Pointer Table */ |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 680 | ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16, |
| 681 | NVOBJ_FLAG_ZERO_ALLOC, |
| 682 | &pgraph->ctx_table); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 683 | if (ret) |
| 684 | return ret; |
| 685 | } |
| 686 | |
| 687 | nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, |
Ben Skeggs | a8eaebc | 2010-09-01 15:24:31 +1000 | [diff] [blame] | 688 | pgraph->ctx_table->pinst >> 4); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 689 | |
| 690 | nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF); |
| 691 | nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); |
| 692 | |
| 693 | nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); |
| 694 | nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000); |
| 695 | nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0); |
| 696 | nv_wr32(dev, 0x400890, 0x01b463ff); |
| 697 | nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xf2de0475); |
| 698 | nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000); |
| 699 | nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); |
| 700 | nv_wr32(dev, 0x400B80, 0x1003d888); |
| 701 | nv_wr32(dev, 0x400B84, 0x0c000000); |
| 702 | nv_wr32(dev, 0x400098, 0x00000000); |
| 703 | nv_wr32(dev, 0x40009C, 0x0005ad00); |
| 704 | nv_wr32(dev, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ |
| 705 | nv_wr32(dev, 0x4000a0, 0x00000000); |
| 706 | nv_wr32(dev, 0x4000a4, 0x00000008); |
| 707 | nv_wr32(dev, 0x4008a8, 0xb784a400); |
| 708 | nv_wr32(dev, 0x400ba0, 0x002f8685); |
| 709 | nv_wr32(dev, 0x400ba4, 0x00231f3f); |
| 710 | nv_wr32(dev, 0x4008a4, 0x40000020); |
| 711 | |
| 712 | if (dev_priv->chipset == 0x34) { |
| 713 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); |
| 714 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00200201); |
| 715 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); |
| 716 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000008); |
| 717 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); |
| 718 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000032); |
| 719 | nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, 0x00E00004); |
| 720 | nv_wr32(dev, NV10_PGRAPH_RDI_DATA , 0x00000002); |
| 721 | } |
| 722 | |
| 723 | nv_wr32(dev, 0x4000c0, 0x00000016); |
| 724 | |
Francisco Jerez | 0d87c10 | 2009-12-16 12:12:27 +0100 | [diff] [blame] | 725 | /* Turn all the tiling regions off. */ |
| 726 | for (i = 0; i < NV10_PFB_TILE__SIZE; i++) |
| 727 | nv20_graph_set_region_tiling(dev, i, 0, 0, 0); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 728 | |
| 729 | nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000100); |
| 730 | nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF); |
| 731 | nv_wr32(dev, 0x0040075c , 0x00000001); |
| 732 | |
| 733 | /* begin RAM config */ |
Jordan Crouse | 01d73a6 | 2010-05-27 13:40:24 -0600 | [diff] [blame] | 734 | /* vramsz = pci_resource_len(dev->pdev, 0) - 1; */ |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 735 | nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0)); |
| 736 | nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1)); |
| 737 | if (dev_priv->chipset != 0x34) { |
| 738 | nv_wr32(dev, 0x400750, 0x00EA0000); |
| 739 | nv_wr32(dev, 0x400754, nv_rd32(dev, NV04_PFB_CFG0)); |
| 740 | nv_wr32(dev, 0x400750, 0x00EA0004); |
| 741 | nv_wr32(dev, 0x400754, nv_rd32(dev, NV04_PFB_CFG1)); |
| 742 | } |
| 743 | |
| 744 | return 0; |
| 745 | } |
| 746 | |
| 747 | struct nouveau_pgraph_object_class nv20_graph_grclass[] = { |
| 748 | { 0x0030, false, NULL }, /* null */ |
| 749 | { 0x0039, false, NULL }, /* m2mf */ |
| 750 | { 0x004a, false, NULL }, /* gdirect */ |
| 751 | { 0x009f, false, NULL }, /* imageblit (nv12) */ |
| 752 | { 0x008a, false, NULL }, /* ifc */ |
| 753 | { 0x0089, false, NULL }, /* sifm */ |
| 754 | { 0x0062, false, NULL }, /* surf2d */ |
| 755 | { 0x0043, false, NULL }, /* rop */ |
| 756 | { 0x0012, false, NULL }, /* beta1 */ |
| 757 | { 0x0072, false, NULL }, /* beta4 */ |
| 758 | { 0x0019, false, NULL }, /* cliprect */ |
| 759 | { 0x0044, false, NULL }, /* pattern */ |
| 760 | { 0x009e, false, NULL }, /* swzsurf */ |
| 761 | { 0x0096, false, NULL }, /* celcius */ |
| 762 | { 0x0097, false, NULL }, /* kelvin (nv20) */ |
| 763 | { 0x0597, false, NULL }, /* kelvin (nv25) */ |
| 764 | {} |
| 765 | }; |
| 766 | |
| 767 | struct nouveau_pgraph_object_class nv30_graph_grclass[] = { |
| 768 | { 0x0030, false, NULL }, /* null */ |
| 769 | { 0x0039, false, NULL }, /* m2mf */ |
| 770 | { 0x004a, false, NULL }, /* gdirect */ |
| 771 | { 0x009f, false, NULL }, /* imageblit (nv12) */ |
| 772 | { 0x008a, false, NULL }, /* ifc */ |
| 773 | { 0x038a, false, NULL }, /* ifc (nv30) */ |
| 774 | { 0x0089, false, NULL }, /* sifm */ |
| 775 | { 0x0389, false, NULL }, /* sifm (nv30) */ |
| 776 | { 0x0062, false, NULL }, /* surf2d */ |
| 777 | { 0x0362, false, NULL }, /* surf2d (nv30) */ |
| 778 | { 0x0043, false, NULL }, /* rop */ |
| 779 | { 0x0012, false, NULL }, /* beta1 */ |
| 780 | { 0x0072, false, NULL }, /* beta4 */ |
| 781 | { 0x0019, false, NULL }, /* cliprect */ |
| 782 | { 0x0044, false, NULL }, /* pattern */ |
| 783 | { 0x039e, false, NULL }, /* swzsurf */ |
| 784 | { 0x0397, false, NULL }, /* rankine (nv30) */ |
| 785 | { 0x0497, false, NULL }, /* rankine (nv35) */ |
| 786 | { 0x0697, false, NULL }, /* rankine (nv34) */ |
| 787 | {} |
| 788 | }; |
| 789 | |