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Kumar Gala5516b542007-06-27 01:17:57 -05001/*
2 * Contains common pci routines for ALL ppc platform
Kumar Galacf1d8a82007-06-28 22:56:24 -05003 * (based on pci_32.c and pci_64.c)
4 *
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
10 *
11 * Common pmac/prep/chrp pci routines. -- Cort
Kumar Gala5516b542007-06-27 01:17:57 -050012 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
Kumar Gala5516b542007-06-27 01:17:57 -050019#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
Paul Gortmaker66b15db2011-05-27 10:46:24 -040024#include <linux/export.h>
Grant Likely22ae7822010-07-29 11:49:01 -060025#include <linux/of_address.h>
Sebastian Andrzej Siewior04bea682011-01-24 09:58:55 +053026#include <linux/of_pci.h>
Kumar Gala5516b542007-06-27 01:17:57 -050027#include <linux/mm.h>
28#include <linux/list.h>
29#include <linux/syscalls.h>
30#include <linux/irq.h>
31#include <linux/vmalloc.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Brian Kingc2e1d842013-04-08 03:05:10 +000033#include <linux/vgaarb.h>
Kumar Gala5516b542007-06-27 01:17:57 -050034
35#include <asm/processor.h>
36#include <asm/io.h>
37#include <asm/prom.h>
38#include <asm/pci-bridge.h>
39#include <asm/byteorder.h>
40#include <asm/machdep.h>
41#include <asm/ppc-pci.h>
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +000042#include <asm/eeh.h>
Kumar Gala5516b542007-06-27 01:17:57 -050043
Kumar Galaa4c9e322007-06-27 13:09:43 -050044static DEFINE_SPINLOCK(hose_spinlock);
Milton Millerc3bd5172009-01-08 02:19:46 +000045LIST_HEAD(hose_list);
Kumar Galaa4c9e322007-06-27 13:09:43 -050046
47/* XXX kill that some day ... */
Stephen Rothwellebfc00f2007-11-19 16:56:15 +110048static int global_phb_number; /* Global phb counter */
Kumar Galaa4c9e322007-06-27 13:09:43 -050049
Benjamin Herrenschmidt25e81f92007-12-11 14:48:17 +110050/* ISA Memory physical address */
51resource_size_t isa_mem_base;
52
Kumar Galaa4c9e322007-06-27 13:09:43 -050053
FUJITA Tomonori45223c52009-08-04 19:08:25 +000054static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
Becky Bruce4fc665b2008-09-12 10:34:46 +000055
FUJITA Tomonori45223c52009-08-04 19:08:25 +000056void set_pci_dma_ops(struct dma_map_ops *dma_ops)
Becky Bruce4fc665b2008-09-12 10:34:46 +000057{
58 pci_dma_ops = dma_ops;
59}
60
FUJITA Tomonori45223c52009-08-04 19:08:25 +000061struct dma_map_ops *get_pci_dma_ops(void)
Becky Bruce4fc665b2008-09-12 10:34:46 +000062{
63 return pci_dma_ops;
64}
65EXPORT_SYMBOL(get_pci_dma_ops);
66
Stephen Rothwelle60516e2007-12-11 11:02:07 +110067struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
Kumar Galaa4c9e322007-06-27 13:09:43 -050068{
69 struct pci_controller *phb;
70
Stephen Rothwelle60516e2007-12-11 11:02:07 +110071 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
Kumar Galaa4c9e322007-06-27 13:09:43 -050072 if (phb == NULL)
73 return NULL;
Stephen Rothwelle60516e2007-12-11 11:02:07 +110074 spin_lock(&hose_spinlock);
75 phb->global_number = global_phb_number++;
76 list_add_tail(&phb->list_node, &hose_list);
77 spin_unlock(&hose_spinlock);
Stephen Rothwell44ef3392007-12-10 14:33:21 +110078 phb->dn = dev;
Kumar Galaa4c9e322007-06-27 13:09:43 -050079 phb->is_dynamic = mem_init_done;
80#ifdef CONFIG_PPC64
81 if (dev) {
82 int nid = of_node_to_nid(dev);
83
84 if (nid < 0 || !node_online(nid))
85 nid = -1;
86
87 PHB_SET_NODE(phb, nid);
88 }
89#endif
90 return phb;
91}
92
93void pcibios_free_controller(struct pci_controller *phb)
94{
95 spin_lock(&hose_spinlock);
96 list_del(&phb->list_node);
97 spin_unlock(&hose_spinlock);
98
99 if (phb->is_dynamic)
100 kfree(phb);
101}
102
Gavin Shan4c2245b2012-09-11 16:59:46 -0600103/*
104 * The function is used to return the minimal alignment
105 * for memory or I/O windows of the associated P2P bridge.
106 * By default, 4KiB alignment for I/O windows and 1MiB for
107 * memory windows.
108 */
109resource_size_t pcibios_window_alignment(struct pci_bus *bus,
110 unsigned long type)
111{
112 if (ppc_md.pcibios_window_alignment)
113 return ppc_md.pcibios_window_alignment(bus, type);
114
115 /*
116 * PCI core will figure out the default
117 * alignment: 4KiB for I/O and 1MiB for
118 * memory window.
119 */
120 return 1;
121}
122
Milton Millerc3bd5172009-01-08 02:19:46 +0000123static resource_size_t pcibios_io_size(const struct pci_controller *hose)
124{
125#ifdef CONFIG_PPC64
126 return hose->pci_io_size;
127#else
Joe Perches28f65c12011-06-09 09:13:32 -0700128 return resource_size(&hose->io_resource);
Milton Millerc3bd5172009-01-08 02:19:46 +0000129#endif
130}
131
Benjamin Herrenschmidt6dfbde22007-07-26 14:07:13 +1000132int pcibios_vaddr_is_ioport(void __iomem *address)
133{
134 int ret = 0;
135 struct pci_controller *hose;
Milton Millerc3bd5172009-01-08 02:19:46 +0000136 resource_size_t size;
Benjamin Herrenschmidt6dfbde22007-07-26 14:07:13 +1000137
138 spin_lock(&hose_spinlock);
139 list_for_each_entry(hose, &hose_list, list_node) {
Milton Millerc3bd5172009-01-08 02:19:46 +0000140 size = pcibios_io_size(hose);
Benjamin Herrenschmidt6dfbde22007-07-26 14:07:13 +1000141 if (address >= hose->io_base_virt &&
142 address < (hose->io_base_virt + size)) {
143 ret = 1;
144 break;
145 }
146 }
147 spin_unlock(&hose_spinlock);
148 return ret;
149}
150
Milton Millerc3bd5172009-01-08 02:19:46 +0000151unsigned long pci_address_to_pio(phys_addr_t address)
152{
153 struct pci_controller *hose;
154 resource_size_t size;
155 unsigned long ret = ~0;
156
157 spin_lock(&hose_spinlock);
158 list_for_each_entry(hose, &hose_list, list_node) {
159 size = pcibios_io_size(hose);
160 if (address >= hose->io_base_phys &&
161 address < (hose->io_base_phys + size)) {
162 unsigned long base =
163 (unsigned long)hose->io_base_virt - _IO_BASE;
164 ret = base + (address - hose->io_base_phys);
165 break;
166 }
167 }
168 spin_unlock(&hose_spinlock);
169
170 return ret;
171}
172EXPORT_SYMBOL_GPL(pci_address_to_pio);
173
Kumar Gala5516b542007-06-27 01:17:57 -0500174/*
175 * Return the domain number for this bus.
176 */
177int pci_domain_nr(struct pci_bus *bus)
178{
Stephen Rothwell6207e812007-12-07 02:04:33 +1100179 struct pci_controller *hose = pci_bus_to_host(bus);
Kumar Gala5516b542007-06-27 01:17:57 -0500180
Stephen Rothwell6207e812007-12-07 02:04:33 +1100181 return hose->global_number;
Kumar Gala5516b542007-06-27 01:17:57 -0500182}
Kumar Gala5516b542007-06-27 01:17:57 -0500183EXPORT_SYMBOL(pci_domain_nr);
Kumar Gala58083da2007-06-27 11:07:51 -0500184
Kumar Galaa4c9e322007-06-27 13:09:43 -0500185/* This routine is meant to be used early during boot, when the
186 * PCI bus numbers have not yet been assigned, and you need to
187 * issue PCI config cycles to an OF device.
188 * It could also be used to "fix" RTAS config cycles if you want
189 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
190 * config cycles.
191 */
192struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
193{
Kumar Galaa4c9e322007-06-27 13:09:43 -0500194 while(node) {
195 struct pci_controller *hose, *tmp;
196 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
Stephen Rothwell44ef3392007-12-10 14:33:21 +1100197 if (hose->dn == node)
Kumar Galaa4c9e322007-06-27 13:09:43 -0500198 return hose;
199 node = node->parent;
200 }
201 return NULL;
202}
203
Kumar Gala58083da2007-06-27 11:07:51 -0500204static ssize_t pci_show_devspec(struct device *dev,
205 struct device_attribute *attr, char *buf)
206{
207 struct pci_dev *pdev;
208 struct device_node *np;
209
210 pdev = to_pci_dev (dev);
211 np = pci_device_to_OF_node(pdev);
212 if (np == NULL || np->full_name == NULL)
213 return 0;
214 return sprintf(buf, "%s", np->full_name);
215}
216static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
Kumar Gala58083da2007-06-27 11:07:51 -0500217
218/* Add sysfs properties */
Tony Breeds4f3731d2007-07-18 11:03:55 +1000219int pcibios_add_platform_entries(struct pci_dev *pdev)
Kumar Gala58083da2007-06-27 11:07:51 -0500220{
Tony Breeds4f3731d2007-07-18 11:03:55 +1000221 return device_create_file(&pdev->dev, &dev_attr_devspec);
Kumar Gala58083da2007-06-27 11:07:51 -0500222}
223
Kumar Gala58083da2007-06-27 11:07:51 -0500224/*
225 * Reads the interrupt pin to determine if interrupt is use by card.
226 * If the interrupt is used, then gets the interrupt line from the
227 * openfirmware and sets it in the pci_dev and pci_config line.
228 */
Benjamin Herrenschmidt4666ca22011-11-29 20:16:25 +0000229static int pci_read_irq_line(struct pci_dev *pci_dev)
Kumar Gala58083da2007-06-27 11:07:51 -0500230{
231 struct of_irq oirq;
232 unsigned int virq;
233
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +0000234 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
Kumar Gala58083da2007-06-27 11:07:51 -0500235
236#ifdef DEBUG
237 memset(&oirq, 0xff, sizeof(oirq));
238#endif
239 /* Try to get a mapping from the device-tree */
240 if (of_irq_map_pci(pci_dev, &oirq)) {
241 u8 line, pin;
242
243 /* If that fails, lets fallback to what is in the config
244 * space and map that through the default controller. We
245 * also set the type to level low since that's what PCI
246 * interrupts are. If your platform does differently, then
247 * either provide a proper interrupt tree or don't use this
248 * function.
249 */
250 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
251 return -1;
252 if (pin == 0)
253 return -1;
254 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
Benjamin Herrenschmidt54a24cb2007-12-20 15:10:02 +1100255 line == 0xff || line == 0) {
Kumar Gala58083da2007-06-27 11:07:51 -0500256 return -1;
257 }
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +0000258 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
259 line, pin);
Kumar Gala58083da2007-06-27 11:07:51 -0500260
261 virq = irq_create_mapping(NULL, line);
262 if (virq != NO_IRQ)
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100263 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
Kumar Gala58083da2007-06-27 11:07:51 -0500264 } else {
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +0000265 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
266 oirq.size, oirq.specifier[0], oirq.specifier[1],
Grant Likely74a7f082012-06-15 11:50:25 -0600267 of_node_full_name(oirq.controller));
Kumar Gala58083da2007-06-27 11:07:51 -0500268
269 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
270 oirq.size);
271 }
272 if(virq == NO_IRQ) {
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +0000273 pr_debug(" Failed to map !\n");
Kumar Gala58083da2007-06-27 11:07:51 -0500274 return -1;
275 }
276
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +0000277 pr_debug(" Mapped to linux irq %d\n", virq);
Kumar Gala58083da2007-06-27 11:07:51 -0500278
279 pci_dev->irq = virq;
280
281 return 0;
282}
Kumar Gala58083da2007-06-27 11:07:51 -0500283
284/*
285 * Platform support for /proc/bus/pci/X/Y mmap()s,
286 * modelled on the sparc64 implementation by Dave Miller.
287 * -- paulus.
288 */
289
290/*
291 * Adjust vm_pgoff of VMA such that it is the physical page offset
292 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
293 *
294 * Basically, the user finds the base address for his device which he wishes
295 * to mmap. They read the 32-bit value from the config space base register,
296 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
297 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
298 *
299 * Returns negative error code on failure, zero on success.
300 */
301static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
302 resource_size_t *offset,
303 enum pci_mmap_state mmap_state)
304{
305 struct pci_controller *hose = pci_bus_to_host(dev->bus);
306 unsigned long io_offset = 0;
307 int i, res_bit;
308
309 if (hose == 0)
310 return NULL; /* should never happen */
311
312 /* If memory, add on the PCI bridge address offset */
313 if (mmap_state == pci_mmap_mem) {
314#if 0 /* See comment in pci_resource_to_user() for why this is disabled */
315 *offset += hose->pci_mem_offset;
316#endif
317 res_bit = IORESOURCE_MEM;
318 } else {
319 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
320 *offset += io_offset;
321 res_bit = IORESOURCE_IO;
322 }
323
324 /*
325 * Check that the offset requested corresponds to one of the
326 * resources of the device.
327 */
328 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
329 struct resource *rp = &dev->resource[i];
330 int flags = rp->flags;
331
332 /* treat ROM as memory (should be already) */
333 if (i == PCI_ROM_RESOURCE)
334 flags |= IORESOURCE_MEM;
335
336 /* Active and same type? */
337 if ((flags & res_bit) == 0)
338 continue;
339
340 /* In the range of this resource? */
341 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
342 continue;
343
344 /* found it! construct the final physical address */
345 if (mmap_state == pci_mmap_io)
346 *offset += hose->io_base_phys - io_offset;
347 return rp;
348 }
349
350 return NULL;
351}
352
353/*
354 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
355 * device mapping.
356 */
357static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
358 pgprot_t protection,
359 enum pci_mmap_state mmap_state,
360 int write_combine)
361{
Kumar Gala58083da2007-06-27 11:07:51 -0500362
363 /* Write combine is always 0 on non-memory space mappings. On
364 * memory space, if the user didn't pass 1, we check for a
365 * "prefetchable" resource. This is a bit hackish, but we use
366 * this to workaround the inability of /sysfs to provide a write
367 * combine bit
368 */
369 if (mmap_state != pci_mmap_mem)
370 write_combine = 0;
371 else if (write_combine == 0) {
372 if (rp->flags & IORESOURCE_PREFETCH)
373 write_combine = 1;
374 }
375
376 /* XXX would be nice to have a way to ask for write-through */
Kumar Gala58083da2007-06-27 11:07:51 -0500377 if (write_combine)
Aneesh Kumar K.V83d5e642013-05-06 10:51:00 +0000378 return pgprot_noncached_wc(protection);
Kumar Gala58083da2007-06-27 11:07:51 -0500379 else
Aneesh Kumar K.V83d5e642013-05-06 10:51:00 +0000380 return pgprot_noncached(protection);
Kumar Gala58083da2007-06-27 11:07:51 -0500381}
382
383/*
384 * This one is used by /dev/mem and fbdev who have no clue about the
385 * PCI device, it tries to find the PCI device first and calls the
386 * above routine
387 */
388pgprot_t pci_phys_mem_access_prot(struct file *file,
389 unsigned long pfn,
390 unsigned long size,
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000391 pgprot_t prot)
Kumar Gala58083da2007-06-27 11:07:51 -0500392{
393 struct pci_dev *pdev = NULL;
394 struct resource *found = NULL;
Benjamin Herrenschmidt7c12d902008-10-01 15:30:04 +0000395 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
Kumar Gala58083da2007-06-27 11:07:51 -0500396 int i;
397
398 if (page_is_ram(pfn))
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000399 return prot;
Kumar Gala58083da2007-06-27 11:07:51 -0500400
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000401 prot = pgprot_noncached(prot);
Kumar Gala58083da2007-06-27 11:07:51 -0500402 for_each_pci_dev(pdev) {
403 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
404 struct resource *rp = &pdev->resource[i];
405 int flags = rp->flags;
406
407 /* Active and same type? */
408 if ((flags & IORESOURCE_MEM) == 0)
409 continue;
410 /* In the range of this resource? */
411 if (offset < (rp->start & PAGE_MASK) ||
412 offset > rp->end)
413 continue;
414 found = rp;
415 break;
416 }
417 if (found)
418 break;
419 }
420 if (found) {
421 if (found->flags & IORESOURCE_PREFETCH)
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000422 prot = pgprot_noncached_wc(prot);
Kumar Gala58083da2007-06-27 11:07:51 -0500423 pci_dev_put(pdev);
424 }
425
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +0000426 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000427 (unsigned long long)offset, pgprot_val(prot));
Kumar Gala58083da2007-06-27 11:07:51 -0500428
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000429 return prot;
Kumar Gala58083da2007-06-27 11:07:51 -0500430}
431
432
433/*
434 * Perform the actual remap of the pages for a PCI device mapping, as
435 * appropriate for this architecture. The region in the process to map
436 * is described by vm_start and vm_end members of VMA, the base physical
437 * address is found in vm_pgoff.
438 * The pci device structure is provided so that architectures may make mapping
439 * decisions on a per-device or per-bus basis.
440 *
441 * Returns a negative error code on failure, zero on success.
442 */
443int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
444 enum pci_mmap_state mmap_state, int write_combine)
445{
Benjamin Herrenschmidt7c12d902008-10-01 15:30:04 +0000446 resource_size_t offset =
447 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
Kumar Gala58083da2007-06-27 11:07:51 -0500448 struct resource *rp;
449 int ret;
450
451 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
452 if (rp == NULL)
453 return -EINVAL;
454
455 vma->vm_pgoff = offset >> PAGE_SHIFT;
456 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
457 vma->vm_page_prot,
458 mmap_state, write_combine);
459
460 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
461 vma->vm_end - vma->vm_start, vma->vm_page_prot);
462
463 return ret;
464}
465
Benjamin Herrenschmidte9f82cb2008-10-14 11:55:31 +1100466/* This provides legacy IO read access on a bus */
467int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
468{
469 unsigned long offset;
470 struct pci_controller *hose = pci_bus_to_host(bus);
471 struct resource *rp = &hose->io_resource;
472 void __iomem *addr;
473
474 /* Check if port can be supported by that bus. We only check
475 * the ranges of the PHB though, not the bus itself as the rules
476 * for forwarding legacy cycles down bridges are not our problem
477 * here. So if the host bridge supports it, we do it.
478 */
479 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
480 offset += port;
481
482 if (!(rp->flags & IORESOURCE_IO))
483 return -ENXIO;
484 if (offset < rp->start || (offset + size) > rp->end)
485 return -ENXIO;
486 addr = hose->io_base_virt + port;
487
488 switch(size) {
489 case 1:
490 *((u8 *)val) = in_8(addr);
491 return 1;
492 case 2:
493 if (port & 1)
494 return -EINVAL;
495 *((u16 *)val) = in_le16(addr);
496 return 2;
497 case 4:
498 if (port & 3)
499 return -EINVAL;
500 *((u32 *)val) = in_le32(addr);
501 return 4;
502 }
503 return -EINVAL;
504}
505
506/* This provides legacy IO write access on a bus */
507int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
508{
509 unsigned long offset;
510 struct pci_controller *hose = pci_bus_to_host(bus);
511 struct resource *rp = &hose->io_resource;
512 void __iomem *addr;
513
514 /* Check if port can be supported by that bus. We only check
515 * the ranges of the PHB though, not the bus itself as the rules
516 * for forwarding legacy cycles down bridges are not our problem
517 * here. So if the host bridge supports it, we do it.
518 */
519 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
520 offset += port;
521
522 if (!(rp->flags & IORESOURCE_IO))
523 return -ENXIO;
524 if (offset < rp->start || (offset + size) > rp->end)
525 return -ENXIO;
526 addr = hose->io_base_virt + port;
527
528 /* WARNING: The generic code is idiotic. It gets passed a pointer
529 * to what can be a 1, 2 or 4 byte quantity and always reads that
530 * as a u32, which means that we have to correct the location of
531 * the data read within those 32 bits for size 1 and 2
532 */
533 switch(size) {
534 case 1:
535 out_8(addr, val >> 24);
536 return 1;
537 case 2:
538 if (port & 1)
539 return -EINVAL;
540 out_le16(addr, val >> 16);
541 return 2;
542 case 4:
543 if (port & 3)
544 return -EINVAL;
545 out_le32(addr, val);
546 return 4;
547 }
548 return -EINVAL;
549}
550
551/* This provides legacy IO or memory mmap access on a bus */
552int pci_mmap_legacy_page_range(struct pci_bus *bus,
553 struct vm_area_struct *vma,
554 enum pci_mmap_state mmap_state)
555{
556 struct pci_controller *hose = pci_bus_to_host(bus);
557 resource_size_t offset =
558 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
559 resource_size_t size = vma->vm_end - vma->vm_start;
560 struct resource *rp;
561
562 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
563 pci_domain_nr(bus), bus->number,
564 mmap_state == pci_mmap_mem ? "MEM" : "IO",
565 (unsigned long long)offset,
566 (unsigned long long)(offset + size - 1));
567
568 if (mmap_state == pci_mmap_mem) {
Benjamin Herrenschmidt5b11abf2009-02-08 14:27:21 +0000569 /* Hack alert !
570 *
571 * Because X is lame and can fail starting if it gets an error trying
572 * to mmap legacy_mem (instead of just moving on without legacy memory
573 * access) we fake it here by giving it anonymous memory, effectively
574 * behaving just like /dev/zero
575 */
576 if ((offset + size) > hose->isa_mem_size) {
577 printk(KERN_DEBUG
578 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
579 current->comm, current->pid, pci_domain_nr(bus), bus->number);
580 if (vma->vm_flags & VM_SHARED)
581 return shmem_zero_setup(vma);
582 return 0;
583 }
Benjamin Herrenschmidte9f82cb2008-10-14 11:55:31 +1100584 offset += hose->isa_mem_phys;
585 } else {
586 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
587 unsigned long roffset = offset + io_offset;
588 rp = &hose->io_resource;
589 if (!(rp->flags & IORESOURCE_IO))
590 return -ENXIO;
591 if (roffset < rp->start || (roffset + size) > rp->end)
592 return -ENXIO;
593 offset += hose->io_base_phys;
594 }
595 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
596
597 vma->vm_pgoff = offset >> PAGE_SHIFT;
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000598 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
Benjamin Herrenschmidte9f82cb2008-10-14 11:55:31 +1100599 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
600 vma->vm_end - vma->vm_start,
601 vma->vm_page_prot);
602}
603
Kumar Gala58083da2007-06-27 11:07:51 -0500604void pci_resource_to_user(const struct pci_dev *dev, int bar,
605 const struct resource *rsrc,
606 resource_size_t *start, resource_size_t *end)
607{
608 struct pci_controller *hose = pci_bus_to_host(dev->bus);
609 resource_size_t offset = 0;
610
611 if (hose == NULL)
612 return;
613
614 if (rsrc->flags & IORESOURCE_IO)
615 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
616
617 /* We pass a fully fixed up address to userland for MMIO instead of
618 * a BAR value because X is lame and expects to be able to use that
619 * to pass to /dev/mem !
620 *
621 * That means that we'll have potentially 64 bits values where some
622 * userland apps only expect 32 (like X itself since it thinks only
623 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
624 * 32 bits CHRPs :-(
625 *
626 * Hopefully, the sysfs insterface is immune to that gunk. Once X
627 * has been fixed (and the fix spread enough), we can re-enable the
628 * 2 lines below and pass down a BAR value to userland. In that case
629 * we'll also have to re-enable the matching code in
630 * __pci_mmap_make_offset().
631 *
632 * BenH.
633 */
634#if 0
635 else if (rsrc->flags & IORESOURCE_MEM)
636 offset = hose->pci_mem_offset;
637#endif
638
639 *start = rsrc->start - offset;
640 *end = rsrc->end - offset;
641}
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100642
643/**
644 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
645 * @hose: newly allocated pci_controller to be setup
646 * @dev: device node of the host bridge
647 * @primary: set if primary bus (32 bits only, soon to be deprecated)
648 *
649 * This function will parse the "ranges" property of a PCI host bridge device
650 * node and setup the resource mapping of a pci controller based on its
651 * content.
652 *
653 * Life would be boring if it wasn't for a few issues that we have to deal
654 * with here:
655 *
656 * - We can only cope with one IO space range and up to 3 Memory space
657 * ranges. However, some machines (thanks Apple !) tend to split their
658 * space into lots of small contiguous ranges. So we have to coalesce.
659 *
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100660 * - Some busses have IO space not starting at 0, which causes trouble with
661 * the way we do our IO resource renumbering. The code somewhat deals with
662 * it for 64 bits but I would expect problems on 32 bits.
663 *
664 * - Some 32 bits platforms such as 4xx can have physical space larger than
665 * 32 bits so we need to use 64 bits values for the parsing
666 */
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -0800667void pci_process_bridge_OF_ranges(struct pci_controller *hose,
668 struct device_node *dev, int primary)
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100669{
670 const u32 *ranges;
671 int rlen;
672 int pna = of_n_addr_cells(dev);
673 int np = pna + 5;
Kevin Hao858957a2013-05-16 20:58:42 +0000674 int memno = 0;
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100675 u32 pci_space;
676 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100677 struct resource *res;
678
679 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
680 dev->full_name, primary ? "(primary)" : "");
681
682 /* Get ranges property */
683 ranges = of_get_property(dev, "ranges", &rlen);
684 if (ranges == NULL)
685 return;
686
687 /* Parse it */
688 while ((rlen -= np * 4) >= 0) {
689 /* Read next ranges element */
690 pci_space = ranges[0];
691 pci_addr = of_read_number(ranges + 1, 2);
692 cpu_addr = of_translate_address(dev, ranges + 3);
693 size = of_read_number(ranges + pna + 3, 2);
694 ranges += np;
Benjamin Herrenschmidte9f82cb2008-10-14 11:55:31 +1100695
696 /* If we failed translation or got a zero-sized region
697 * (some FW try to feed us with non sensical zero sized regions
698 * such as power3 which look like some kind of attempt at exposing
699 * the VGA memory hole)
700 */
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100701 if (cpu_addr == OF_BAD_ADDR || size == 0)
702 continue;
703
704 /* Now consume following elements while they are contiguous */
705 for (; rlen >= np * sizeof(u32);
706 ranges += np, rlen -= np * 4) {
707 if (ranges[0] != pci_space)
708 break;
709 pci_next = of_read_number(ranges + 1, 2);
710 cpu_next = of_translate_address(dev, ranges + 3);
711 if (pci_next != pci_addr + size ||
712 cpu_next != cpu_addr + size)
713 break;
714 size += of_read_number(ranges + pna + 3, 2);
715 }
716
717 /* Act based on address space type */
718 res = NULL;
719 switch ((pci_space >> 24) & 0x3) {
720 case 1: /* PCI IO space */
721 printk(KERN_INFO
722 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
723 cpu_addr, cpu_addr + size - 1, pci_addr);
724
725 /* We support only one IO range */
726 if (hose->pci_io_size) {
727 printk(KERN_INFO
728 " \\--> Skipped (too many) !\n");
729 continue;
730 }
731#ifdef CONFIG_PPC32
732 /* On 32 bits, limit I/O space to 16MB */
733 if (size > 0x01000000)
734 size = 0x01000000;
735
736 /* 32 bits needs to map IOs here */
737 hose->io_base_virt = ioremap(cpu_addr, size);
738
739 /* Expect trouble if pci_addr is not 0 */
740 if (primary)
741 isa_io_base =
742 (unsigned long)hose->io_base_virt;
743#endif /* CONFIG_PPC32 */
744 /* pci_io_size and io_base_phys always represent IO
745 * space starting at 0 so we factor in pci_addr
746 */
747 hose->pci_io_size = pci_addr + size;
748 hose->io_base_phys = cpu_addr - pci_addr;
749
750 /* Build resource */
751 res = &hose->io_resource;
752 res->flags = IORESOURCE_IO;
753 res->start = pci_addr;
754 break;
755 case 2: /* PCI Memory space */
Benjamin Herrenschmidt67260ac2008-07-17 15:53:31 +1000756 case 3: /* PCI 64 bits Memory space */
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100757 printk(KERN_INFO
758 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
759 cpu_addr, cpu_addr + size - 1, pci_addr,
760 (pci_space & 0x40000000) ? "Prefetch" : "");
761
762 /* We support only 3 memory ranges */
763 if (memno >= 3) {
764 printk(KERN_INFO
765 " \\--> Skipped (too many) !\n");
766 continue;
767 }
768 /* Handles ISA memory hole space here */
769 if (pci_addr == 0) {
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100770 if (primary || isa_mem_base == 0)
771 isa_mem_base = cpu_addr;
Benjamin Herrenschmidte9f82cb2008-10-14 11:55:31 +1100772 hose->isa_mem_phys = cpu_addr;
773 hose->isa_mem_size = size;
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100774 }
775
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100776 /* Build resource */
Benjamin Herrenschmidt3fd47f02013-05-06 13:40:40 +1000777 hose->mem_offset[memno] = cpu_addr - pci_addr;
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100778 res = &hose->mem_resources[memno++];
779 res->flags = IORESOURCE_MEM;
780 if (pci_space & 0x40000000)
781 res->flags |= IORESOURCE_PREFETCH;
782 res->start = cpu_addr;
783 break;
784 }
785 if (res != NULL) {
786 res->name = dev->full_name;
787 res->end = res->start + size - 1;
788 res->parent = NULL;
789 res->sibling = NULL;
790 res->child = NULL;
791 }
792 }
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100793}
Benjamin Herrenschmidtfa462f22007-12-20 14:54:49 +1100794
795/* Decide whether to display the domain number in /proc */
796int pci_proc_domain(struct pci_bus *bus)
797{
798 struct pci_controller *hose = pci_bus_to_host(bus);
Benjamin Herrenschmidt1fd0f522008-10-02 14:12:51 +0000799
Rob Herring0e47ff12011-07-12 09:25:51 -0500800 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
Benjamin Herrenschmidtfa462f22007-12-20 14:54:49 +1100801 return 0;
Rob Herring0e47ff12011-07-12 09:25:51 -0500802 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
Benjamin Herrenschmidtfa462f22007-12-20 14:54:49 +1100803 return hose->global_number != 0;
804 return 1;
Benjamin Herrenschmidtfa462f22007-12-20 14:54:49 +1100805}
806
Kleber Sacilotto de Souzad82fb312013-05-03 12:43:12 +0000807int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
808{
809 if (ppc_md.pcibios_root_bridge_prepare)
810 return ppc_md.pcibios_root_bridge_prepare(bridge);
811
812 return 0;
813}
814
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100815/* This header fixup will do the resource fixup for all devices as they are
816 * probed, but not for bridge ranges
817 */
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -0800818static void pcibios_fixup_resources(struct pci_dev *dev)
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100819{
820 struct pci_controller *hose = pci_bus_to_host(dev->bus);
821 int i;
822
823 if (!hose) {
824 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
825 pci_name(dev));
826 return;
827 }
828 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
829 struct resource *res = dev->resource + i;
Kevin Haoc5df4572013-06-05 02:26:51 +0000830 struct pci_bus_region reg;
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100831 if (!res->flags)
832 continue;
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +0000833
834 /* If we're going to re-assign everything, we mark all resources
835 * as unset (and 0-base them). In addition, we mark BARs starting
836 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
837 * since in that case, we don't want to re-assign anything
Benjamin Herrenschmidt7f172892008-02-29 14:58:03 +1100838 */
Kevin Haoc5df4572013-06-05 02:26:51 +0000839 pcibios_resource_to_bus(dev, &reg, res);
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +0000840 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
Kevin Haoc5df4572013-06-05 02:26:51 +0000841 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +0000842 /* Only print message if not re-assigning */
843 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
844 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
845 "is unassigned\n",
846 pci_name(dev), i,
847 (unsigned long long)res->start,
848 (unsigned long long)res->end,
849 (unsigned int)res->flags);
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100850 res->end -= res->start;
851 res->start = 0;
852 res->flags |= IORESOURCE_UNSET;
853 continue;
854 }
855
Bjorn Helgaas6c5705f2012-02-23 20:19:03 -0700856 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100857 pci_name(dev), i,
858 (unsigned long long)res->start,\
859 (unsigned long long)res->end,
860 (unsigned int)res->flags);
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100861 }
862
863 /* Call machine specific resource fixup */
864 if (ppc_md.pcibios_fixup_resources)
865 ppc_md.pcibios_fixup_resources(dev);
866}
867DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
868
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000869/* This function tries to figure out if a bridge resource has been initialized
870 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
871 * things go more smoothly when it gets it right. It should covers cases such
872 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
873 */
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -0800874static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
875 struct resource *res)
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100876{
Benjamin Herrenschmidtbe8cbcd2007-12-20 14:55:04 +1100877 struct pci_controller *hose = pci_bus_to_host(bus);
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100878 struct pci_dev *dev = bus->self;
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000879 resource_size_t offset;
Benjamin Herrenschmidt3fd47f02013-05-06 13:40:40 +1000880 struct pci_bus_region region;
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000881 u16 command;
882 int i;
883
884 /* We don't do anything if PCI_PROBE_ONLY is set */
Rob Herring0e47ff12011-07-12 09:25:51 -0500885 if (pci_has_flag(PCI_PROBE_ONLY))
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000886 return 0;
887
888 /* Job is a bit different between memory and IO */
889 if (res->flags & IORESOURCE_MEM) {
Benjamin Herrenschmidt3fd47f02013-05-06 13:40:40 +1000890 pcibios_resource_to_bus(dev, &region, res);
891
892 /* If the BAR is non-0 then it's probably been initialized */
893 if (region.start != 0)
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000894 return 0;
895
896 /* The BAR is 0, let's check if memory decoding is enabled on
897 * the bridge. If not, we consider it unassigned
898 */
899 pci_read_config_word(dev, PCI_COMMAND, &command);
900 if ((command & PCI_COMMAND_MEMORY) == 0)
901 return 1;
902
903 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
904 * resources covers that starting address (0 then it's good enough for
Benjamin Herrenschmidt3fd47f02013-05-06 13:40:40 +1000905 * us for memory space)
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000906 */
907 for (i = 0; i < 3; i++) {
908 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
Benjamin Herrenschmidt3fd47f02013-05-06 13:40:40 +1000909 hose->mem_resources[i].start == hose->mem_offset[i])
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000910 return 0;
911 }
912
913 /* Well, it starts at 0 and we know it will collide so we may as
914 * well consider it as unassigned. That covers the Apple case.
915 */
916 return 1;
917 } else {
918 /* If the BAR is non-0, then we consider it assigned */
919 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
920 if (((res->start - offset) & 0xfffffffful) != 0)
921 return 0;
922
923 /* Here, we are a bit different than memory as typically IO space
924 * starting at low addresses -is- valid. What we do instead if that
925 * we consider as unassigned anything that doesn't have IO enabled
926 * in the PCI command register, and that's it.
927 */
928 pci_read_config_word(dev, PCI_COMMAND, &command);
929 if (command & PCI_COMMAND_IO)
930 return 0;
931
932 /* It's starting at 0 and IO is disabled in the bridge, consider
933 * it unassigned
934 */
935 return 1;
936 }
937}
938
939/* Fixup resources of a PCI<->PCI bridge */
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -0800940static void pcibios_fixup_bridge(struct pci_bus *bus)
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000941{
942 struct resource *res;
943 int i;
944
945 struct pci_dev *dev = bus->self;
946
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700947 pci_bus_for_each_resource(bus, res, i) {
948 if (!res || !res->flags)
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000949 continue;
950 if (i >= 3 && bus->self->transparent)
951 continue;
952
Gavin Shancf1a4cf2012-06-03 22:15:25 +0000953 /* If we're going to reassign everything, we can
954 * shrink the P2P resource to have size as being
955 * of 0 in order to save space.
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +0000956 */
957 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
958 res->flags |= IORESOURCE_UNSET;
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +0000959 res->start = 0;
Gavin Shancf1a4cf2012-06-03 22:15:25 +0000960 res->end = -1;
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +0000961 continue;
962 }
963
Bjorn Helgaas6c5705f2012-02-23 20:19:03 -0700964 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000965 pci_name(dev), i,
966 (unsigned long long)res->start,\
967 (unsigned long long)res->end,
968 (unsigned int)res->flags);
969
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000970 /* Try to detect uninitialized P2P bridge resources,
971 * and clear them out so they get re-assigned later
972 */
973 if (pcibios_uninitialized_bridge_resource(bus, res)) {
974 res->flags = 0;
975 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000976 }
977 }
978}
979
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -0800980void pcibios_setup_bus_self(struct pci_bus *bus)
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +0000981{
Benjamin Herrenschmidt7eef4402008-10-27 19:48:56 +0000982 /* Fix up the bus resources for P2P bridges */
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +0000983 if (bus->self != NULL)
984 pcibios_fixup_bridge(bus);
985
986 /* Platform specific bus fixups. This is currently only used
Benjamin Herrenschmidt7eef4402008-10-27 19:48:56 +0000987 * by fsl_pci and I'm hoping to get rid of it at some point
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +0000988 */
989 if (ppc_md.pcibios_fixup_bus)
990 ppc_md.pcibios_fixup_bus(bus);
991
992 /* Setup bus DMA mappings */
993 if (ppc_md.pci_dma_bus_setup)
994 ppc_md.pci_dma_bus_setup(bus);
995}
996
Guenter Roeck7846de42013-06-10 10:18:08 -0700997static void pcibios_setup_device(struct pci_dev *dev)
Yuanquan Chen37f02192013-04-02 01:26:54 +0000998{
999 /* Fixup NUMA node as it may not be setup yet by the generic
1000 * code and is needed by the DMA init
1001 */
1002 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1003
1004 /* Hook up default DMA ops */
1005 set_dma_ops(&dev->dev, pci_dma_ops);
1006 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1007
1008 /* Additional platform DMA/iommu setup */
1009 if (ppc_md.pci_dma_dev_setup)
1010 ppc_md.pci_dma_dev_setup(dev);
1011
1012 /* Read default IRQs and fixup if necessary */
1013 pci_read_irq_line(dev);
1014 if (ppc_md.pci_irq_fixup)
1015 ppc_md.pci_irq_fixup(dev);
1016}
1017
Guenter Roeck7846de42013-06-10 10:18:08 -07001018int pcibios_add_device(struct pci_dev *dev)
1019{
1020 /*
1021 * We can only call pcibios_setup_device() after bus setup is complete,
1022 * since some of the platform specific DMA setup code depends on it.
1023 */
1024 if (dev->bus->is_added)
1025 pcibios_setup_device(dev);
1026 return 0;
1027}
1028
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -08001029void pcibios_setup_bus_devices(struct pci_bus *bus)
Benjamin Herrenschmidt7eef4402008-10-27 19:48:56 +00001030{
1031 struct pci_dev *dev;
1032
1033 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1034 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1035
1036 list_for_each_entry(dev, &bus->devices, bus_list) {
Benjamin Herrenschmidt2d1c8612009-12-09 17:52:13 +11001037 /* Cardbus can call us to add new devices to a bus, so ignore
1038 * those who are already fully discovered
1039 */
1040 if (dev->is_added)
1041 continue;
1042
Yuanquan Chen37f02192013-04-02 01:26:54 +00001043 pcibios_setup_device(dev);
Benjamin Herrenschmidt7eef4402008-10-27 19:48:56 +00001044 }
1045}
1046
Myron Stowe79c8be82011-10-28 15:48:03 -06001047void pcibios_set_master(struct pci_dev *dev)
1048{
1049 /* No special bus mastering setup handling */
1050}
1051
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -08001052void pcibios_fixup_bus(struct pci_bus *bus)
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +11001053{
1054 /* When called from the generic PCI probe, read PCI<->PCI bridge
Benjamin Herrenschmidt7eef4402008-10-27 19:48:56 +00001055 * bases. This is -not- called when generating the PCI tree from
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +00001056 * the OF device-tree.
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +11001057 */
1058 if (bus->self != NULL)
1059 pci_read_bridge_bases(bus);
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +00001060
1061 /* Now fixup the bus bus */
1062 pcibios_setup_bus_self(bus);
1063
1064 /* Now fixup devices on that bus */
1065 pcibios_setup_bus_devices(bus);
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +11001066}
1067EXPORT_SYMBOL(pcibios_fixup_bus);
1068
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -08001069void pci_fixup_cardbus(struct pci_bus *bus)
Benjamin Herrenschmidt2d1c8612009-12-09 17:52:13 +11001070{
1071 /* Now fixup devices on that bus */
1072 pcibios_setup_bus_devices(bus);
1073}
1074
1075
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001076static int skip_isa_ioresource_align(struct pci_dev *dev)
1077{
Rob Herring0e47ff12011-07-12 09:25:51 -05001078 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001079 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1080 return 1;
1081 return 0;
1082}
1083
1084/*
1085 * We need to avoid collisions with `mirrored' VGA ports
1086 * and other strange ISA hardware, so we always want the
1087 * addresses to be allocated in the 0x000-0x0ff region
1088 * modulo 0x400.
1089 *
1090 * Why? Because some silly external IO cards only decode
1091 * the low 10 bits of the IO address. The 0x00-0xff region
1092 * is reserved for motherboard devices that decode all 16
1093 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1094 * but we want to try to avoid allocating at 0x2900-0x2bff
1095 * which might have be mirrored at 0x0100-0x03ff..
1096 */
Dominik Brodowski3b7a17f2010-01-01 17:40:50 +01001097resource_size_t pcibios_align_resource(void *data, const struct resource *res,
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001098 resource_size_t size, resource_size_t align)
1099{
1100 struct pci_dev *dev = data;
Dominik Brodowskib26b2d42010-01-01 17:40:49 +01001101 resource_size_t start = res->start;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001102
1103 if (res->flags & IORESOURCE_IO) {
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001104 if (skip_isa_ioresource_align(dev))
Dominik Brodowskib26b2d42010-01-01 17:40:49 +01001105 return start;
1106 if (start & 0x300)
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001107 start = (start + 0x3ff) & ~0x3ff;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001108 }
Dominik Brodowskib26b2d42010-01-01 17:40:49 +01001109
1110 return start;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001111}
1112EXPORT_SYMBOL(pcibios_align_resource);
1113
1114/*
1115 * Reparent resource children of pr that conflict with res
1116 * under res, and make res replace those children.
1117 */
Heiko Schocher0f6023d2009-09-24 02:45:14 +00001118static int reparent_resources(struct resource *parent,
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001119 struct resource *res)
1120{
1121 struct resource *p, **pp;
1122 struct resource **firstpp = NULL;
1123
1124 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1125 if (p->end < res->start)
1126 continue;
1127 if (res->end < p->start)
1128 break;
1129 if (p->start < res->start || p->end > res->end)
1130 return -1; /* not completely contained */
1131 if (firstpp == NULL)
1132 firstpp = pp;
1133 }
1134 if (firstpp == NULL)
1135 return -1; /* didn't find any conflicting entries? */
1136 res->parent = parent;
1137 res->child = *firstpp;
1138 res->sibling = *pp;
1139 *firstpp = res;
1140 *pp = NULL;
1141 for (p = res->child; p != NULL; p = p->sibling) {
1142 p->parent = res;
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +00001143 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1144 p->name,
1145 (unsigned long long)p->start,
1146 (unsigned long long)p->end, res->name);
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001147 }
1148 return 0;
1149}
1150
1151/*
1152 * Handle resources of PCI devices. If the world were perfect, we could
1153 * just allocate all the resource regions and do nothing more. It isn't.
1154 * On the other hand, we cannot just re-allocate all devices, as it would
1155 * require us to know lots of host bridge internals. So we attempt to
1156 * keep as much of the original configuration as possible, but tweak it
1157 * when it's found to be wrong.
1158 *
1159 * Known BIOS problems we have to work around:
1160 * - I/O or memory regions not configured
1161 * - regions configured, but not enabled in the command register
1162 * - bogus I/O addresses above 64K used
1163 * - expansion ROMs left enabled (this may sound harmless, but given
1164 * the fact the PCI specs explicitly allow address decoders to be
1165 * shared between expansion ROMs and other resource regions, it's
1166 * at least dangerous)
1167 *
1168 * Our solution:
1169 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1170 * This gives us fixed barriers on where we can allocate.
1171 * (2) Allocate resources for all enabled devices. If there is
1172 * a collision, just mark the resource as unallocated. Also
1173 * disable expansion ROMs during this step.
1174 * (3) Try to allocate resources for disabled devices. If the
1175 * resources were assigned correctly, everything goes well,
1176 * if they weren't, they won't disturb allocation of other
1177 * resources.
1178 * (4) Assign new addresses to resources which were either
1179 * not configured at all or misconfigured. If explicitly
1180 * requested by the user, configure expansion ROM address
1181 * as well.
1182 */
1183
Nathan Fontenote90a1312008-10-27 19:48:17 +00001184void pcibios_allocate_bus_resources(struct pci_bus *bus)
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001185{
Nathan Fontenote90a1312008-10-27 19:48:17 +00001186 struct pci_bus *b;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001187 int i;
1188 struct resource *res, *pr;
1189
Benjamin Herrenschmidtb5ae5f92008-10-27 19:48:44 +00001190 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1191 pci_domain_nr(bus), bus->number);
1192
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -07001193 pci_bus_for_each_resource(bus, res, i) {
1194 if (!res || !res->flags || res->start > res->end || res->parent)
Nathan Fontenote90a1312008-10-27 19:48:17 +00001195 continue;
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +00001196
1197 /* If the resource was left unset at this point, we clear it */
1198 if (res->flags & IORESOURCE_UNSET)
1199 goto clear_resource;
1200
Nathan Fontenote90a1312008-10-27 19:48:17 +00001201 if (bus->parent == NULL)
1202 pr = (res->flags & IORESOURCE_IO) ?
1203 &ioport_resource : &iomem_resource;
1204 else {
Nathan Fontenote90a1312008-10-27 19:48:17 +00001205 pr = pci_find_parent_resource(bus->self, res);
1206 if (pr == res) {
1207 /* this happens when the generic PCI
1208 * code (wrongly) decides that this
1209 * bridge is transparent -- paulus
1210 */
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001211 continue;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001212 }
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001213 }
Nathan Fontenote90a1312008-10-27 19:48:17 +00001214
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +00001215 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1216 "[0x%x], parent %p (%s)\n",
1217 bus->self ? pci_name(bus->self) : "PHB",
1218 bus->number, i,
1219 (unsigned long long)res->start,
1220 (unsigned long long)res->end,
1221 (unsigned int)res->flags,
1222 pr, (pr && pr->name) ? pr->name : "nil");
Nathan Fontenote90a1312008-10-27 19:48:17 +00001223
1224 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1225 if (request_resource(pr, res) == 0)
1226 continue;
1227 /*
1228 * Must be a conflict with an existing entry.
1229 * Move that entry (or entries) under the
1230 * bridge resource and try again.
1231 */
1232 if (reparent_resources(pr, res) == 0)
1233 continue;
1234 }
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +00001235 pr_warning("PCI: Cannot allocate resource region "
1236 "%d of PCI bridge %d, will remap\n", i, bus->number);
1237 clear_resource:
Gavin Shancf1a4cf2012-06-03 22:15:25 +00001238 /* The resource might be figured out when doing
1239 * reassignment based on the resources required
1240 * by the downstream PCI devices. Here we set
1241 * the size of the resource to be 0 in order to
1242 * save more space.
1243 */
1244 res->start = 0;
1245 res->end = -1;
Nathan Fontenote90a1312008-10-27 19:48:17 +00001246 res->flags = 0;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001247 }
Nathan Fontenote90a1312008-10-27 19:48:17 +00001248
1249 list_for_each_entry(b, &bus->children, node)
1250 pcibios_allocate_bus_resources(b);
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001251}
1252
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -08001253static inline void alloc_resource(struct pci_dev *dev, int idx)
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001254{
1255 struct resource *pr, *r = &dev->resource[idx];
1256
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +00001257 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1258 pci_name(dev), idx,
1259 (unsigned long long)r->start,
1260 (unsigned long long)r->end,
1261 (unsigned int)r->flags);
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001262
1263 pr = pci_find_parent_resource(dev, r);
1264 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1265 request_resource(pr, r) < 0) {
1266 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1267 " of device %s, will remap\n", idx, pci_name(dev));
1268 if (pr)
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +00001269 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1270 pr,
1271 (unsigned long long)pr->start,
1272 (unsigned long long)pr->end,
1273 (unsigned int)pr->flags);
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001274 /* We'll assign a new address later */
1275 r->flags |= IORESOURCE_UNSET;
1276 r->end -= r->start;
1277 r->start = 0;
1278 }
1279}
1280
1281static void __init pcibios_allocate_resources(int pass)
1282{
1283 struct pci_dev *dev = NULL;
1284 int idx, disabled;
1285 u16 command;
1286 struct resource *r;
1287
1288 for_each_pci_dev(dev) {
1289 pci_read_config_word(dev, PCI_COMMAND, &command);
Benjamin Herrenschmidtad892a62009-05-14 20:16:47 +00001290 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001291 r = &dev->resource[idx];
1292 if (r->parent) /* Already allocated */
1293 continue;
1294 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1295 continue; /* Not assigned at all */
Benjamin Herrenschmidtad892a62009-05-14 20:16:47 +00001296 /* We only allocate ROMs on pass 1 just in case they
1297 * have been screwed up by firmware
1298 */
1299 if (idx == PCI_ROM_RESOURCE )
1300 disabled = 1;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001301 if (r->flags & IORESOURCE_IO)
1302 disabled = !(command & PCI_COMMAND_IO);
1303 else
1304 disabled = !(command & PCI_COMMAND_MEMORY);
Paul Mackerras533b1922007-12-31 10:04:15 +11001305 if (pass == disabled)
1306 alloc_resource(dev, idx);
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001307 }
1308 if (pass)
1309 continue;
1310 r = &dev->resource[PCI_ROM_RESOURCE];
Benjamin Herrenschmidtad892a62009-05-14 20:16:47 +00001311 if (r->flags) {
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001312 /* Turn the ROM off, leave the resource region,
1313 * but keep it unregistered.
1314 */
1315 u32 reg;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001316 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
Benjamin Herrenschmidtad892a62009-05-14 20:16:47 +00001317 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1318 pr_debug("PCI: Switching off ROM of %s\n",
1319 pci_name(dev));
1320 r->flags &= ~IORESOURCE_ROM_ENABLE;
1321 pci_write_config_dword(dev, dev->rom_base_reg,
1322 reg & ~PCI_ROM_ADDRESS_ENABLE);
1323 }
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001324 }
1325 }
1326}
1327
Benjamin Herrenschmidtc1f34302008-11-11 17:45:52 +00001328static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1329{
1330 struct pci_controller *hose = pci_bus_to_host(bus);
1331 resource_size_t offset;
1332 struct resource *res, *pres;
1333 int i;
1334
1335 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1336
1337 /* Check for IO */
1338 if (!(hose->io_resource.flags & IORESOURCE_IO))
1339 goto no_io;
1340 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1341 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1342 BUG_ON(res == NULL);
1343 res->name = "Legacy IO";
1344 res->flags = IORESOURCE_IO;
1345 res->start = offset;
1346 res->end = (offset + 0xfff) & 0xfffffffful;
1347 pr_debug("Candidate legacy IO: %pR\n", res);
1348 if (request_resource(&hose->io_resource, res)) {
1349 printk(KERN_DEBUG
1350 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1351 pci_domain_nr(bus), bus->number, res);
1352 kfree(res);
1353 }
1354
1355 no_io:
1356 /* Check for memory */
Benjamin Herrenschmidtc1f34302008-11-11 17:45:52 +00001357 for (i = 0; i < 3; i++) {
1358 pres = &hose->mem_resources[i];
Benjamin Herrenschmidt3fd47f02013-05-06 13:40:40 +10001359 offset = hose->mem_offset[i];
Benjamin Herrenschmidtc1f34302008-11-11 17:45:52 +00001360 if (!(pres->flags & IORESOURCE_MEM))
1361 continue;
1362 pr_debug("hose mem res: %pR\n", pres);
1363 if ((pres->start - offset) <= 0xa0000 &&
1364 (pres->end - offset) >= 0xbffff)
1365 break;
1366 }
1367 if (i >= 3)
1368 return;
1369 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1370 BUG_ON(res == NULL);
1371 res->name = "Legacy VGA memory";
1372 res->flags = IORESOURCE_MEM;
1373 res->start = 0xa0000 + offset;
1374 res->end = 0xbffff + offset;
1375 pr_debug("Candidate VGA memory: %pR\n", res);
1376 if (request_resource(pres, res)) {
1377 printk(KERN_DEBUG
1378 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1379 pci_domain_nr(bus), bus->number, res);
1380 kfree(res);
1381 }
1382}
1383
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001384void __init pcibios_resource_survey(void)
1385{
Nathan Fontenote90a1312008-10-27 19:48:17 +00001386 struct pci_bus *b;
1387
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +00001388 /* Allocate and assign resources */
Nathan Fontenote90a1312008-10-27 19:48:17 +00001389 list_for_each_entry(b, &pci_root_buses, node)
1390 pcibios_allocate_bus_resources(b);
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +00001391 pcibios_allocate_resources(0);
1392 pcibios_allocate_resources(1);
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001393
Benjamin Herrenschmidtc1f34302008-11-11 17:45:52 +00001394 /* Before we start assigning unassigned resource, we try to reserve
1395 * the low IO area and the VGA memory area if they intersect the
1396 * bus available resources to avoid allocating things on top of them
1397 */
Rob Herring0e47ff12011-07-12 09:25:51 -05001398 if (!pci_has_flag(PCI_PROBE_ONLY)) {
Benjamin Herrenschmidtc1f34302008-11-11 17:45:52 +00001399 list_for_each_entry(b, &pci_root_buses, node)
1400 pcibios_reserve_legacy_regions(b);
1401 }
1402
1403 /* Now, if the platform didn't decide to blindly trust the firmware,
1404 * we proceed to assigning things that were left unassigned
1405 */
Rob Herring0e47ff12011-07-12 09:25:51 -05001406 if (!pci_has_flag(PCI_PROBE_ONLY)) {
Wolfram Sanga77acda2009-03-09 06:39:01 +00001407 pr_debug("PCI: Assigning unassigned resources...\n");
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001408 pci_assign_unassigned_resources();
1409 }
1410
1411 /* Call machine dependent fixup */
1412 if (ppc_md.pcibios_fixup)
1413 ppc_md.pcibios_fixup();
1414}
1415
Benjamin Herrenschmidtfd6852c2008-10-27 19:48:52 +00001416/* This is used by the PCI hotplug driver to allocate resource
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001417 * of newly plugged busses. We can try to consolidate with the
Benjamin Herrenschmidtfd6852c2008-10-27 19:48:52 +00001418 * rest of the code later, for now, keep it as-is as our main
1419 * resource allocation function doesn't deal with sub-trees yet.
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001420 */
Stephen Rothwellbaf75b02009-06-01 14:53:53 +00001421void pcibios_claim_one_bus(struct pci_bus *bus)
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001422{
1423 struct pci_dev *dev;
1424 struct pci_bus *child_bus;
1425
1426 list_for_each_entry(dev, &bus->devices, bus_list) {
1427 int i;
1428
1429 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1430 struct resource *r = &dev->resource[i];
1431
1432 if (r->parent || !r->start || !r->flags)
1433 continue;
Benjamin Herrenschmidtfd6852c2008-10-27 19:48:52 +00001434
1435 pr_debug("PCI: Claiming %s: "
1436 "Resource %d: %016llx..%016llx [%x]\n",
1437 pci_name(dev), i,
1438 (unsigned long long)r->start,
1439 (unsigned long long)r->end,
1440 (unsigned int)r->flags);
1441
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001442 pci_claim_resource(dev, i);
1443 }
1444 }
1445
1446 list_for_each_entry(child_bus, &bus->children, node)
1447 pcibios_claim_one_bus(child_bus);
1448}
Benjamin Herrenschmidtfd6852c2008-10-27 19:48:52 +00001449
1450
1451/* pcibios_finish_adding_to_bus
1452 *
1453 * This is to be called by the hotplug code after devices have been
1454 * added to a bus, this include calling it for a PHB that is just
1455 * being added
1456 */
1457void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1458{
1459 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1460 pci_domain_nr(bus), bus->number);
1461
1462 /* Allocate bus and devices resources */
1463 pcibios_allocate_bus_resources(bus);
1464 pcibios_claim_one_bus(bus);
1465
Thadeu Lima de Souza Cascardo6a040ce2012-12-28 09:13:19 +00001466 /* Fixup EEH */
1467 eeh_add_device_tree_late(bus);
1468
Benjamin Herrenschmidtfd6852c2008-10-27 19:48:52 +00001469 /* Add new devices to global lists. Register in proc, sysfs. */
1470 pci_bus_add_devices(bus);
1471
Thadeu Lima de Souza Cascardo6a040ce2012-12-28 09:13:19 +00001472 /* sysfs files should only be added after devices are added */
1473 eeh_add_sysfs_files(bus);
Benjamin Herrenschmidtfd6852c2008-10-27 19:48:52 +00001474}
1475EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1476
Benjamin Herrenschmidt549beb92007-12-20 14:54:57 +11001477int pcibios_enable_device(struct pci_dev *dev, int mask)
1478{
Benjamin Herrenschmidt549beb92007-12-20 14:54:57 +11001479 if (ppc_md.pcibios_enable_device_hook)
1480 if (ppc_md.pcibios_enable_device_hook(dev))
1481 return -EINVAL;
1482
Bjorn Helgaas7cfb5f92008-03-04 11:56:56 -07001483 return pci_enable_resources(dev, mask);
Benjamin Herrenschmidt549beb92007-12-20 14:54:57 +11001484}
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001485
Bjorn Helgaas38973ba2012-03-16 17:48:09 -06001486resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1487{
1488 return (unsigned long) hose->io_base_virt - _IO_BASE;
1489}
1490
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -08001491static void pcibios_setup_phb_resources(struct pci_controller *hose,
1492 struct list_head *resources)
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001493{
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001494 struct resource *res;
Benjamin Herrenschmidt3fd47f02013-05-06 13:40:40 +10001495 resource_size_t offset;
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001496 int i;
1497
1498 /* Hookup PHB IO resource */
Bjorn Helgaas45a709f2011-10-28 16:27:43 -06001499 res = &hose->io_resource;
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001500
1501 if (!res->flags) {
1502 printk(KERN_WARNING "PCI: I/O resource not set for host"
1503 " bridge %s (domain %d)\n",
1504 hose->dn->full_name, hose->global_number);
Benjamin Herrenschmidt3fd47f02013-05-06 13:40:40 +10001505 } else {
1506 offset = pcibios_io_space_offset(hose);
1507
1508 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n",
Benjamin Herrenschmidta0b8e762013-05-04 14:22:57 +00001509 (unsigned long long)res->start,
1510 (unsigned long long)res->end,
Benjamin Herrenschmidt3fd47f02013-05-06 13:40:40 +10001511 (unsigned long)res->flags,
1512 (unsigned long long)offset);
1513 pci_add_resource_offset(resources, res, offset);
Benjamin Herrenschmidta0b8e762013-05-04 14:22:57 +00001514 }
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001515
1516 /* Hookup PHB Memory resources */
1517 for (i = 0; i < 3; ++i) {
1518 res = &hose->mem_resources[i];
1519 if (!res->flags) {
Benjamin Herrenschmidtbee7dd92013-05-20 17:24:39 +00001520 if (i == 0)
1521 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1522 "host bridge %s (domain %d)\n",
1523 hose->dn->full_name, hose->global_number);
Benjamin Herrenschmidt3fd47f02013-05-06 13:40:40 +10001524 continue;
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001525 }
Benjamin Herrenschmidt3fd47f02013-05-06 13:40:40 +10001526 offset = hose->mem_offset[i];
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001527
Benjamin Herrenschmidt3fd47f02013-05-06 13:40:40 +10001528
1529 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i,
1530 (unsigned long long)res->start,
1531 (unsigned long long)res->end,
1532 (unsigned long)res->flags,
1533 (unsigned long long)offset);
1534
1535 pci_add_resource_offset(resources, res, offset);
1536 }
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001537}
Kumar Gala89c2dd62009-08-25 16:20:45 +00001538
1539/*
1540 * Null PCI config access functions, for the case when we can't
1541 * find a hose.
1542 */
1543#define NULL_PCI_OP(rw, size, type) \
1544static int \
1545null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1546{ \
1547 return PCIBIOS_DEVICE_NOT_FOUND; \
1548}
1549
1550static int
1551null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1552 int len, u32 *val)
1553{
1554 return PCIBIOS_DEVICE_NOT_FOUND;
1555}
1556
1557static int
1558null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1559 int len, u32 val)
1560{
1561 return PCIBIOS_DEVICE_NOT_FOUND;
1562}
1563
1564static struct pci_ops null_pci_ops =
1565{
1566 .read = null_read_config,
1567 .write = null_write_config,
1568};
1569
1570/*
1571 * These functions are used early on before PCI scanning is done
1572 * and all of the pci_dev and pci_bus structures have been created.
1573 */
1574static struct pci_bus *
1575fake_pci_bus(struct pci_controller *hose, int busnr)
1576{
1577 static struct pci_bus bus;
1578
1579 if (hose == 0) {
1580 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1581 }
1582 bus.number = busnr;
1583 bus.sysdata = hose;
1584 bus.ops = hose? hose->ops: &null_pci_ops;
1585 return &bus;
1586}
1587
1588#define EARLY_PCI_OP(rw, size, type) \
1589int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1590 int devfn, int offset, type value) \
1591{ \
1592 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1593 devfn, offset, value); \
1594}
1595
1596EARLY_PCI_OP(read, byte, u8 *)
1597EARLY_PCI_OP(read, word, u16 *)
1598EARLY_PCI_OP(read, dword, u32 *)
1599EARLY_PCI_OP(write, byte, u8)
1600EARLY_PCI_OP(write, word, u16)
1601EARLY_PCI_OP(write, dword, u32)
1602
1603extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1604int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1605 int cap)
1606{
1607 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1608}
Grant Likely0ed2c722009-08-28 08:58:16 +00001609
Benjamin Herrenschmidt98d9f302011-04-11 11:37:07 +10001610struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1611{
1612 struct pci_controller *hose = bus->sysdata;
1613
1614 return of_node_get(hose->dn);
1615}
1616
Grant Likely0ed2c722009-08-28 08:58:16 +00001617/**
1618 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1619 * @hose: Pointer to the PCI host controller instance structure
Grant Likely0ed2c722009-08-28 08:58:16 +00001620 */
Greg Kroah-Hartmancad5cef2012-12-21 14:04:10 -08001621void pcibios_scan_phb(struct pci_controller *hose)
Grant Likely0ed2c722009-08-28 08:58:16 +00001622{
Bjorn Helgaas45a709f2011-10-28 16:27:43 -06001623 LIST_HEAD(resources);
Grant Likely0ed2c722009-08-28 08:58:16 +00001624 struct pci_bus *bus;
1625 struct device_node *node = hose->dn;
1626 int mode;
1627
Grant Likely74a7f082012-06-15 11:50:25 -06001628 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
Grant Likely0ed2c722009-08-28 08:58:16 +00001629
Grant Likely0ed2c722009-08-28 08:58:16 +00001630 /* Get some IO space for the new PHB */
1631 pcibios_setup_phb_io_space(hose);
1632
1633 /* Wire up PHB bus resources */
Bjorn Helgaas45a709f2011-10-28 16:27:43 -06001634 pcibios_setup_phb_resources(hose, &resources);
1635
Yinghai Lube8e60d2012-05-17 18:51:12 -07001636 hose->busn.start = hose->first_busno;
1637 hose->busn.end = hose->last_busno;
1638 hose->busn.flags = IORESOURCE_BUS;
1639 pci_add_resource(&resources, &hose->busn);
1640
Bjorn Helgaas45a709f2011-10-28 16:27:43 -06001641 /* Create an empty bus for the toplevel */
1642 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1643 hose->ops, hose, &resources);
1644 if (bus == NULL) {
1645 pr_err("Failed to create bus for PCI domain %04x\n",
1646 hose->global_number);
1647 pci_free_resource_list(&resources);
1648 return;
1649 }
Bjorn Helgaas45a709f2011-10-28 16:27:43 -06001650 hose->bus = bus;
Grant Likely0ed2c722009-08-28 08:58:16 +00001651
1652 /* Get probe mode and perform scan */
1653 mode = PCI_PROBE_NORMAL;
1654 if (node && ppc_md.pci_probe_mode)
1655 mode = ppc_md.pci_probe_mode(bus);
1656 pr_debug(" probe mode: %d\n", mode);
Yinghai Lube8e60d2012-05-17 18:51:12 -07001657 if (mode == PCI_PROBE_DEVTREE)
Grant Likely0ed2c722009-08-28 08:58:16 +00001658 of_scan_bus(node, bus);
Grant Likely0ed2c722009-08-28 08:58:16 +00001659
Yinghai Lube8e60d2012-05-17 18:51:12 -07001660 if (mode == PCI_PROBE_NORMAL) {
1661 pci_bus_update_busn_res_end(bus, 255);
1662 hose->last_busno = pci_scan_child_bus(bus);
1663 pci_bus_update_busn_res_end(bus, hose->last_busno);
1664 }
Benjamin Herrenschmidt781fb7a2011-09-19 17:44:50 +00001665
Benjamin Herrenschmidt491b98c2011-11-06 18:55:57 +00001666 /* Platform gets a chance to do some global fixups before
1667 * we proceed to resource allocation
1668 */
1669 if (ppc_md.pcibios_fixup_phb)
1670 ppc_md.pcibios_fixup_phb(hose);
1671
Benjamin Herrenschmidt781fb7a2011-09-19 17:44:50 +00001672 /* Configure PCI Express settings */
Benjamin Herrenschmidtbb36c442011-09-26 14:22:39 +10001673 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
Benjamin Herrenschmidt781fb7a2011-09-19 17:44:50 +00001674 struct pci_bus *child;
1675 list_for_each_entry(child, &bus->children, node) {
1676 struct pci_dev *self = child->self;
1677 if (!self)
1678 continue;
1679 pcie_bus_configure_settings(child, self->pcie_mpss);
1680 }
1681 }
Grant Likely0ed2c722009-08-28 08:58:16 +00001682}
Kumar Galac0654882011-05-19 22:26:18 -05001683
1684static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1685{
1686 int i, class = dev->class >> 8;
Jason Jin05737c72011-10-28 16:08:00 +08001687 /* When configured as agent, programing interface = 1 */
1688 int prog_if = dev->class & 0xf;
Kumar Galac0654882011-05-19 22:26:18 -05001689
1690 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1691 class == PCI_CLASS_BRIDGE_OTHER) &&
1692 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
Jason Jin05737c72011-10-28 16:08:00 +08001693 (prog_if == 0) &&
Kumar Galac0654882011-05-19 22:26:18 -05001694 (dev->bus->parent == NULL)) {
1695 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1696 dev->resource[i].start = 0;
1697 dev->resource[i].end = 0;
1698 dev->resource[i].flags = 0;
1699 }
1700 }
1701}
1702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
Brian Kingc2e1d842013-04-08 03:05:10 +00001704
1705static void fixup_vga(struct pci_dev *pdev)
1706{
1707 u16 cmd;
1708
1709 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1710 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1711 vga_set_default_device(pdev);
1712
1713}
1714DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1715 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);