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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Ethernet driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * I copied the basic skeleton from the lance driver, because I did not
6 * know how to write the Linux driver, but I did know how the LANCE worked.
7 *
8 * This version of the driver is somewhat selectable for the different
9 * processor/board combinations. It works for the boards I know about
10 * now, and should be easily modified to include others. Some of the
11 * configuration information is contained in <asm/commproc.h> and the
12 * remainder is here.
13 *
14 * Buffer descriptors are kept in the CPM dual port RAM, and the frame
15 * buffers are in the host memory.
16 *
17 * Right now, I am very watseful with the buffers. I allocate memory
18 * pages and then divide them into 2K frame buffers. This way I know I
19 * have buffers large enough to hold one frame within one buffer descriptor.
20 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
21 * will be much more memory efficient and will easily handle lots of
22 * small packets.
23 *
24 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/string.h>
28#include <linux/ptrace.h>
29#include <linux/errno.h>
30#include <linux/ioport.h>
31#include <linux/slab.h>
32#include <linux/interrupt.h>
33#include <linux/pci.h>
34#include <linux/init.h>
35#include <linux/delay.h>
36#include <linux/netdevice.h>
37#include <linux/etherdevice.h>
38#include <linux/skbuff.h>
39#include <linux/spinlock.h>
40#include <linux/dma-mapping.h>
41#include <linux/bitops.h>
42
43#include <asm/8xx_immap.h>
44#include <asm/pgtable.h>
45#include <asm/mpc8xx.h>
46#include <asm/uaccess.h>
47#include <asm/commproc.h>
48
49/*
50 * Theory of Operation
51 *
52 * The MPC8xx CPM performs the Ethernet processing on SCC1. It can use
53 * an aribtrary number of buffers on byte boundaries, but must have at
54 * least two receive buffers to prevent constant overrun conditions.
55 *
56 * The buffer descriptors are allocated from the CPM dual port memory
57 * with the data buffers allocated from host memory, just like all other
58 * serial communication protocols. The host memory buffers are allocated
59 * from the free page pool, and then divided into smaller receive and
60 * transmit buffers. The size of the buffers should be a power of two,
61 * since that nicely divides the page. This creates a ring buffer
62 * structure similar to the LANCE and other controllers.
63 *
64 * Like the LANCE driver:
65 * The driver runs as two independent, single-threaded flows of control. One
66 * is the send-packet routine, which enforces single-threaded use by the
67 * cep->tx_busy flag. The other thread is the interrupt handler, which is
68 * single threaded by the hardware and other software.
69 *
70 * The send packet thread has partial control over the Tx ring and the
71 * 'cep->tx_busy' flag. It sets the tx_busy flag whenever it's queuing a Tx
72 * packet. If the next queue slot is empty, it clears the tx_busy flag when
73 * finished otherwise it sets the 'lp->tx_full' flag.
74 *
75 * The MBX has a control register external to the MPC8xx that has some
76 * control of the Ethernet interface. Information is in the manual for
77 * your board.
78 *
79 * The RPX boards have an external control/status register. Consult the
80 * programming documents for details unique to your board.
81 *
82 * For the TQM8xx(L) modules, there is no control register interface.
83 * All functions are directly controlled using I/O pins. See <asm/commproc.h>.
84 */
85
86/* The transmitter timeout
87 */
88#define TX_TIMEOUT (2*HZ)
89
90/* The number of Tx and Rx buffers. These are allocated from the page
91 * pool. The code may assume these are power of two, so it is best
92 * to keep them that size.
93 * We don't need to allocate pages for the transmitter. We just use
94 * the skbuffer directly.
95 */
96#ifdef CONFIG_ENET_BIG_BUFFERS
97#define CPM_ENET_RX_PAGES 32
98#define CPM_ENET_RX_FRSIZE 2048
99#define CPM_ENET_RX_FRPPG (PAGE_SIZE / CPM_ENET_RX_FRSIZE)
100#define RX_RING_SIZE (CPM_ENET_RX_FRPPG * CPM_ENET_RX_PAGES)
101#define TX_RING_SIZE 64 /* Must be power of two */
102#define TX_RING_MOD_MASK 63 /* for this to work */
103#else
104#define CPM_ENET_RX_PAGES 4
105#define CPM_ENET_RX_FRSIZE 2048
106#define CPM_ENET_RX_FRPPG (PAGE_SIZE / CPM_ENET_RX_FRSIZE)
107#define RX_RING_SIZE (CPM_ENET_RX_FRPPG * CPM_ENET_RX_PAGES)
108#define TX_RING_SIZE 8 /* Must be power of two */
109#define TX_RING_MOD_MASK 7 /* for this to work */
110#endif
111
112/* The CPM stores dest/src/type, data, and checksum for receive packets.
113 */
114#define PKT_MAXBUF_SIZE 1518
115#define PKT_MINBUF_SIZE 64
116#define PKT_MAXBLR_SIZE 1520
117
118/* The CPM buffer descriptors track the ring buffers. The rx_bd_base and
119 * tx_bd_base always point to the base of the buffer descriptors. The
120 * cur_rx and cur_tx point to the currently available buffer.
121 * The dirty_tx tracks the current buffer that is being sent by the
122 * controller. The cur_tx and dirty_tx are equal under both completely
123 * empty and completely full conditions. The empty/ready indicator in
124 * the buffer descriptor determines the actual condition.
125 */
126struct scc_enet_private {
127 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
128 struct sk_buff* tx_skbuff[TX_RING_SIZE];
129 ushort skb_cur;
130 ushort skb_dirty;
131
132 /* CPM dual port RAM relative addresses.
133 */
134 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
135 cbd_t *tx_bd_base;
136 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
137 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
138 scc_t *sccp;
139
140 /* Virtual addresses for the receive buffers because we can't
141 * do a __va() on them anymore.
142 */
143 unsigned char *rx_vaddr[RX_RING_SIZE];
144 struct net_device_stats stats;
145 uint tx_full;
146 spinlock_t lock;
147};
148
149static int scc_enet_open(struct net_device *dev);
150static int scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
151static int scc_enet_rx(struct net_device *dev);
Al Viro39e3eb72006-10-09 12:48:42 +0100152static void scc_enet_interrupt(void *dev_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153static int scc_enet_close(struct net_device *dev);
154static struct net_device_stats *scc_enet_get_stats(struct net_device *dev);
155static void set_multicast_list(struct net_device *dev);
156
157/* Get this from various configuration locations (depends on board).
158*/
159/*static ushort my_enet_addr[] = { 0x0800, 0x3e26, 0x1559 };*/
160
161/* Typically, 860(T) boards use SCC1 for Ethernet, and other 8xx boards
162 * use SCC2. Some even may use SCC3.
163 * This is easily extended if necessary.
164 */
165#if defined(CONFIG_SCC3_ENET)
166#define CPM_CR_ENET CPM_CR_CH_SCC3
167#define PROFF_ENET PROFF_SCC3
168#define SCC_ENET 2 /* Index, not number! */
169#define CPMVEC_ENET CPMVEC_SCC3
170#elif defined(CONFIG_SCC2_ENET)
171#define CPM_CR_ENET CPM_CR_CH_SCC2
172#define PROFF_ENET PROFF_SCC2
173#define SCC_ENET 1 /* Index, not number! */
174#define CPMVEC_ENET CPMVEC_SCC2
175#elif defined(CONFIG_SCC1_ENET)
176#define CPM_CR_ENET CPM_CR_CH_SCC1
177#define PROFF_ENET PROFF_SCC1
178#define SCC_ENET 0 /* Index, not number! */
179#define CPMVEC_ENET CPMVEC_SCC1
180#else
181#error CONFIG_SCCx_ENET not defined
182#endif
183
184static int
185scc_enet_open(struct net_device *dev)
186{
187
188 /* I should reset the ring buffers here, but I don't yet know
189 * a simple way to do that.
190 */
191
192 netif_start_queue(dev);
193 return 0; /* Always succeed */
194}
195
196static int
197scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
198{
199 struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv;
200 volatile cbd_t *bdp;
201
202 /* Fill in a Tx ring entry */
203 bdp = cep->cur_tx;
204
205#ifndef final_version
206 if (bdp->cbd_sc & BD_ENET_TX_READY) {
207 /* Ooops. All transmit buffers are full. Bail out.
208 * This should not happen, since cep->tx_busy should be set.
209 */
210 printk("%s: tx queue full!.\n", dev->name);
211 return 1;
212 }
213#endif
214
215 /* Clear all of the status flags.
216 */
217 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
218
219 /* If the frame is short, tell CPM to pad it.
220 */
221 if (skb->len <= ETH_ZLEN)
222 bdp->cbd_sc |= BD_ENET_TX_PAD;
223 else
224 bdp->cbd_sc &= ~BD_ENET_TX_PAD;
225
226 /* Set buffer length and buffer pointer.
227 */
228 bdp->cbd_datlen = skb->len;
229 bdp->cbd_bufaddr = __pa(skb->data);
230
231 /* Save skb pointer.
232 */
233 cep->tx_skbuff[cep->skb_cur] = skb;
234
235 cep->stats.tx_bytes += skb->len;
236 cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK;
237
238 /* Push the data cache so the CPM does not get stale memory
239 * data.
240 */
241 flush_dcache_range((unsigned long)(skb->data),
242 (unsigned long)(skb->data + skb->len));
243
244 spin_lock_irq(&cep->lock);
245
246 /* Send it on its way. Tell CPM its ready, interrupt when done,
247 * its the last BD of the frame, and to put the CRC on the end.
248 */
249 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR | BD_ENET_TX_LAST | BD_ENET_TX_TC);
250
251 dev->trans_start = jiffies;
252
253 /* If this was the last BD in the ring, start at the beginning again.
254 */
255 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
256 bdp = cep->tx_bd_base;
257 else
258 bdp++;
259
260 if (bdp->cbd_sc & BD_ENET_TX_READY) {
261 netif_stop_queue(dev);
262 cep->tx_full = 1;
263 }
264
265 cep->cur_tx = (cbd_t *)bdp;
266
267 spin_unlock_irq(&cep->lock);
268
269 return 0;
270}
271
272static void
273scc_enet_timeout(struct net_device *dev)
274{
275 struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv;
276
277 printk("%s: transmit timed out.\n", dev->name);
278 cep->stats.tx_errors++;
279#ifndef final_version
280 {
281 int i;
282 cbd_t *bdp;
283 printk(" Ring data dump: cur_tx %p%s cur_rx %p.\n",
284 cep->cur_tx, cep->tx_full ? " (full)" : "",
285 cep->cur_rx);
286 bdp = cep->tx_bd_base;
287 for (i = 0 ; i < TX_RING_SIZE; i++, bdp++)
288 printk("%04x %04x %08x\n",
289 bdp->cbd_sc,
290 bdp->cbd_datlen,
291 bdp->cbd_bufaddr);
292 bdp = cep->rx_bd_base;
293 for (i = 0 ; i < RX_RING_SIZE; i++, bdp++)
294 printk("%04x %04x %08x\n",
295 bdp->cbd_sc,
296 bdp->cbd_datlen,
297 bdp->cbd_bufaddr);
298 }
299#endif
300 if (!cep->tx_full)
301 netif_wake_queue(dev);
302}
303
304/* The interrupt handler.
305 * This is called from the CPM handler, not the MPC core interrupt.
306 */
307static void
Al Viro39e3eb72006-10-09 12:48:42 +0100308scc_enet_interrupt(void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700309{
310 struct net_device *dev = dev_id;
311 volatile struct scc_enet_private *cep;
312 volatile cbd_t *bdp;
313 ushort int_events;
314 int must_restart;
315
316 cep = (struct scc_enet_private *)dev->priv;
317
318 /* Get the interrupt events that caused us to be here.
319 */
320 int_events = cep->sccp->scc_scce;
321 cep->sccp->scc_scce = int_events;
322 must_restart = 0;
323
324 /* Handle receive event in its own function.
325 */
326 if (int_events & SCCE_ENET_RXF)
327 scc_enet_rx(dev_id);
328
329 /* Check for a transmit error. The manual is a little unclear
330 * about this, so the debug code until I get it figured out. It
331 * appears that if TXE is set, then TXB is not set. However,
332 * if carrier sense is lost during frame transmission, the TXE
333 * bit is set, "and continues the buffer transmission normally."
334 * I don't know if "normally" implies TXB is set when the buffer
335 * descriptor is closed.....trial and error :-).
336 */
337
338 /* Transmit OK, or non-fatal error. Update the buffer descriptors.
339 */
340 if (int_events & (SCCE_ENET_TXE | SCCE_ENET_TXB)) {
341 spin_lock(&cep->lock);
342 bdp = cep->dirty_tx;
343 while ((bdp->cbd_sc&BD_ENET_TX_READY)==0) {
344 if ((bdp==cep->cur_tx) && (cep->tx_full == 0))
345 break;
346
347 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
348 cep->stats.tx_heartbeat_errors++;
349 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
350 cep->stats.tx_window_errors++;
351 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
352 cep->stats.tx_aborted_errors++;
353 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
354 cep->stats.tx_fifo_errors++;
355 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
356 cep->stats.tx_carrier_errors++;
357
358
359 /* No heartbeat or Lost carrier are not really bad errors.
360 * The others require a restart transmit command.
361 */
362 if (bdp->cbd_sc &
363 (BD_ENET_TX_LC | BD_ENET_TX_RL | BD_ENET_TX_UN)) {
364 must_restart = 1;
365 cep->stats.tx_errors++;
366 }
367
368 cep->stats.tx_packets++;
369
370 /* Deferred means some collisions occurred during transmit,
371 * but we eventually sent the packet OK.
372 */
373 if (bdp->cbd_sc & BD_ENET_TX_DEF)
374 cep->stats.collisions++;
375
376 /* Free the sk buffer associated with this last transmit.
377 */
378 dev_kfree_skb_irq(cep->tx_skbuff[cep->skb_dirty]);
379 cep->skb_dirty = (cep->skb_dirty + 1) & TX_RING_MOD_MASK;
380
381 /* Update pointer to next buffer descriptor to be transmitted.
382 */
383 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
384 bdp = cep->tx_bd_base;
385 else
386 bdp++;
387
388 /* I don't know if we can be held off from processing these
389 * interrupts for more than one frame time. I really hope
390 * not. In such a case, we would now want to check the
391 * currently available BD (cur_tx) and determine if any
392 * buffers between the dirty_tx and cur_tx have also been
393 * sent. We would want to process anything in between that
394 * does not have BD_ENET_TX_READY set.
395 */
396
397 /* Since we have freed up a buffer, the ring is no longer
398 * full.
399 */
400 if (cep->tx_full) {
401 cep->tx_full = 0;
402 if (netif_queue_stopped(dev))
403 netif_wake_queue(dev);
404 }
405
406 cep->dirty_tx = (cbd_t *)bdp;
407 }
408
409 if (must_restart) {
410 volatile cpm8xx_t *cp;
411
412 /* Some transmit errors cause the transmitter to shut
413 * down. We now issue a restart transmit. Since the
414 * errors close the BD and update the pointers, the restart
415 * _should_ pick up without having to reset any of our
416 * pointers either.
417 */
418 cp = cpmp;
419 cp->cp_cpcr =
420 mk_cr_cmd(CPM_CR_ENET, CPM_CR_RESTART_TX) | CPM_CR_FLG;
421 while (cp->cp_cpcr & CPM_CR_FLG);
422 }
423 spin_unlock(&cep->lock);
424 }
425
426 /* Check for receive busy, i.e. packets coming but no place to
427 * put them. This "can't happen" because the receive interrupt
428 * is tossing previous frames.
429 */
430 if (int_events & SCCE_ENET_BSY) {
431 cep->stats.rx_dropped++;
432 printk("CPM ENET: BSY can't happen.\n");
433 }
434
435 return;
436}
437
438/* During a receive, the cur_rx points to the current incoming buffer.
439 * When we update through the ring, if the next incoming buffer has
440 * not been given to the system, we just set the empty indicator,
441 * effectively tossing the packet.
442 */
443static int
444scc_enet_rx(struct net_device *dev)
445{
446 struct scc_enet_private *cep;
447 volatile cbd_t *bdp;
448 struct sk_buff *skb;
449 ushort pkt_len;
450
451 cep = (struct scc_enet_private *)dev->priv;
452
453 /* First, grab all of the stats for the incoming packet.
454 * These get messed up if we get called due to a busy condition.
455 */
456 bdp = cep->cur_rx;
457
458for (;;) {
459 if (bdp->cbd_sc & BD_ENET_RX_EMPTY)
460 break;
461
462#ifndef final_version
463 /* Since we have allocated space to hold a complete frame, both
464 * the first and last indicators should be set.
465 */
466 if ((bdp->cbd_sc & (BD_ENET_RX_FIRST | BD_ENET_RX_LAST)) !=
467 (BD_ENET_RX_FIRST | BD_ENET_RX_LAST))
468 printk("CPM ENET: rcv is not first+last\n");
469#endif
470
471 /* Frame too long or too short.
472 */
473 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH))
474 cep->stats.rx_length_errors++;
475 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
476 cep->stats.rx_frame_errors++;
477 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
478 cep->stats.rx_crc_errors++;
479 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
480 cep->stats.rx_crc_errors++;
481
482 /* Report late collisions as a frame error.
483 * On this error, the BD is closed, but we don't know what we
484 * have in the buffer. So, just drop this frame on the floor.
485 */
486 if (bdp->cbd_sc & BD_ENET_RX_CL) {
487 cep->stats.rx_frame_errors++;
488 }
489 else {
490
491 /* Process the incoming frame.
492 */
493 cep->stats.rx_packets++;
494 pkt_len = bdp->cbd_datlen;
495 cep->stats.rx_bytes += pkt_len;
496
497 /* This does 16 byte alignment, much more than we need.
498 * The packet length includes FCS, but we don't want to
499 * include that when passing upstream as it messes up
500 * bridging applications.
501 */
502 skb = dev_alloc_skb(pkt_len-4);
503
504 if (skb == NULL) {
505 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
506 cep->stats.rx_dropped++;
507 }
508 else {
509 skb->dev = dev;
510 skb_put(skb,pkt_len-4); /* Make room */
511 eth_copy_and_sum(skb,
512 cep->rx_vaddr[bdp - cep->rx_bd_base],
513 pkt_len-4, 0);
514 skb->protocol=eth_type_trans(skb,dev);
515 netif_rx(skb);
516 }
517 }
518
519 /* Clear the status flags for this buffer.
520 */
521 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
522
523 /* Mark the buffer empty.
524 */
525 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
526
527 /* Update BD pointer to next entry.
528 */
529 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
530 bdp = cep->rx_bd_base;
531 else
532 bdp++;
533
534 }
535 cep->cur_rx = (cbd_t *)bdp;
536
537 return 0;
538}
539
540static int
541scc_enet_close(struct net_device *dev)
542{
543 /* Don't know what to do yet.
544 */
545 netif_stop_queue(dev);
546
547 return 0;
548}
549
550static struct net_device_stats *scc_enet_get_stats(struct net_device *dev)
551{
552 struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv;
553
554 return &cep->stats;
555}
556
557/* Set or clear the multicast filter for this adaptor.
558 * Skeleton taken from sunlance driver.
559 * The CPM Ethernet implementation allows Multicast as well as individual
560 * MAC address filtering. Some of the drivers check to make sure it is
561 * a group multicast address, and discard those that are not. I guess I
562 * will do the same for now, but just remove the test if you want
563 * individual filtering as well (do the upper net layers want or support
564 * this kind of feature?).
565 */
566
567static void set_multicast_list(struct net_device *dev)
568{
569 struct scc_enet_private *cep;
570 struct dev_mc_list *dmi;
571 u_char *mcptr, *tdptr;
572 volatile scc_enet_t *ep;
573 int i, j;
574 cep = (struct scc_enet_private *)dev->priv;
575
576 /* Get pointer to SCC area in parameter RAM.
577 */
578 ep = (scc_enet_t *)dev->base_addr;
579
580 if (dev->flags&IFF_PROMISC) {
581
582 /* Log any net taps. */
583 printk("%s: Promiscuous mode enabled.\n", dev->name);
584 cep->sccp->scc_psmr |= SCC_PSMR_PRO;
585 } else {
586
587 cep->sccp->scc_psmr &= ~SCC_PSMR_PRO;
588
589 if (dev->flags & IFF_ALLMULTI) {
590 /* Catch all multicast addresses, so set the
591 * filter to all 1's.
592 */
593 ep->sen_gaddr1 = 0xffff;
594 ep->sen_gaddr2 = 0xffff;
595 ep->sen_gaddr3 = 0xffff;
596 ep->sen_gaddr4 = 0xffff;
597 }
598 else {
599 /* Clear filter and add the addresses in the list.
600 */
601 ep->sen_gaddr1 = 0;
602 ep->sen_gaddr2 = 0;
603 ep->sen_gaddr3 = 0;
604 ep->sen_gaddr4 = 0;
605
606 dmi = dev->mc_list;
607
608 for (i=0; i<dev->mc_count; i++) {
609
610 /* Only support group multicast for now.
611 */
612 if (!(dmi->dmi_addr[0] & 1))
613 continue;
614
615 /* The address in dmi_addr is LSB first,
616 * and taddr is MSB first. We have to
617 * copy bytes MSB first from dmi_addr.
618 */
619 mcptr = (u_char *)dmi->dmi_addr + 5;
620 tdptr = (u_char *)&ep->sen_taddrh;
621 for (j=0; j<6; j++)
622 *tdptr++ = *mcptr--;
623
624 /* Ask CPM to run CRC and set bit in
625 * filter mask.
626 */
627 cpmp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_SET_GADDR) | CPM_CR_FLG;
628 /* this delay is necessary here -- Cort */
629 udelay(10);
630 while (cpmp->cp_cpcr & CPM_CR_FLG);
631 }
632 }
633 }
634}
635
636/* Initialize the CPM Ethernet on SCC. If EPPC-Bug loaded us, or performed
637 * some other network I/O, a whole bunch of this has already been set up.
638 * It is no big deal if we do it again, we just have to disable the
639 * transmit and receive to make sure we don't catch the CPM with some
640 * inconsistent control information.
641 */
642static int __init scc_enet_init(void)
643{
644 struct net_device *dev;
645 struct scc_enet_private *cep;
646 int i, j, k, err;
647 uint dp_offset;
648 unsigned char *eap, *ba;
649 dma_addr_t mem_addr;
650 bd_t *bd;
651 volatile cbd_t *bdp;
652 volatile cpm8xx_t *cp;
653 volatile scc_t *sccp;
654 volatile scc_enet_t *ep;
655 volatile immap_t *immap;
656
657 cp = cpmp; /* Get pointer to Communication Processor */
658
659 immap = (immap_t *)(mfspr(SPRN_IMMR) & 0xFFFF0000); /* and to internal registers */
660
661 bd = (bd_t *)__res;
662
663 dev = alloc_etherdev(sizeof(*cep));
664 if (!dev)
665 return -ENOMEM;
666
667 cep = dev->priv;
668 spin_lock_init(&cep->lock);
669
670 /* Get pointer to SCC area in parameter RAM.
671 */
672 ep = (scc_enet_t *)(&cp->cp_dparam[PROFF_ENET]);
673
674 /* And another to the SCC register area.
675 */
676 sccp = (volatile scc_t *)(&cp->cp_scc[SCC_ENET]);
677 cep->sccp = (scc_t *)sccp; /* Keep the pointer handy */
678
679 /* Disable receive and transmit in case EPPC-Bug started it.
680 */
681 sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
682
683 /* Cookbook style from the MPC860 manual.....
684 * Not all of this is necessary if EPPC-Bug has initialized
685 * the network.
686 * So far we are lucky, all board configurations use the same
687 * pins, or at least the same I/O Port for these functions.....
688 * It can't last though......
689 */
690
691#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
692 /* Configure port A pins for Txd and Rxd.
693 */
694 immap->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
695 immap->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
696 immap->im_ioport.iop_paodr &= ~PA_ENET_TXD;
697#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
698 /* Configure port B pins for Txd and Rxd.
699 */
700 immap->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
701 immap->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
702 immap->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
703#else
704#error Exactly ONE pair of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
705#endif
706
707#if defined(PC_ENET_LBK)
708 /* Configure port C pins to disable External Loopback
709 */
710 immap->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
711 immap->im_ioport.iop_pcdir |= PC_ENET_LBK;
712 immap->im_ioport.iop_pcso &= ~PC_ENET_LBK;
713 immap->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
714#endif /* PC_ENET_LBK */
715
Andrei Konovalove6b62392005-07-05 18:54:43 -0700716#ifdef PE_ENET_TCLK
717 /* Configure port E for TCLK and RCLK.
718 */
719 cp->cp_pepar |= (PE_ENET_TCLK | PE_ENET_RCLK);
720 cp->cp_pedir &= ~(PE_ENET_TCLK | PE_ENET_RCLK);
721 cp->cp_peso &= ~(PE_ENET_TCLK | PE_ENET_RCLK);
722#else
723 /* Configure port A for TCLK and RCLK.
724 */
725 immap->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
726 immap->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
727#endif
728
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729 /* Configure port C pins to enable CLSN and RENA.
730 */
731 immap->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
732 immap->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
733 immap->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
734
Linus Torvalds1da177e2005-04-16 15:20:36 -0700735 /* Configure Serial Interface clock routing.
736 * First, clear all SCC bits to zero, then set the ones we want.
737 */
738 cp->cp_sicr &= ~SICR_ENET_MASK;
739 cp->cp_sicr |= SICR_ENET_CLKRT;
740
741 /* Manual says set SDDR, but I can't find anything with that
742 * name. I think it is a misprint, and should be SDCR. This
743 * has already been set by the communication processor initialization.
744 */
745
746 /* Allocate space for the buffer descriptors in the DP ram.
747 * These are relative offsets in the DP ram address space.
748 * Initialize base addresses for the buffer descriptors.
749 */
750 dp_offset = cpm_dpalloc(sizeof(cbd_t) * RX_RING_SIZE, 8);
751 ep->sen_genscc.scc_rbase = dp_offset;
752 cep->rx_bd_base = cpm_dpram_addr(dp_offset);
753
754 dp_offset = cpm_dpalloc(sizeof(cbd_t) * TX_RING_SIZE, 8);
755 ep->sen_genscc.scc_tbase = dp_offset;
756 cep->tx_bd_base = cpm_dpram_addr(dp_offset);
757
758 cep->dirty_tx = cep->cur_tx = cep->tx_bd_base;
759 cep->cur_rx = cep->rx_bd_base;
760
761 /* Issue init Rx BD command for SCC.
762 * Manual says to perform an Init Rx parameters here. We have
763 * to perform both Rx and Tx because the SCC may have been
764 * already running.
765 * In addition, we have to do it later because we don't yet have
766 * all of the BD control/status set properly.
767 cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_INIT_RX) | CPM_CR_FLG;
768 while (cp->cp_cpcr & CPM_CR_FLG);
769 */
770
771 /* Initialize function code registers for big-endian.
772 */
773 ep->sen_genscc.scc_rfcr = SCC_EB;
774 ep->sen_genscc.scc_tfcr = SCC_EB;
775
776 /* Set maximum bytes per receive buffer.
777 * This appears to be an Ethernet frame size, not the buffer
778 * fragment size. It must be a multiple of four.
779 */
780 ep->sen_genscc.scc_mrblr = PKT_MAXBLR_SIZE;
781
782 /* Set CRC preset and mask.
783 */
784 ep->sen_cpres = 0xffffffff;
785 ep->sen_cmask = 0xdebb20e3;
786
787 ep->sen_crcec = 0; /* CRC Error counter */
788 ep->sen_alec = 0; /* alignment error counter */
789 ep->sen_disfc = 0; /* discard frame counter */
790
791 ep->sen_pads = 0x8888; /* Tx short frame pad character */
792 ep->sen_retlim = 15; /* Retry limit threshold */
793
794 ep->sen_maxflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
795 ep->sen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register */
796
797 ep->sen_maxd1 = PKT_MAXBLR_SIZE; /* maximum DMA1 length */
798 ep->sen_maxd2 = PKT_MAXBLR_SIZE; /* maximum DMA2 length */
799
800 /* Clear hash tables.
801 */
802 ep->sen_gaddr1 = 0;
803 ep->sen_gaddr2 = 0;
804 ep->sen_gaddr3 = 0;
805 ep->sen_gaddr4 = 0;
806 ep->sen_iaddr1 = 0;
807 ep->sen_iaddr2 = 0;
808 ep->sen_iaddr3 = 0;
809 ep->sen_iaddr4 = 0;
810
811 /* Set Ethernet station address.
812 */
813 eap = (unsigned char *)&(ep->sen_paddrh);
814 for (i=5; i>=0; i--)
815 *eap++ = dev->dev_addr[i] = bd->bi_enetaddr[i];
816
817 ep->sen_pper = 0; /* 'cause the book says so */
818 ep->sen_taddrl = 0; /* temp address (LSB) */
819 ep->sen_taddrm = 0;
820 ep->sen_taddrh = 0; /* temp address (MSB) */
821
822 /* Now allocate the host memory pages and initialize the
823 * buffer descriptors.
824 */
825 bdp = cep->tx_bd_base;
826 for (i=0; i<TX_RING_SIZE; i++) {
827
828 /* Initialize the BD for every fragment in the page.
829 */
830 bdp->cbd_sc = 0;
831 bdp->cbd_bufaddr = 0;
832 bdp++;
833 }
834
835 /* Set the last buffer to wrap.
836 */
837 bdp--;
838 bdp->cbd_sc |= BD_SC_WRAP;
839
840 bdp = cep->rx_bd_base;
841 k = 0;
842 for (i=0; i<CPM_ENET_RX_PAGES; i++) {
843
844 /* Allocate a page.
845 */
846 ba = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE,
847 &mem_addr, GFP_KERNEL);
848 /* BUG: no check for failure */
849
850 /* Initialize the BD for every fragment in the page.
851 */
852 for (j=0; j<CPM_ENET_RX_FRPPG; j++) {
853 bdp->cbd_sc = BD_ENET_RX_EMPTY | BD_ENET_RX_INTR;
854 bdp->cbd_bufaddr = mem_addr;
855 cep->rx_vaddr[k++] = ba;
856 mem_addr += CPM_ENET_RX_FRSIZE;
857 ba += CPM_ENET_RX_FRSIZE;
858 bdp++;
859 }
860 }
861
862 /* Set the last buffer to wrap.
863 */
864 bdp--;
865 bdp->cbd_sc |= BD_SC_WRAP;
866
867 /* Let's re-initialize the channel now. We have to do it later
868 * than the manual describes because we have just now finished
869 * the BD initialization.
870 */
871 cp->cp_cpcr = mk_cr_cmd(CPM_CR_ENET, CPM_CR_INIT_TRX) | CPM_CR_FLG;
872 while (cp->cp_cpcr & CPM_CR_FLG);
873
874 cep->skb_cur = cep->skb_dirty = 0;
875
876 sccp->scc_scce = 0xffff; /* Clear any pending events */
877
878 /* Enable interrupts for transmit error, complete frame
879 * received, and any transmit buffer we have also set the
880 * interrupt flag.
881 */
882 sccp->scc_sccm = (SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB);
883
884 /* Install our interrupt handler.
885 */
886 cpm_install_handler(CPMVEC_ENET, scc_enet_interrupt, dev);
887
888 /* Set GSMR_H to enable all normal operating modes.
889 * Set GSMR_L to enable Ethernet to MC68160.
890 */
891 sccp->scc_gsmrh = 0;
892 sccp->scc_gsmrl = (SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 | SCC_GSMRL_MODE_ENET);
893
894 /* Set sync/delimiters.
895 */
896 sccp->scc_dsr = 0xd555;
897
898 /* Set processing mode. Use Ethernet CRC, catch broadcast, and
899 * start frame search 22 bit times after RENA.
900 */
901 sccp->scc_psmr = (SCC_PSMR_ENCRC | SCC_PSMR_NIB22);
902
903 /* It is now OK to enable the Ethernet transmitter.
904 * Unfortunately, there are board implementation differences here.
905 */
Andrei Konovalove6b62392005-07-05 18:54:43 -0700906#if (!defined (PB_ENET_TENA) && defined (PC_ENET_TENA) && !defined (PE_ENET_TENA))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700907 immap->im_ioport.iop_pcpar |= PC_ENET_TENA;
908 immap->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
Andrei Konovalove6b62392005-07-05 18:54:43 -0700909#elif ( defined (PB_ENET_TENA) && !defined (PC_ENET_TENA) && !defined (PE_ENET_TENA))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700910 cp->cp_pbpar |= PB_ENET_TENA;
911 cp->cp_pbdir |= PB_ENET_TENA;
Andrei Konovalove6b62392005-07-05 18:54:43 -0700912#elif ( !defined (PB_ENET_TENA) && !defined (PC_ENET_TENA) && defined (PE_ENET_TENA))
913 cp->cp_pepar |= PE_ENET_TENA;
914 cp->cp_pedir &= ~PE_ENET_TENA;
915 cp->cp_peso |= PE_ENET_TENA;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700916#else
Andrei Konovalove6b62392005-07-05 18:54:43 -0700917#error Configuration Error: define exactly ONE of PB_ENET_TENA, PC_ENET_TENA, PE_ENET_TENA
Linus Torvalds1da177e2005-04-16 15:20:36 -0700918#endif
919
920#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
921 /* And while we are here, set the configuration to enable ethernet.
922 */
923 *((volatile uint *)RPX_CSR_ADDR) &= ~BCSR0_ETHLPBK;
924 *((volatile uint *)RPX_CSR_ADDR) |=
925 (BCSR0_ETHEN | BCSR0_COLTESTDIS | BCSR0_FULLDPLXDIS);
926#endif
927
928#ifdef CONFIG_BSEIP
929 /* BSE uses port B and C for PHY control.
930 */
931 cp->cp_pbpar &= ~(PB_BSE_POWERUP | PB_BSE_FDXDIS);
932 cp->cp_pbdir |= (PB_BSE_POWERUP | PB_BSE_FDXDIS);
933 cp->cp_pbdat |= (PB_BSE_POWERUP | PB_BSE_FDXDIS);
934
935 immap->im_ioport.iop_pcpar &= ~PC_BSE_LOOPBACK;
936 immap->im_ioport.iop_pcdir |= PC_BSE_LOOPBACK;
937 immap->im_ioport.iop_pcso &= ~PC_BSE_LOOPBACK;
938 immap->im_ioport.iop_pcdat &= ~PC_BSE_LOOPBACK;
939#endif
940
941#ifdef CONFIG_FADS
942 cp->cp_pbpar |= PB_ENET_TENA;
943 cp->cp_pbdir |= PB_ENET_TENA;
944
945 /* Enable the EEST PHY.
946 */
947 *((volatile uint *)BCSR1) &= ~BCSR1_ETHEN;
948#endif
949
Andrei Konovalove6b62392005-07-05 18:54:43 -0700950#ifdef CONFIG_MPC885ADS
951
952 /* Deassert PHY reset and enable the PHY.
953 */
954 {
955 volatile uint __iomem *bcsr = ioremap(BCSR_ADDR, BCSR_SIZE);
956 uint tmp;
957
958 tmp = in_be32(bcsr + 1 /* BCSR1 */);
959 tmp |= BCSR1_ETHEN;
960 out_be32(bcsr + 1, tmp);
961 tmp = in_be32(bcsr + 4 /* BCSR4 */);
962 tmp |= BCSR4_ETH10_RST;
963 out_be32(bcsr + 4, tmp);
964 iounmap(bcsr);
965 }
966
967 /* On MPC885ADS SCC ethernet PHY defaults to the full duplex mode
968 * upon reset. SCC is set to half duplex by default. So this
969 * inconsistency should be better fixed by the software.
970 */
971#endif
972
Linus Torvalds1da177e2005-04-16 15:20:36 -0700973 dev->base_addr = (unsigned long)ep;
974#if 0
975 dev->name = "CPM_ENET";
976#endif
977
978 /* The CPM Ethernet specific entries in the device structure. */
979 dev->open = scc_enet_open;
980 dev->hard_start_xmit = scc_enet_start_xmit;
981 dev->tx_timeout = scc_enet_timeout;
982 dev->watchdog_timeo = TX_TIMEOUT;
983 dev->stop = scc_enet_close;
984 dev->get_stats = scc_enet_get_stats;
985 dev->set_multicast_list = set_multicast_list;
986
987 err = register_netdev(dev);
988 if (err) {
989 free_netdev(dev);
990 return err;
991 }
992
993 /* And last, enable the transmit and receive processing.
994 */
995 sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
996
997 printk("%s: CPM ENET Version 0.2 on SCC%d, ", dev->name, SCC_ENET+1);
998 for (i=0; i<5; i++)
999 printk("%02x:", dev->dev_addr[i]);
1000 printk("%02x\n", dev->dev_addr[5]);
1001
1002 return 0;
1003}
1004
1005module_init(scc_enet_init);
Andrei Konovalove6b62392005-07-05 18:54:43 -07001006