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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * Copyright (C) 2001 Ralf Baechle
Ralf Baechle70342282013-01-22 12:59:30 +01006 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
7 * Author: Maciej W. Rozycki <macro@mips.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * This file define the irq handler for MIPS CPU interrupts.
10 *
Ralf Baechle70342282013-01-22 12:59:30 +010011 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17/*
18 * Almost all MIPS CPUs define 8 interrupt sources. They are typically
19 * level triggered (i.e., cannot be cleared from CPU; must be cleared from
20 * device). The first two are software interrupts which we don't really
21 * use or support. The last one is usually the CPU timer interrupt if
22 * counter register is present or, for CPUs with an external FPU, by
23 * convention it's the FPU exception interrupt.
24 *
25 * Don't even think about using this on SMP. You have been warned.
26 *
27 * This file exports one global function:
Atsushi Nemoto97dcb822007-01-08 02:14:29 +090028 * void mips_cpu_irq_init(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070029 */
30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/kernel.h>
David Howellsca4d3e672010-10-07 14:08:54 +010033#include <linux/irq.h>
Gabor Juhos0916b462013-01-31 12:20:43 +000034#include <linux/irqdomain.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
36#include <asm/irq_cpu.h>
37#include <asm/mipsregs.h>
Ralf Baechled03d0a52005-08-17 13:44:26 +000038#include <asm/mipsmtregs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
Thomas Gleixnera93951c2011-03-23 21:09:02 +000040static inline void unmask_mips_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070041{
Thomas Gleixnera93951c2011-03-23 21:09:02 +000042 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
Ralf Baechle569f75b2005-07-13 18:20:33 +000043 irq_enable_hazard();
Linus Torvalds1da177e2005-04-16 15:20:36 -070044}
45
Thomas Gleixnera93951c2011-03-23 21:09:02 +000046static inline void mask_mips_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070047{
Thomas Gleixnera93951c2011-03-23 21:09:02 +000048 clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
Ralf Baechle569f75b2005-07-13 18:20:33 +000049 irq_disable_hazard();
Linus Torvalds1da177e2005-04-16 15:20:36 -070050}
51
Ralf Baechle94dee172006-07-02 14:41:42 +010052static struct irq_chip mips_cpu_irq_controller = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +090053 .name = "MIPS",
Thomas Gleixnera93951c2011-03-23 21:09:02 +000054 .irq_ack = mask_mips_irq,
55 .irq_mask = mask_mips_irq,
56 .irq_mask_ack = mask_mips_irq,
57 .irq_unmask = unmask_mips_irq,
58 .irq_eoi = unmask_mips_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -070059};
60
Ralf Baechled03d0a52005-08-17 13:44:26 +000061/*
62 * Basically the same as above but taking care of all the MT stuff
63 */
64
Thomas Gleixnera93951c2011-03-23 21:09:02 +000065static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
Ralf Baechled03d0a52005-08-17 13:44:26 +000066{
67 unsigned int vpflags = dvpe();
68
Thomas Gleixnera93951c2011-03-23 21:09:02 +000069 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
Ralf Baechled03d0a52005-08-17 13:44:26 +000070 evpe(vpflags);
Thomas Gleixnera93951c2011-03-23 21:09:02 +000071 unmask_mips_irq(d);
Ralf Baechled03d0a52005-08-17 13:44:26 +000072 return 0;
73}
74
Ralf Baechled03d0a52005-08-17 13:44:26 +000075/*
76 * While we ack the interrupt interrupts are disabled and thus we don't need
77 * to deal with concurrency issues. Same for mips_cpu_irq_end.
78 */
Thomas Gleixnera93951c2011-03-23 21:09:02 +000079static void mips_mt_cpu_irq_ack(struct irq_data *d)
Ralf Baechled03d0a52005-08-17 13:44:26 +000080{
81 unsigned int vpflags = dvpe();
Thomas Gleixnera93951c2011-03-23 21:09:02 +000082 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
Ralf Baechled03d0a52005-08-17 13:44:26 +000083 evpe(vpflags);
Thomas Gleixnera93951c2011-03-23 21:09:02 +000084 mask_mips_irq(d);
Ralf Baechled03d0a52005-08-17 13:44:26 +000085}
86
Ralf Baechle94dee172006-07-02 14:41:42 +010087static struct irq_chip mips_mt_cpu_irq_controller = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +090088 .name = "MIPS",
Thomas Gleixnera93951c2011-03-23 21:09:02 +000089 .irq_startup = mips_mt_cpu_irq_startup,
90 .irq_ack = mips_mt_cpu_irq_ack,
91 .irq_mask = mask_mips_irq,
92 .irq_mask_ack = mips_mt_cpu_irq_ack,
93 .irq_unmask = unmask_mips_irq,
94 .irq_eoi = unmask_mips_irq,
Ralf Baechled03d0a52005-08-17 13:44:26 +000095};
Linus Torvalds1da177e2005-04-16 15:20:36 -070096
Atsushi Nemoto97dcb822007-01-08 02:14:29 +090097void __init mips_cpu_irq_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070098{
Atsushi Nemoto97dcb822007-01-08 02:14:29 +090099 int irq_base = MIPS_CPU_IRQ_BASE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100 int i;
101
Maciej W. Rozycki925ddb02005-02-03 23:06:29 +0000102 /* Mask interrupts. */
103 clear_c0_status(ST0_IM);
104 clear_c0_cause(CAUSEF_IP);
105
Kevin Cernekee273f2d72010-10-16 14:22:33 -0700106 /* Software interrupts are used for MT/CMT IPI */
107 for (i = irq_base; i < irq_base + 2; i++)
108 irq_set_chip_and_handler(i, cpu_has_mipsmt ?
109 &mips_mt_cpu_irq_controller :
110 &mips_cpu_irq_controller,
111 handle_percpu_irq);
Ralf Baechled03d0a52005-08-17 13:44:26 +0000112
Atsushi Nemoto1603b5a2006-11-02 02:08:36 +0900113 for (i = irq_base + 2; i < irq_base + 8; i++)
Thomas Gleixnere4ec7982011-03-27 15:19:28 +0200114 irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
Ralf Baechle30e748a2007-11-15 19:37:15 +0000115 handle_percpu_irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116}
Gabor Juhos0916b462013-01-31 12:20:43 +0000117
118#ifdef CONFIG_IRQ_DOMAIN
119static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
120 irq_hw_number_t hw)
121{
122 static struct irq_chip *chip;
123
124 if (hw < 2 && cpu_has_mipsmt) {
125 /* Software interrupts are used for MT/CMT IPI */
126 chip = &mips_mt_cpu_irq_controller;
127 } else {
128 chip = &mips_cpu_irq_controller;
129 }
130
131 irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
132
133 return 0;
134}
135
136static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
137 .map = mips_cpu_intc_map,
138 .xlate = irq_domain_xlate_onecell,
139};
140
141int __init mips_cpu_intc_init(struct device_node *of_node,
142 struct device_node *parent)
143{
144 struct irq_domain *domain;
145
146 /* Mask interrupts. */
147 clear_c0_status(ST0_IM);
148 clear_c0_cause(CAUSEF_IP);
149
150 domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
151 &mips_cpu_intc_irq_domain_ops, NULL);
152 if (!domain)
Ralf Baechlef7777dc2013-09-18 16:05:26 +0200153 panic("Failed to add irqdomain for MIPS CPU");
Gabor Juhos0916b462013-01-31 12:20:43 +0000154
155 return 0;
156}
157#endif /* CONFIG_IRQ_DOMAIN */