Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2001 MontaVista Software Inc. |
| 3 | * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net |
| 4 | * |
| 5 | * Copyright (C) 2001 Ralf Baechle |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 6 | * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. |
| 7 | * Author: Maciej W. Rozycki <macro@mips.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * |
| 9 | * This file define the irq handler for MIPS CPU interrupts. |
| 10 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify it |
| 12 | * under the terms of the GNU General Public License as published by the |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | * Free Software Foundation; either version 2 of the License, or (at your |
| 14 | * option) any later version. |
| 15 | */ |
| 16 | |
| 17 | /* |
| 18 | * Almost all MIPS CPUs define 8 interrupt sources. They are typically |
| 19 | * level triggered (i.e., cannot be cleared from CPU; must be cleared from |
| 20 | * device). The first two are software interrupts which we don't really |
| 21 | * use or support. The last one is usually the CPU timer interrupt if |
| 22 | * counter register is present or, for CPUs with an external FPU, by |
| 23 | * convention it's the FPU exception interrupt. |
| 24 | * |
| 25 | * Don't even think about using this on SMP. You have been warned. |
| 26 | * |
| 27 | * This file exports one global function: |
Atsushi Nemoto | 97dcb82 | 2007-01-08 02:14:29 +0900 | [diff] [blame] | 28 | * void mips_cpu_irq_init(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | */ |
| 30 | #include <linux/init.h> |
| 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/kernel.h> |
David Howells | ca4d3e67 | 2010-10-07 14:08:54 +0100 | [diff] [blame] | 33 | #include <linux/irq.h> |
Gabor Juhos | 0916b46 | 2013-01-31 12:20:43 +0000 | [diff] [blame] | 34 | #include <linux/irqdomain.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | |
| 36 | #include <asm/irq_cpu.h> |
| 37 | #include <asm/mipsregs.h> |
Ralf Baechle | d03d0a5 | 2005-08-17 13:44:26 +0000 | [diff] [blame] | 38 | #include <asm/mipsmtregs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | |
Thomas Gleixner | a93951c | 2011-03-23 21:09:02 +0000 | [diff] [blame] | 40 | static inline void unmask_mips_irq(struct irq_data *d) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | { |
Thomas Gleixner | a93951c | 2011-03-23 21:09:02 +0000 | [diff] [blame] | 42 | set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); |
Ralf Baechle | 569f75b | 2005-07-13 18:20:33 +0000 | [diff] [blame] | 43 | irq_enable_hazard(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | } |
| 45 | |
Thomas Gleixner | a93951c | 2011-03-23 21:09:02 +0000 | [diff] [blame] | 46 | static inline void mask_mips_irq(struct irq_data *d) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | { |
Thomas Gleixner | a93951c | 2011-03-23 21:09:02 +0000 | [diff] [blame] | 48 | clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); |
Ralf Baechle | 569f75b | 2005-07-13 18:20:33 +0000 | [diff] [blame] | 49 | irq_disable_hazard(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 50 | } |
| 51 | |
Ralf Baechle | 94dee17 | 2006-07-02 14:41:42 +0100 | [diff] [blame] | 52 | static struct irq_chip mips_cpu_irq_controller = { |
Atsushi Nemoto | 70d21cd | 2007-01-15 00:07:25 +0900 | [diff] [blame] | 53 | .name = "MIPS", |
Thomas Gleixner | a93951c | 2011-03-23 21:09:02 +0000 | [diff] [blame] | 54 | .irq_ack = mask_mips_irq, |
| 55 | .irq_mask = mask_mips_irq, |
| 56 | .irq_mask_ack = mask_mips_irq, |
| 57 | .irq_unmask = unmask_mips_irq, |
| 58 | .irq_eoi = unmask_mips_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 59 | }; |
| 60 | |
Ralf Baechle | d03d0a5 | 2005-08-17 13:44:26 +0000 | [diff] [blame] | 61 | /* |
| 62 | * Basically the same as above but taking care of all the MT stuff |
| 63 | */ |
| 64 | |
Thomas Gleixner | a93951c | 2011-03-23 21:09:02 +0000 | [diff] [blame] | 65 | static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) |
Ralf Baechle | d03d0a5 | 2005-08-17 13:44:26 +0000 | [diff] [blame] | 66 | { |
| 67 | unsigned int vpflags = dvpe(); |
| 68 | |
Thomas Gleixner | a93951c | 2011-03-23 21:09:02 +0000 | [diff] [blame] | 69 | clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); |
Ralf Baechle | d03d0a5 | 2005-08-17 13:44:26 +0000 | [diff] [blame] | 70 | evpe(vpflags); |
Thomas Gleixner | a93951c | 2011-03-23 21:09:02 +0000 | [diff] [blame] | 71 | unmask_mips_irq(d); |
Ralf Baechle | d03d0a5 | 2005-08-17 13:44:26 +0000 | [diff] [blame] | 72 | return 0; |
| 73 | } |
| 74 | |
Ralf Baechle | d03d0a5 | 2005-08-17 13:44:26 +0000 | [diff] [blame] | 75 | /* |
| 76 | * While we ack the interrupt interrupts are disabled and thus we don't need |
| 77 | * to deal with concurrency issues. Same for mips_cpu_irq_end. |
| 78 | */ |
Thomas Gleixner | a93951c | 2011-03-23 21:09:02 +0000 | [diff] [blame] | 79 | static void mips_mt_cpu_irq_ack(struct irq_data *d) |
Ralf Baechle | d03d0a5 | 2005-08-17 13:44:26 +0000 | [diff] [blame] | 80 | { |
| 81 | unsigned int vpflags = dvpe(); |
Thomas Gleixner | a93951c | 2011-03-23 21:09:02 +0000 | [diff] [blame] | 82 | clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); |
Ralf Baechle | d03d0a5 | 2005-08-17 13:44:26 +0000 | [diff] [blame] | 83 | evpe(vpflags); |
Thomas Gleixner | a93951c | 2011-03-23 21:09:02 +0000 | [diff] [blame] | 84 | mask_mips_irq(d); |
Ralf Baechle | d03d0a5 | 2005-08-17 13:44:26 +0000 | [diff] [blame] | 85 | } |
| 86 | |
Ralf Baechle | 94dee17 | 2006-07-02 14:41:42 +0100 | [diff] [blame] | 87 | static struct irq_chip mips_mt_cpu_irq_controller = { |
Atsushi Nemoto | 70d21cd | 2007-01-15 00:07:25 +0900 | [diff] [blame] | 88 | .name = "MIPS", |
Thomas Gleixner | a93951c | 2011-03-23 21:09:02 +0000 | [diff] [blame] | 89 | .irq_startup = mips_mt_cpu_irq_startup, |
| 90 | .irq_ack = mips_mt_cpu_irq_ack, |
| 91 | .irq_mask = mask_mips_irq, |
| 92 | .irq_mask_ack = mips_mt_cpu_irq_ack, |
| 93 | .irq_unmask = unmask_mips_irq, |
| 94 | .irq_eoi = unmask_mips_irq, |
Ralf Baechle | d03d0a5 | 2005-08-17 13:44:26 +0000 | [diff] [blame] | 95 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 96 | |
Atsushi Nemoto | 97dcb82 | 2007-01-08 02:14:29 +0900 | [diff] [blame] | 97 | void __init mips_cpu_irq_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | { |
Atsushi Nemoto | 97dcb82 | 2007-01-08 02:14:29 +0900 | [diff] [blame] | 99 | int irq_base = MIPS_CPU_IRQ_BASE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | int i; |
| 101 | |
Maciej W. Rozycki | 925ddb0 | 2005-02-03 23:06:29 +0000 | [diff] [blame] | 102 | /* Mask interrupts. */ |
| 103 | clear_c0_status(ST0_IM); |
| 104 | clear_c0_cause(CAUSEF_IP); |
| 105 | |
Kevin Cernekee | 273f2d7 | 2010-10-16 14:22:33 -0700 | [diff] [blame] | 106 | /* Software interrupts are used for MT/CMT IPI */ |
| 107 | for (i = irq_base; i < irq_base + 2; i++) |
| 108 | irq_set_chip_and_handler(i, cpu_has_mipsmt ? |
| 109 | &mips_mt_cpu_irq_controller : |
| 110 | &mips_cpu_irq_controller, |
| 111 | handle_percpu_irq); |
Ralf Baechle | d03d0a5 | 2005-08-17 13:44:26 +0000 | [diff] [blame] | 112 | |
Atsushi Nemoto | 1603b5a | 2006-11-02 02:08:36 +0900 | [diff] [blame] | 113 | for (i = irq_base + 2; i < irq_base + 8; i++) |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 114 | irq_set_chip_and_handler(i, &mips_cpu_irq_controller, |
Ralf Baechle | 30e748a | 2007-11-15 19:37:15 +0000 | [diff] [blame] | 115 | handle_percpu_irq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | } |
Gabor Juhos | 0916b46 | 2013-01-31 12:20:43 +0000 | [diff] [blame] | 117 | |
| 118 | #ifdef CONFIG_IRQ_DOMAIN |
| 119 | static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq, |
| 120 | irq_hw_number_t hw) |
| 121 | { |
| 122 | static struct irq_chip *chip; |
| 123 | |
| 124 | if (hw < 2 && cpu_has_mipsmt) { |
| 125 | /* Software interrupts are used for MT/CMT IPI */ |
| 126 | chip = &mips_mt_cpu_irq_controller; |
| 127 | } else { |
| 128 | chip = &mips_cpu_irq_controller; |
| 129 | } |
| 130 | |
| 131 | irq_set_chip_and_handler(irq, chip, handle_percpu_irq); |
| 132 | |
| 133 | return 0; |
| 134 | } |
| 135 | |
| 136 | static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = { |
| 137 | .map = mips_cpu_intc_map, |
| 138 | .xlate = irq_domain_xlate_onecell, |
| 139 | }; |
| 140 | |
| 141 | int __init mips_cpu_intc_init(struct device_node *of_node, |
| 142 | struct device_node *parent) |
| 143 | { |
| 144 | struct irq_domain *domain; |
| 145 | |
| 146 | /* Mask interrupts. */ |
| 147 | clear_c0_status(ST0_IM); |
| 148 | clear_c0_cause(CAUSEF_IP); |
| 149 | |
| 150 | domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, |
| 151 | &mips_cpu_intc_irq_domain_ops, NULL); |
| 152 | if (!domain) |
Ralf Baechle | f7777dc | 2013-09-18 16:05:26 +0200 | [diff] [blame] | 153 | panic("Failed to add irqdomain for MIPS CPU"); |
Gabor Juhos | 0916b46 | 2013-01-31 12:20:43 +0000 | [diff] [blame] | 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | #endif /* CONFIG_IRQ_DOMAIN */ |