Lars-Peter Clausen | 588858c | 2014-02-17 14:10:00 +0000 | [diff] [blame] | 1 | Xilinx XADC device driver |
| 2 | |
| 3 | This binding document describes the bindings for both of them since the |
| 4 | bindings are very similar. The Xilinx XADC is a ADC that can be found in the |
| 5 | series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. |
| 6 | Currently two different frontends for the DRP interface exist. One that is only |
| 7 | available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The |
| 8 | other one is available on all series 7 platforms and is a softmacro with a AXI |
| 9 | interface. This binding document describes the bindings for both of them since |
| 10 | the bindings are very similar. |
| 11 | |
| 12 | Required properties: |
| 13 | - compatible: Should be one of |
| 14 | * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device |
| 15 | configuration interface to interface to the XADC hardmacro. |
| 16 | * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to |
| 17 | interface to the XADC hardmacro. |
| 18 | - reg: Address and length of the register set for the device |
| 19 | - interrupts: Interrupt for the XADC control interface. |
| 20 | - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock, |
| 21 | when using the AXI-XADC pcore this must be the clock that provides the |
| 22 | clock to the AXI bus interface of the core. |
| 23 | |
| 24 | Optional properties: |
| 25 | - interrupt-parent: phandle to the parent interrupt controller |
| 26 | - xlnx,external-mux: |
| 27 | * "none": No external multiplexer is used, this is the default |
| 28 | if the property is omitted. |
| 29 | * "single": External multiplexer mode is used with one |
| 30 | multiplexer. |
| 31 | * "dual": External multiplexer mode is used with two |
| 32 | multiplexers for simultaneous sampling. |
| 33 | - xlnx,external-mux-channel: Configures which pair of pins is used to |
| 34 | sample data in external mux mode. |
| 35 | Valid values for single external multiplexer mode are: |
| 36 | 0: VP/VN |
| 37 | 1: VAUXP[0]/VAUXN[0] |
| 38 | 2: VAUXP[1]/VAUXN[1] |
| 39 | ... |
| 40 | 16: VAUXP[15]/VAUXN[15] |
| 41 | Valid values for dual external multiplexer mode are: |
| 42 | 1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8] |
| 43 | 2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9] |
| 44 | ... |
| 45 | 8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15] |
| 46 | |
| 47 | This property needs to be present if the device is configured for |
| 48 | external multiplexer mode (either single or dual). If the device is |
| 49 | not using external multiplexer mode the property is ignored. |
| 50 | - xnlx,channels: List of external channels that are connected to the ADC |
| 51 | Required properties: |
| 52 | * #address-cells: Should be 1. |
| 53 | * #size-cells: Should be 0. |
| 54 | |
| 55 | The child nodes of this node represent the external channels which are |
| 56 | connected to the ADC. If the property is no present no external |
| 57 | channels will be assumed to be connected. |
| 58 | |
| 59 | Each child node represents one channel and has the following |
| 60 | properties: |
| 61 | Required properties: |
| 62 | * reg: Pair of pins the the channel is connected to. |
| 63 | 0: VP/VN |
| 64 | 1: VAUXP[0]/VAUXN[0] |
| 65 | 2: VAUXP[1]/VAUXN[1] |
| 66 | ... |
| 67 | 16: VAUXP[15]/VAUXN[15] |
| 68 | Note each channel number should only be used at most |
| 69 | once. |
| 70 | Optional properties: |
| 71 | * xlnx,bipolar: If set the channel is used in bipolar |
| 72 | mode. |
| 73 | |
| 74 | |
| 75 | Examples: |
| 76 | xadc@f8007100 { |
| 77 | compatible = "xlnx,zynq-xadc-1.00.a"; |
| 78 | reg = <0xf8007100 0x20>; |
| 79 | interrupts = <0 7 4>; |
| 80 | interrupt-parent = <&gic>; |
| 81 | clocks = <&pcap_clk>; |
| 82 | |
| 83 | xlnx,channels { |
| 84 | #address-cells = <1>; |
| 85 | #size-cells = <0>; |
| 86 | channel@0 { |
| 87 | reg = <0>; |
| 88 | }; |
| 89 | channel@1 { |
| 90 | reg = <1>; |
| 91 | }; |
| 92 | channel@8 { |
| 93 | reg = <8>; |
| 94 | }; |
| 95 | }; |
| 96 | }; |
| 97 | |
| 98 | xadc@43200000 { |
| 99 | compatible = "xlnx,axi-xadc-1.00.a"; |
| 100 | reg = <0x43200000 0x1000>; |
| 101 | interrupts = <0 53 4>; |
| 102 | interrupt-parent = <&gic>; |
| 103 | clocks = <&fpga1_clk>; |
| 104 | |
| 105 | xlnx,channels { |
| 106 | #address-cells = <1>; |
| 107 | #size-cells = <0>; |
| 108 | channel@0 { |
| 109 | reg = <0>; |
| 110 | xlnx,bipolar; |
| 111 | }; |
| 112 | }; |
| 113 | }; |