blob: c7714185f83103219de72565f34a3dadbb6e198d [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Intel AGPGART routines.
3 */
4
Linus Torvalds1da177e2005-04-16 15:20:36 -07005#include <linux/module.h>
6#include <linux/pci.h>
7#include <linux/init.h>
Ahmed S. Darwish1eaf1222007-02-06 18:08:28 +02008#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07009#include <linux/pagemap.h>
10#include <linux/agp_backend.h>
11#include "agp.h"
12
Carlos Martíne914a362008-01-24 10:34:09 +100013#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
14#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
Eric Anholt65c25aa2006-09-06 11:57:18 -040015#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
16#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
Zhenyu Wang9119f852008-01-23 15:49:26 +100017#define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
18#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
Eric Anholt65c25aa2006-09-06 11:57:18 -040019#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
20#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
21#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
22#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
Wang Zhenyu4598af32007-04-09 08:51:36 +080023#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
24#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
Zhenyu Wangdde47872007-07-26 09:18:09 +080025#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
Wang Zhenyuc8eebfd2007-05-31 11:34:06 +080026#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
Zhenyu Wangdde47872007-07-26 09:18:09 +080027#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
Wang Zhenyudf80b142007-05-31 11:51:12 +080028#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
Wang Zhenyu874808c62007-06-06 11:16:25 +080029#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
30#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
31#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
32#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
33#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
34#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
Zhenyu Wang99d32bd2008-07-30 12:26:50 -070035#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
36#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
Zhenyu Wang25ce77a2008-06-19 14:17:58 +100037#define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
38#define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
39#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
40#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
41#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
42#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
Zhenyu Wanga50ccc62008-11-17 14:39:00 +080043#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
44#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
Eric Anholt65c25aa2006-09-06 11:57:18 -040045
Dave Airlief011ae72008-01-25 11:23:04 +100046/* cover 915 and 945 variants */
47#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
48 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
49 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
50 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
51 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
52 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
53
Eric Anholt65c25aa2006-09-06 11:57:18 -040054#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
Dave Airlief011ae72008-01-25 11:23:04 +100055 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
56 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
57 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
58 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
Eric Anholt82e14a62008-10-14 11:28:58 -070059 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
Eric Anholt65c25aa2006-09-06 11:57:18 -040060
Wang Zhenyu874808c62007-06-06 11:16:25 +080061#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
62 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
63 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
Eric Anholt65c25aa2006-09-06 11:57:18 -040064
Zhenyu Wang25ce77a2008-06-19 14:17:58 +100065#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
66 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
Eric Anholt82e14a62008-10-14 11:28:58 -070067 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
Zhenyu Wanga50ccc62008-11-17 14:39:00 +080068 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
69 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB)
Zhenyu Wang25ce77a2008-06-19 14:17:58 +100070
Thomas Hellstroma030ce42007-01-23 10:33:43 +010071extern int agp_memory_reserved;
72
73
Linus Torvalds1da177e2005-04-16 15:20:36 -070074/* Intel 815 register */
75#define INTEL_815_APCONT 0x51
76#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
77
78/* Intel i820 registers */
79#define INTEL_I820_RDCR 0x51
80#define INTEL_I820_ERRSTS 0xc8
81
82/* Intel i840 registers */
83#define INTEL_I840_MCHCFG 0x50
84#define INTEL_I840_ERRSTS 0xc8
85
86/* Intel i850 registers */
87#define INTEL_I850_MCHCFG 0x50
88#define INTEL_I850_ERRSTS 0xc8
89
90/* intel 915G registers */
91#define I915_GMADDR 0x18
92#define I915_MMADDR 0x10
93#define I915_PTEADDR 0x1C
94#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
95#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
Zhenyu Wang25ce77a2008-06-19 14:17:58 +100096#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
97#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
98#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
99#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
100#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
101#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
102
Dave Airlie6c00a612007-10-29 18:06:10 +1000103#define I915_IFPADDR 0x60
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104
Eric Anholt65c25aa2006-09-06 11:57:18 -0400105/* Intel 965G registers */
106#define I965_MSAC 0x62
Dave Airlie6c00a612007-10-29 18:06:10 +1000107#define I965_IFPADDR 0x70
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108
109/* Intel 7505 registers */
110#define INTEL_I7505_APSIZE 0x74
111#define INTEL_I7505_NCAPID 0x60
112#define INTEL_I7505_NISTAT 0x6c
113#define INTEL_I7505_ATTBASE 0x78
114#define INTEL_I7505_ERRSTS 0x42
115#define INTEL_I7505_AGPCTRL 0x70
116#define INTEL_I7505_MCHCFG 0x50
117
Dave Jonese5524f32007-02-22 18:41:28 -0500118static const struct aper_size_info_fixed intel_i810_sizes[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119{
120 {64, 16384, 4},
121 /* The 32M mode still requires a 64k gatt */
122 {32, 8192, 4}
123};
124
125#define AGP_DCACHE_MEMORY 1
126#define AGP_PHYS_MEMORY 2
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100127#define INTEL_AGP_CACHED_MEMORY 3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128
129static struct gatt_mask intel_i810_masks[] =
130{
131 {.mask = I810_PTE_VALID, .type = 0},
132 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100133 {.mask = I810_PTE_VALID, .type = 0},
134 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
135 .type = INTEL_AGP_CACHED_MEMORY}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136};
137
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800138static struct _intel_private {
139 struct pci_dev *pcidev; /* device one */
140 u8 __iomem *registers;
141 u32 __iomem *gtt; /* I915G */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142 int num_dcache_entries;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800143 /* gtt_entries is the number of gtt entries that are already mapped
144 * to stolen memory. Stolen memory is larger than the memory mapped
145 * through gtt_entries, as it includes some reserved space for the BIOS
146 * popup and for the GTT.
147 */
148 int gtt_entries; /* i830+ */
Dave Airlie2162e6a2007-11-21 16:36:31 +1000149 union {
150 void __iomem *i9xx_flush_page;
151 void *i8xx_flush_page;
152 };
153 struct page *i8xx_page;
Dave Airlie6c00a612007-10-29 18:06:10 +1000154 struct resource ifp_resource;
Dave Airlie4d64dd92008-01-23 15:34:29 +1000155 int resource_valid;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800156} intel_private;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157
158static int intel_i810_fetch_size(void)
159{
160 u32 smram_miscc;
161 struct aper_size_info_fixed *values;
162
163 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
164 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
165
166 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700167 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 return 0;
169 }
170 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
171 agp_bridge->previous_size =
172 agp_bridge->current_size = (void *) (values + 1);
173 agp_bridge->aperture_size_idx = 1;
174 return values[1].size;
175 } else {
176 agp_bridge->previous_size =
177 agp_bridge->current_size = (void *) (values);
178 agp_bridge->aperture_size_idx = 0;
179 return values[0].size;
180 }
181
182 return 0;
183}
184
185static int intel_i810_configure(void)
186{
187 struct aper_size_info_fixed *current_size;
188 u32 temp;
189 int i;
190
191 current_size = A_SIZE_FIX(agp_bridge->current_size);
192
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800193 if (!intel_private.registers) {
194 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
Dave Jonese4ac5e42007-02-04 17:37:42 -0500195 temp &= 0xfff80000;
196
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800197 intel_private.registers = ioremap(temp, 128 * 4096);
198 if (!intel_private.registers) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700199 dev_err(&intel_private.pcidev->dev,
200 "can't remap memory\n");
Dave Jonese4ac5e42007-02-04 17:37:42 -0500201 return -ENOMEM;
202 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 }
204
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800205 if ((readl(intel_private.registers+I810_DRAM_CTL)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
207 /* This will need to be dynamically assigned */
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700208 dev_info(&intel_private.pcidev->dev,
209 "detected 4MB dedicated video ram\n");
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800210 intel_private.num_dcache_entries = 1024;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800212 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800214 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
215 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216
217 if (agp_bridge->driver->needs_scratch_page) {
218 for (i = 0; i < current_size->num_entries; i++) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800219 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 }
Keith Packard44d49442008-10-14 17:18:45 -0700221 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222 }
223 global_cache_flush();
224 return 0;
225}
226
227static void intel_i810_cleanup(void)
228{
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800229 writel(0, intel_private.registers+I810_PGETBL_CTL);
230 readl(intel_private.registers); /* PCI Posting. */
231 iounmap(intel_private.registers);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232}
233
234static void intel_i810_tlbflush(struct agp_memory *mem)
235{
236 return;
237}
238
239static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
240{
241 return;
242}
243
244/* Exists to support ARGB cursors */
245static void *i8xx_alloc_pages(void)
246{
Dave Airlief011ae72008-01-25 11:23:04 +1000247 struct page *page;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248
Linus Torvalds66c669b2006-11-22 14:55:29 -0800249 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250 if (page == NULL)
251 return NULL;
252
Arjan van de Ven6d238cc2008-01-30 13:34:06 +0100253 if (set_pages_uc(page, 4) < 0) {
254 set_pages_wb(page, 4);
Jan Beulich89cf7cc2007-04-02 14:50:14 +0100255 __free_pages(page, 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 return NULL;
257 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700258 get_page(page);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259 atomic_inc(&agp_bridge->current_memory_agp);
260 return page_address(page);
261}
262
263static void i8xx_destroy_pages(void *addr)
264{
265 struct page *page;
266
267 if (addr == NULL)
268 return;
269
270 page = virt_to_page(addr);
Arjan van de Ven6d238cc2008-01-30 13:34:06 +0100271 set_pages_wb(page, 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 put_page(page);
Jan Beulich89cf7cc2007-04-02 14:50:14 +0100273 __free_pages(page, 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274 atomic_dec(&agp_bridge->current_memory_agp);
275}
276
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100277static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
278 int type)
279{
280 if (type < AGP_USER_TYPES)
281 return type;
282 else if (type == AGP_USER_CACHED_MEMORY)
283 return INTEL_AGP_CACHED_MEMORY;
284 else
285 return 0;
286}
287
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
289 int type)
290{
291 int i, j, num_entries;
292 void *temp;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100293 int ret = -EINVAL;
294 int mask_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100296 if (mem->page_count == 0)
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100297 goto out;
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100298
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299 temp = agp_bridge->current_size;
300 num_entries = A_SIZE_FIX(temp)->num_entries;
301
Dave Jones6a92a4e2006-02-28 00:54:25 -0500302 if ((pg_start + mem->page_count) > num_entries)
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100303 goto out_err;
304
Dave Jones6a92a4e2006-02-28 00:54:25 -0500305
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100307 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
308 ret = -EBUSY;
309 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700311 }
312
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100313 if (type != mem->type)
314 goto out_err;
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100315
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100316 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
317
318 switch (mask_type) {
319 case AGP_DCACHE_MEMORY:
320 if (!mem->is_flushed)
321 global_cache_flush();
322 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
323 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800324 intel_private.registers+I810_PTE_BASE+(i*4));
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100325 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800326 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100327 break;
328 case AGP_PHYS_MEMORY:
329 case AGP_NORMAL_MEMORY:
330 if (!mem->is_flushed)
331 global_cache_flush();
332 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
333 writel(agp_bridge->driver->mask_memory(agp_bridge,
334 mem->memory[i],
335 mask_type),
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800336 intel_private.registers+I810_PTE_BASE+(j*4));
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100337 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800338 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100339 break;
340 default:
341 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343
344 agp_bridge->driver->tlb_flush(mem);
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100345out:
346 ret = 0;
347out_err:
Dave Airlie9516b032008-06-19 10:42:17 +1000348 mem->is_flushed = true;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100349 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350}
351
352static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
353 int type)
354{
355 int i;
356
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100357 if (mem->page_count == 0)
358 return 0;
359
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800361 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800363 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365 agp_bridge->driver->tlb_flush(mem);
366 return 0;
367}
368
369/*
370 * The i810/i830 requires a physical address to program its mouse
371 * pointer into hardware.
372 * However the Xserver still writes to it through the agp aperture.
373 */
374static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
375{
376 struct agp_memory *new;
377 void *addr;
378
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379 switch (pg_count) {
380 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
381 break;
382 case 4:
383 /* kludge to get 4 physical pages for ARGB cursor */
384 addr = i8xx_alloc_pages();
385 break;
386 default:
387 return NULL;
388 }
389
390 if (addr == NULL)
391 return NULL;
392
393 new = agp_create_memory(pg_count);
394 if (new == NULL)
395 return NULL;
396
Keir Fraser07eee782005-03-30 13:17:04 -0800397 new->memory[0] = virt_to_gart(addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398 if (pg_count == 4) {
399 /* kludge to get 4 physical pages for ARGB cursor */
400 new->memory[1] = new->memory[0] + PAGE_SIZE;
401 new->memory[2] = new->memory[1] + PAGE_SIZE;
402 new->memory[3] = new->memory[2] + PAGE_SIZE;
403 }
404 new->page_count = pg_count;
405 new->num_scratch_pages = pg_count;
406 new->type = AGP_PHYS_MEMORY;
407 new->physical = new->memory[0];
408 return new;
409}
410
411static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
412{
413 struct agp_memory *new;
414
415 if (type == AGP_DCACHE_MEMORY) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800416 if (pg_count != intel_private.num_dcache_entries)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417 return NULL;
418
419 new = agp_create_memory(1);
420 if (new == NULL)
421 return NULL;
422
423 new->type = AGP_DCACHE_MEMORY;
424 new->page_count = pg_count;
425 new->num_scratch_pages = 0;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100426 agp_free_page_array(new);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427 return new;
428 }
429 if (type == AGP_PHYS_MEMORY)
430 return alloc_agpphysmem_i8xx(pg_count, type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 return NULL;
432}
433
434static void intel_i810_free_by_type(struct agp_memory *curr)
435{
436 agp_free_key(curr->key);
Dave Jones6a92a4e2006-02-28 00:54:25 -0500437 if (curr->type == AGP_PHYS_MEMORY) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700438 if (curr->page_count == 4)
Keir Fraser07eee782005-03-30 13:17:04 -0800439 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
Alan Hourihane88d51962005-11-06 23:35:34 -0800440 else {
Jan Beulichda503fa2008-06-18 09:28:00 +0100441 void *va = gart_to_virt(curr->memory[0]);
442
443 agp_bridge->driver->agp_destroy_page(va,
Dave Airliea2721e92007-10-15 10:19:16 +1000444 AGP_PAGE_DESTROY_UNMAP);
Jan Beulichda503fa2008-06-18 09:28:00 +0100445 agp_bridge->driver->agp_destroy_page(va,
Dave Airliea2721e92007-10-15 10:19:16 +1000446 AGP_PAGE_DESTROY_FREE);
Alan Hourihane88d51962005-11-06 23:35:34 -0800447 }
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100448 agp_free_page_array(curr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449 }
450 kfree(curr);
451}
452
453static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
454 unsigned long addr, int type)
455{
456 /* Type checking must be done elsewhere */
457 return addr | bridge->driver->masks[type].mask;
458}
459
460static struct aper_size_info_fixed intel_i830_sizes[] =
461{
462 {128, 32768, 5},
463 /* The 64M mode still requires a 128k gatt */
464 {64, 16384, 5},
465 {256, 65536, 6},
Eric Anholt65c25aa2006-09-06 11:57:18 -0400466 {512, 131072, 7},
Linus Torvalds1da177e2005-04-16 15:20:36 -0700467};
468
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469static void intel_i830_init_gtt_entries(void)
470{
471 u16 gmch_ctrl;
472 int gtt_entries;
473 u8 rdct;
474 int local = 0;
475 static const int ddt[4] = { 0, 16, 32, 64 };
Eric Anholtc41e0de2006-12-19 12:57:24 -0800476 int size; /* reserved space (in kb) at the top of stolen memory */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477
Dave Airlief011ae72008-01-25 11:23:04 +1000478 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479
Eric Anholtc41e0de2006-12-19 12:57:24 -0800480 if (IS_I965) {
481 u32 pgetbl_ctl;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800482 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
Eric Anholtc41e0de2006-12-19 12:57:24 -0800483
Eric Anholtc41e0de2006-12-19 12:57:24 -0800484 /* The 965 has a field telling us the size of the GTT,
485 * which may be larger than what is necessary to map the
486 * aperture.
487 */
488 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
489 case I965_PGETBL_SIZE_128KB:
490 size = 128;
491 break;
492 case I965_PGETBL_SIZE_256KB:
493 size = 256;
494 break;
495 case I965_PGETBL_SIZE_512KB:
496 size = 512;
497 break;
Zhenyu Wang4e8b6e22008-01-23 14:54:37 +1000498 case I965_PGETBL_SIZE_1MB:
499 size = 1024;
500 break;
501 case I965_PGETBL_SIZE_2MB:
502 size = 2048;
503 break;
504 case I965_PGETBL_SIZE_1_5MB:
505 size = 1024 + 512;
506 break;
Eric Anholtc41e0de2006-12-19 12:57:24 -0800507 default:
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700508 dev_info(&intel_private.pcidev->dev,
509 "unknown page table size, assuming 512KB\n");
Eric Anholtc41e0de2006-12-19 12:57:24 -0800510 size = 512;
511 }
512 size += 4; /* add in BIOS popup space */
Wang Zhenyu874808c62007-06-06 11:16:25 +0800513 } else if (IS_G33) {
514 /* G33's GTT size defined in gmch_ctrl */
515 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
516 case G33_PGETBL_SIZE_1M:
517 size = 1024;
518 break;
519 case G33_PGETBL_SIZE_2M:
520 size = 2048;
521 break;
522 default:
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700523 dev_info(&agp_bridge->dev->dev,
524 "unknown page table size 0x%x, assuming 512KB\n",
Wang Zhenyu874808c62007-06-06 11:16:25 +0800525 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
526 size = 512;
527 }
528 size += 4;
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000529 } else if (IS_G4X) {
530 /* On 4 series hardware, GTT stolen is separate from graphics
Eric Anholt82e14a62008-10-14 11:28:58 -0700531 * stolen, ignore it in stolen gtt entries counting. However,
532 * 4KB of the stolen memory doesn't get mapped to the GTT.
533 */
534 size = 4;
Eric Anholtc41e0de2006-12-19 12:57:24 -0800535 } else {
536 /* On previous hardware, the GTT size was just what was
537 * required to map the aperture.
538 */
539 size = agp_bridge->driver->fetch_size() + 4;
540 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541
542 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
543 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
544 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
545 case I830_GMCH_GMS_STOLEN_512:
546 gtt_entries = KB(512) - KB(size);
547 break;
548 case I830_GMCH_GMS_STOLEN_1024:
549 gtt_entries = MB(1) - KB(size);
550 break;
551 case I830_GMCH_GMS_STOLEN_8192:
552 gtt_entries = MB(8) - KB(size);
553 break;
554 case I830_GMCH_GMS_LOCAL:
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800555 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
557 MB(ddt[I830_RDRAM_DDT(rdct)]);
558 local = 1;
559 break;
560 default:
561 gtt_entries = 0;
562 break;
563 }
564 } else {
Dave Airliee67aa272007-09-18 22:46:35 -0700565 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700566 case I855_GMCH_GMS_STOLEN_1M:
567 gtt_entries = MB(1) - KB(size);
568 break;
569 case I855_GMCH_GMS_STOLEN_4M:
570 gtt_entries = MB(4) - KB(size);
571 break;
572 case I855_GMCH_GMS_STOLEN_8M:
573 gtt_entries = MB(8) - KB(size);
574 break;
575 case I855_GMCH_GMS_STOLEN_16M:
576 gtt_entries = MB(16) - KB(size);
577 break;
578 case I855_GMCH_GMS_STOLEN_32M:
579 gtt_entries = MB(32) - KB(size);
580 break;
581 case I915_GMCH_GMS_STOLEN_48M:
582 /* Check it's really I915G */
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000583 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584 gtt_entries = MB(48) - KB(size);
585 else
586 gtt_entries = 0;
587 break;
588 case I915_GMCH_GMS_STOLEN_64M:
589 /* Check it's really I915G */
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000590 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700591 gtt_entries = MB(64) - KB(size);
592 else
593 gtt_entries = 0;
Wang Zhenyu874808c62007-06-06 11:16:25 +0800594 break;
595 case G33_GMCH_GMS_STOLEN_128M:
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000596 if (IS_G33 || IS_I965 || IS_G4X)
Wang Zhenyu874808c62007-06-06 11:16:25 +0800597 gtt_entries = MB(128) - KB(size);
598 else
599 gtt_entries = 0;
600 break;
601 case G33_GMCH_GMS_STOLEN_256M:
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000602 if (IS_G33 || IS_I965 || IS_G4X)
Wang Zhenyu874808c62007-06-06 11:16:25 +0800603 gtt_entries = MB(256) - KB(size);
604 else
605 gtt_entries = 0;
606 break;
Zhenyu Wang25ce77a2008-06-19 14:17:58 +1000607 case INTEL_GMCH_GMS_STOLEN_96M:
608 if (IS_I965 || IS_G4X)
609 gtt_entries = MB(96) - KB(size);
610 else
611 gtt_entries = 0;
612 break;
613 case INTEL_GMCH_GMS_STOLEN_160M:
614 if (IS_I965 || IS_G4X)
615 gtt_entries = MB(160) - KB(size);
616 else
617 gtt_entries = 0;
618 break;
619 case INTEL_GMCH_GMS_STOLEN_224M:
620 if (IS_I965 || IS_G4X)
621 gtt_entries = MB(224) - KB(size);
622 else
623 gtt_entries = 0;
624 break;
625 case INTEL_GMCH_GMS_STOLEN_352M:
626 if (IS_I965 || IS_G4X)
627 gtt_entries = MB(352) - KB(size);
628 else
629 gtt_entries = 0;
630 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700631 default:
632 gtt_entries = 0;
633 break;
634 }
635 }
636 if (gtt_entries > 0)
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700637 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638 gtt_entries / KB(1), local ? "local" : "stolen");
639 else
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700640 dev_info(&agp_bridge->dev->dev,
641 "no pre-allocated video memory detected\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700642 gtt_entries /= KB(4);
643
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800644 intel_private.gtt_entries = gtt_entries;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700645}
646
Dave Airlie2162e6a2007-11-21 16:36:31 +1000647static void intel_i830_fini_flush(void)
648{
649 kunmap(intel_private.i8xx_page);
650 intel_private.i8xx_flush_page = NULL;
651 unmap_page_from_agp(intel_private.i8xx_page);
Dave Airlie2162e6a2007-11-21 16:36:31 +1000652
653 __free_page(intel_private.i8xx_page);
Dave Airlie4d64dd92008-01-23 15:34:29 +1000654 intel_private.i8xx_page = NULL;
Dave Airlie2162e6a2007-11-21 16:36:31 +1000655}
656
657static void intel_i830_setup_flush(void)
658{
Dave Airlie4d64dd92008-01-23 15:34:29 +1000659 /* return if we've already set the flush mechanism up */
660 if (intel_private.i8xx_page)
661 return;
Dave Airlie2162e6a2007-11-21 16:36:31 +1000662
663 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
Dave Airlief011ae72008-01-25 11:23:04 +1000664 if (!intel_private.i8xx_page)
Dave Airlie2162e6a2007-11-21 16:36:31 +1000665 return;
Dave Airlie2162e6a2007-11-21 16:36:31 +1000666
667 /* make page uncached */
668 map_page_into_agp(intel_private.i8xx_page);
Dave Airlie2162e6a2007-11-21 16:36:31 +1000669
670 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
671 if (!intel_private.i8xx_flush_page)
672 intel_i830_fini_flush();
673}
674
675static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
676{
677 unsigned int *pg = intel_private.i8xx_flush_page;
678 int i;
679
Dave Airlief011ae72008-01-25 11:23:04 +1000680 for (i = 0; i < 256; i += 2)
Dave Airlie2162e6a2007-11-21 16:36:31 +1000681 *(pg + i) = i;
Dave Airlief011ae72008-01-25 11:23:04 +1000682
Dave Airlie2162e6a2007-11-21 16:36:31 +1000683 wmb();
684}
685
Linus Torvalds1da177e2005-04-16 15:20:36 -0700686/* The intel i830 automatically initializes the agp aperture during POST.
687 * Use the memory already set aside for in the GTT.
688 */
689static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
690{
691 int page_order;
692 struct aper_size_info_fixed *size;
693 int num_entries;
694 u32 temp;
695
696 size = agp_bridge->current_size;
697 page_order = size->page_order;
698 num_entries = size->num_entries;
699 agp_bridge->gatt_table_real = NULL;
700
Dave Airlief011ae72008-01-25 11:23:04 +1000701 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700702 temp &= 0xfff80000;
703
Dave Airlief011ae72008-01-25 11:23:04 +1000704 intel_private.registers = ioremap(temp, 128 * 4096);
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800705 if (!intel_private.registers)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700706 return -ENOMEM;
707
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800708 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700709 global_cache_flush(); /* FIXME: ?? */
710
711 /* we have to call this as early as possible after the MMIO base address is known */
712 intel_i830_init_gtt_entries();
713
714 agp_bridge->gatt_table = NULL;
715
716 agp_bridge->gatt_bus_addr = temp;
717
718 return 0;
719}
720
721/* Return the gatt table to a sane state. Use the top of stolen
722 * memory for the GTT.
723 */
724static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
725{
726 return 0;
727}
728
729static int intel_i830_fetch_size(void)
730{
731 u16 gmch_ctrl;
732 struct aper_size_info_fixed *values;
733
734 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
735
736 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
737 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
738 /* 855GM/852GM/865G has 128MB aperture size */
739 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
740 agp_bridge->aperture_size_idx = 0;
741 return values[0].size;
742 }
743
Dave Airlief011ae72008-01-25 11:23:04 +1000744 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745
746 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
747 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
748 agp_bridge->aperture_size_idx = 0;
749 return values[0].size;
750 } else {
751 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
752 agp_bridge->aperture_size_idx = 1;
753 return values[1].size;
754 }
755
756 return 0;
757}
758
759static int intel_i830_configure(void)
760{
761 struct aper_size_info_fixed *current_size;
762 u32 temp;
763 u16 gmch_ctrl;
764 int i;
765
766 current_size = A_SIZE_FIX(agp_bridge->current_size);
767
Dave Airlief011ae72008-01-25 11:23:04 +1000768 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700769 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
770
Dave Airlief011ae72008-01-25 11:23:04 +1000771 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700772 gmch_ctrl |= I830_GMCH_ENABLED;
Dave Airlief011ae72008-01-25 11:23:04 +1000773 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800775 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
776 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700777
778 if (agp_bridge->driver->needs_scratch_page) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800779 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
780 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781 }
Keith Packard44d49442008-10-14 17:18:45 -0700782 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783 }
784
785 global_cache_flush();
Dave Airlie2162e6a2007-11-21 16:36:31 +1000786
787 intel_i830_setup_flush();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788 return 0;
789}
790
791static void intel_i830_cleanup(void)
792{
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800793 iounmap(intel_private.registers);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794}
795
Dave Airlief011ae72008-01-25 11:23:04 +1000796static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
797 int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798{
Dave Airlief011ae72008-01-25 11:23:04 +1000799 int i, j, num_entries;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700800 void *temp;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100801 int ret = -EINVAL;
802 int mask_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700803
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100804 if (mem->page_count == 0)
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100805 goto out;
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100806
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807 temp = agp_bridge->current_size;
808 num_entries = A_SIZE_FIX(temp)->num_entries;
809
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800810 if (pg_start < intel_private.gtt_entries) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700811 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
812 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
813 pg_start, intel_private.gtt_entries);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700815 dev_info(&intel_private.pcidev->dev,
816 "trying to insert into local/stolen memory\n");
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100817 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818 }
819
820 if ((pg_start + mem->page_count) > num_entries)
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100821 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700822
823 /* The i830 can't check the GTT for entries since its read only,
824 * depend on the caller to make the correct offset decisions.
825 */
826
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100827 if (type != mem->type)
828 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100830 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
831
832 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
833 mask_type != INTEL_AGP_CACHED_MEMORY)
834 goto out_err;
835
836 if (!mem->is_flushed)
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100837 global_cache_flush();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838
839 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
840 writel(agp_bridge->driver->mask_memory(agp_bridge,
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100841 mem->memory[i], mask_type),
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800842 intel_private.registers+I810_PTE_BASE+(j*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800844 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845 agp_bridge->driver->tlb_flush(mem);
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100846
847out:
848 ret = 0;
849out_err:
Dave Airlie9516b032008-06-19 10:42:17 +1000850 mem->is_flushed = true;
Thomas Hellstroma030ce42007-01-23 10:33:43 +0100851 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852}
853
Dave Airlief011ae72008-01-25 11:23:04 +1000854static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
855 int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856{
857 int i;
858
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +0100859 if (mem->page_count == 0)
860 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800862 if (pg_start < intel_private.gtt_entries) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700863 dev_info(&intel_private.pcidev->dev,
864 "trying to disable local/stolen memory\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865 return -EINVAL;
866 }
867
868 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800869 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700870 }
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800871 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700872
Linus Torvalds1da177e2005-04-16 15:20:36 -0700873 agp_bridge->driver->tlb_flush(mem);
874 return 0;
875}
876
Dave Airlief011ae72008-01-25 11:23:04 +1000877static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878{
879 if (type == AGP_PHYS_MEMORY)
880 return alloc_agpphysmem_i8xx(pg_count, type);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881 /* always return NULL for other allocation types for now */
882 return NULL;
883}
884
Dave Airlie6c00a612007-10-29 18:06:10 +1000885static int intel_alloc_chipset_flush_resource(void)
886{
887 int ret;
888 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
889 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
890 pcibios_align_resource, agp_bridge->dev);
Dave Airlie6c00a612007-10-29 18:06:10 +1000891
Dave Airlie2162e6a2007-11-21 16:36:31 +1000892 return ret;
Dave Airlie6c00a612007-10-29 18:06:10 +1000893}
894
895static void intel_i915_setup_chipset_flush(void)
896{
897 int ret;
898 u32 temp;
899
900 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
901 if (!(temp & 0x1)) {
902 intel_alloc_chipset_flush_resource();
Dave Airlie4d64dd92008-01-23 15:34:29 +1000903 intel_private.resource_valid = 1;
Dave Airlie6c00a612007-10-29 18:06:10 +1000904 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
905 } else {
906 temp &= ~1;
907
Dave Airlie4d64dd92008-01-23 15:34:29 +1000908 intel_private.resource_valid = 1;
Dave Airlie6c00a612007-10-29 18:06:10 +1000909 intel_private.ifp_resource.start = temp;
910 intel_private.ifp_resource.end = temp + PAGE_SIZE;
911 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
Dave Airlie4d64dd92008-01-23 15:34:29 +1000912 /* some BIOSes reserve this area in a pnp some don't */
913 if (ret)
914 intel_private.resource_valid = 0;
Dave Airlie6c00a612007-10-29 18:06:10 +1000915 }
916}
917
918static void intel_i965_g33_setup_chipset_flush(void)
919{
920 u32 temp_hi, temp_lo;
921 int ret;
922
923 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
924 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
925
926 if (!(temp_lo & 0x1)) {
927
928 intel_alloc_chipset_flush_resource();
929
Dave Airlie4d64dd92008-01-23 15:34:29 +1000930 intel_private.resource_valid = 1;
Andrew Morton1fa4db72007-11-29 10:00:48 +1000931 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
932 upper_32_bits(intel_private.ifp_resource.start));
Dave Airlie6c00a612007-10-29 18:06:10 +1000933 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
Dave Airlie6c00a612007-10-29 18:06:10 +1000934 } else {
935 u64 l64;
Dave Airlief011ae72008-01-25 11:23:04 +1000936
Dave Airlie6c00a612007-10-29 18:06:10 +1000937 temp_lo &= ~0x1;
938 l64 = ((u64)temp_hi << 32) | temp_lo;
939
Dave Airlie4d64dd92008-01-23 15:34:29 +1000940 intel_private.resource_valid = 1;
Dave Airlie6c00a612007-10-29 18:06:10 +1000941 intel_private.ifp_resource.start = l64;
942 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
943 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
Dave Airlie4d64dd92008-01-23 15:34:29 +1000944 /* some BIOSes reserve this area in a pnp some don't */
945 if (ret)
946 intel_private.resource_valid = 0;
Dave Airlie6c00a612007-10-29 18:06:10 +1000947 }
948}
949
Dave Airlie2162e6a2007-11-21 16:36:31 +1000950static void intel_i9xx_setup_flush(void)
951{
Dave Airlie4d64dd92008-01-23 15:34:29 +1000952 /* return if already configured */
953 if (intel_private.ifp_resource.start)
954 return;
Dave Airlie2162e6a2007-11-21 16:36:31 +1000955
Dave Airlie4d64dd92008-01-23 15:34:29 +1000956 /* setup a resource for this object */
Dave Airlie2162e6a2007-11-21 16:36:31 +1000957 intel_private.ifp_resource.name = "Intel Flush Page";
958 intel_private.ifp_resource.flags = IORESOURCE_MEM;
959
960 /* Setup chipset flush for 915 */
Zhenyu Wang7d15ddf2008-06-20 11:48:06 +1000961 if (IS_I965 || IS_G33 || IS_G4X) {
Dave Airlie2162e6a2007-11-21 16:36:31 +1000962 intel_i965_g33_setup_chipset_flush();
963 } else {
964 intel_i915_setup_chipset_flush();
965 }
966
967 if (intel_private.ifp_resource.start) {
968 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
969 if (!intel_private.i9xx_flush_page)
Bjorn Helgaase3cf6952008-07-30 12:26:51 -0700970 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
Dave Airlie2162e6a2007-11-21 16:36:31 +1000971 }
972}
973
Linus Torvalds1da177e2005-04-16 15:20:36 -0700974static int intel_i915_configure(void)
975{
976 struct aper_size_info_fixed *current_size;
977 u32 temp;
978 u16 gmch_ctrl;
979 int i;
980
981 current_size = A_SIZE_FIX(agp_bridge->current_size);
982
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800983 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984
985 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
986
Dave Airlief011ae72008-01-25 11:23:04 +1000987 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700988 gmch_ctrl |= I830_GMCH_ENABLED;
Dave Airlief011ae72008-01-25 11:23:04 +1000989 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700990
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800991 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
992 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700993
994 if (agp_bridge->driver->needs_scratch_page) {
Wang Zhenyuc4ca8812007-05-30 09:40:46 +0800995 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
996 writel(agp_bridge->scratch_page, intel_private.gtt+i);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700997 }
Keith Packard44d49442008-10-14 17:18:45 -0700998 readl(intel_private.gtt+i-1); /* PCI Posting. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999 }
1000
1001 global_cache_flush();
Dave Airlie6c00a612007-10-29 18:06:10 +10001002
Dave Airlie2162e6a2007-11-21 16:36:31 +10001003 intel_i9xx_setup_flush();
Dave Airlief011ae72008-01-25 11:23:04 +10001004
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005 return 0;
1006}
1007
1008static void intel_i915_cleanup(void)
1009{
Dave Airlie2162e6a2007-11-21 16:36:31 +10001010 if (intel_private.i9xx_flush_page)
1011 iounmap(intel_private.i9xx_flush_page);
Dave Airlie4d64dd92008-01-23 15:34:29 +10001012 if (intel_private.resource_valid)
1013 release_resource(&intel_private.ifp_resource);
1014 intel_private.ifp_resource.start = 0;
1015 intel_private.resource_valid = 0;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001016 iounmap(intel_private.gtt);
1017 iounmap(intel_private.registers);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018}
1019
Dave Airlie6c00a612007-10-29 18:06:10 +10001020static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1021{
Dave Airlie2162e6a2007-11-21 16:36:31 +10001022 if (intel_private.i9xx_flush_page)
1023 writel(1, intel_private.i9xx_flush_page);
Dave Airlie6c00a612007-10-29 18:06:10 +10001024}
1025
Dave Airlief011ae72008-01-25 11:23:04 +10001026static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1027 int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028{
Dave Airlief011ae72008-01-25 11:23:04 +10001029 int i, j, num_entries;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030 void *temp;
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001031 int ret = -EINVAL;
1032 int mask_type;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001033
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +01001034 if (mem->page_count == 0)
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001035 goto out;
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +01001036
Linus Torvalds1da177e2005-04-16 15:20:36 -07001037 temp = agp_bridge->current_size;
1038 num_entries = A_SIZE_FIX(temp)->num_entries;
1039
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001040 if (pg_start < intel_private.gtt_entries) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07001041 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1042 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1043 pg_start, intel_private.gtt_entries);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07001045 dev_info(&intel_private.pcidev->dev,
1046 "trying to insert into local/stolen memory\n");
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001047 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001048 }
1049
1050 if ((pg_start + mem->page_count) > num_entries)
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001051 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001053 /* The i915 can't check the GTT for entries since its read only,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001054 * depend on the caller to make the correct offset decisions.
1055 */
1056
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001057 if (type != mem->type)
1058 goto out_err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001059
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001060 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1061
1062 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1063 mask_type != INTEL_AGP_CACHED_MEMORY)
1064 goto out_err;
1065
1066 if (!mem->is_flushed)
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +01001067 global_cache_flush();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068
1069 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1070 writel(agp_bridge->driver->mask_memory(agp_bridge,
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001071 mem->memory[i], mask_type), intel_private.gtt+j);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072 }
1073
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001074 readl(intel_private.gtt+j-1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001075 agp_bridge->driver->tlb_flush(mem);
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001076
1077 out:
1078 ret = 0;
1079 out_err:
Dave Airlie9516b032008-06-19 10:42:17 +10001080 mem->is_flushed = true;
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001081 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082}
1083
Dave Airlief011ae72008-01-25 11:23:04 +10001084static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1085 int type)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001086{
1087 int i;
1088
Thomas Hellstrom5aa80c72006-12-20 16:33:41 +01001089 if (mem->page_count == 0)
1090 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001091
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001092 if (pg_start < intel_private.gtt_entries) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07001093 dev_info(&intel_private.pcidev->dev,
1094 "trying to disable local/stolen memory\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095 return -EINVAL;
1096 }
1097
Dave Airlief011ae72008-01-25 11:23:04 +10001098 for (i = pg_start; i < (mem->page_count + pg_start); i++)
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001099 writel(agp_bridge->scratch_page, intel_private.gtt+i);
Dave Airlief011ae72008-01-25 11:23:04 +10001100
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001101 readl(intel_private.gtt+i-1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001102
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103 agp_bridge->driver->tlb_flush(mem);
1104 return 0;
1105}
1106
Eric Anholtc41e0de2006-12-19 12:57:24 -08001107/* Return the aperture size by just checking the resource length. The effect
1108 * described in the spec of the MSAC registers is just changing of the
1109 * resource size.
1110 */
1111static int intel_i9xx_fetch_size(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001112{
Ahmed S. Darwish1eaf1222007-02-06 18:08:28 +02001113 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
Eric Anholtc41e0de2006-12-19 12:57:24 -08001114 int aper_size; /* size in megabytes */
1115 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001117 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001118
Eric Anholtc41e0de2006-12-19 12:57:24 -08001119 for (i = 0; i < num_sizes; i++) {
1120 if (aper_size == intel_i830_sizes[i].size) {
1121 agp_bridge->current_size = intel_i830_sizes + i;
1122 agp_bridge->previous_size = agp_bridge->current_size;
1123 return aper_size;
1124 }
1125 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126
Eric Anholtc41e0de2006-12-19 12:57:24 -08001127 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001128}
1129
1130/* The intel i915 automatically initializes the agp aperture during POST.
1131 * Use the memory already set aside for in the GTT.
1132 */
1133static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1134{
1135 int page_order;
1136 struct aper_size_info_fixed *size;
1137 int num_entries;
1138 u32 temp, temp2;
Zhenyu Wang47406222007-09-11 15:23:58 -07001139 int gtt_map_size = 256 * 1024;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140
1141 size = agp_bridge->current_size;
1142 page_order = size->page_order;
1143 num_entries = size->num_entries;
1144 agp_bridge->gatt_table_real = NULL;
1145
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001146 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
Dave Airlief011ae72008-01-25 11:23:04 +10001147 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001148
Zhenyu Wang47406222007-09-11 15:23:58 -07001149 if (IS_G33)
1150 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1151 intel_private.gtt = ioremap(temp2, gtt_map_size);
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001152 if (!intel_private.gtt)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153 return -ENOMEM;
1154
1155 temp &= 0xfff80000;
1156
Dave Airlief011ae72008-01-25 11:23:04 +10001157 intel_private.registers = ioremap(temp, 128 * 4096);
Scott Thompson5bdbc7d2007-08-25 18:14:00 +10001158 if (!intel_private.registers) {
1159 iounmap(intel_private.gtt);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001160 return -ENOMEM;
Scott Thompson5bdbc7d2007-08-25 18:14:00 +10001161 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001162
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08001163 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001164 global_cache_flush(); /* FIXME: ? */
1165
1166 /* we have to call this as early as possible after the MMIO base address is known */
1167 intel_i830_init_gtt_entries();
1168
1169 agp_bridge->gatt_table = NULL;
1170
1171 agp_bridge->gatt_bus_addr = temp;
1172
1173 return 0;
1174}
Linus Torvalds7d915a32006-11-22 09:37:54 -08001175
1176/*
1177 * The i965 supports 36-bit physical addresses, but to keep
1178 * the format of the GTT the same, the bits that don't fit
1179 * in a 32-bit word are shifted down to bits 4..7.
1180 *
1181 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1182 * is always zero on 32-bit architectures, so no need to make
1183 * this conditional.
1184 */
1185static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1186 unsigned long addr, int type)
1187{
1188 /* Shift high bits down */
1189 addr |= (addr >> 28) & 0xf0;
1190
1191 /* Type checking must be done elsewhere */
1192 return addr | bridge->driver->masks[type].mask;
1193}
1194
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10001195static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1196{
1197 switch (agp_bridge->dev->device) {
Zhenyu Wang99d32bd2008-07-30 12:26:50 -07001198 case PCI_DEVICE_ID_INTEL_GM45_HB:
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10001199 case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1200 case PCI_DEVICE_ID_INTEL_Q45_HB:
1201 case PCI_DEVICE_ID_INTEL_G45_HB:
Zhenyu Wanga50ccc62008-11-17 14:39:00 +08001202 case PCI_DEVICE_ID_INTEL_G41_HB:
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10001203 *gtt_offset = *gtt_size = MB(2);
1204 break;
1205 default:
1206 *gtt_offset = *gtt_size = KB(512);
1207 }
1208}
1209
Eric Anholt65c25aa2006-09-06 11:57:18 -04001210/* The intel i965 automatically initializes the agp aperture during POST.
Eric Anholtc41e0de2006-12-19 12:57:24 -08001211 * Use the memory already set aside for in the GTT.
1212 */
Eric Anholt65c25aa2006-09-06 11:57:18 -04001213static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1214{
Dave Airlie62c96b92008-06-19 14:27:53 +10001215 int page_order;
1216 struct aper_size_info_fixed *size;
1217 int num_entries;
1218 u32 temp;
1219 int gtt_offset, gtt_size;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001220
Dave Airlie62c96b92008-06-19 14:27:53 +10001221 size = agp_bridge->current_size;
1222 page_order = size->page_order;
1223 num_entries = size->num_entries;
1224 agp_bridge->gatt_table_real = NULL;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001225
Dave Airlie62c96b92008-06-19 14:27:53 +10001226 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
Eric Anholt65c25aa2006-09-06 11:57:18 -04001227
Dave Airlie62c96b92008-06-19 14:27:53 +10001228 temp &= 0xfff00000;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001229
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10001230 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
Eric Anholt65c25aa2006-09-06 11:57:18 -04001231
Dave Airlie62c96b92008-06-19 14:27:53 +10001232 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
Eric Anholt65c25aa2006-09-06 11:57:18 -04001233
Dave Airlie62c96b92008-06-19 14:27:53 +10001234 if (!intel_private.gtt)
1235 return -ENOMEM;
Zhenyu Wang4e8b6e22008-01-23 14:54:37 +10001236
Dave Airlie62c96b92008-06-19 14:27:53 +10001237 intel_private.registers = ioremap(temp, 128 * 4096);
1238 if (!intel_private.registers) {
Scott Thompson5bdbc7d2007-08-25 18:14:00 +10001239 iounmap(intel_private.gtt);
1240 return -ENOMEM;
1241 }
Eric Anholt65c25aa2006-09-06 11:57:18 -04001242
Dave Airlie62c96b92008-06-19 14:27:53 +10001243 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1244 global_cache_flush(); /* FIXME: ? */
Eric Anholt65c25aa2006-09-06 11:57:18 -04001245
Dave Airlie62c96b92008-06-19 14:27:53 +10001246 /* we have to call this as early as possible after the MMIO base address is known */
1247 intel_i830_init_gtt_entries();
Eric Anholt65c25aa2006-09-06 11:57:18 -04001248
Dave Airlie62c96b92008-06-19 14:27:53 +10001249 agp_bridge->gatt_table = NULL;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001250
Dave Airlie62c96b92008-06-19 14:27:53 +10001251 agp_bridge->gatt_bus_addr = temp;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001252
Dave Airlie62c96b92008-06-19 14:27:53 +10001253 return 0;
Eric Anholt65c25aa2006-09-06 11:57:18 -04001254}
1255
Linus Torvalds1da177e2005-04-16 15:20:36 -07001256
1257static int intel_fetch_size(void)
1258{
1259 int i;
1260 u16 temp;
1261 struct aper_size_info_16 *values;
1262
1263 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1264 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1265
1266 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1267 if (temp == values[i].size_value) {
1268 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1269 agp_bridge->aperture_size_idx = i;
1270 return values[i].size;
1271 }
1272 }
1273
1274 return 0;
1275}
1276
1277static int __intel_8xx_fetch_size(u8 temp)
1278{
1279 int i;
1280 struct aper_size_info_8 *values;
1281
1282 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1283
1284 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1285 if (temp == values[i].size_value) {
1286 agp_bridge->previous_size =
1287 agp_bridge->current_size = (void *) (values + i);
1288 agp_bridge->aperture_size_idx = i;
1289 return values[i].size;
1290 }
1291 }
1292 return 0;
1293}
1294
1295static int intel_8xx_fetch_size(void)
1296{
1297 u8 temp;
1298
1299 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1300 return __intel_8xx_fetch_size(temp);
1301}
1302
1303static int intel_815_fetch_size(void)
1304{
1305 u8 temp;
1306
1307 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1308 * one non-reserved bit, so mask the others out ... */
1309 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1310 temp &= (1 << 3);
1311
1312 return __intel_8xx_fetch_size(temp);
1313}
1314
1315static void intel_tlbflush(struct agp_memory *mem)
1316{
1317 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1318 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1319}
1320
1321
1322static void intel_8xx_tlbflush(struct agp_memory *mem)
1323{
1324 u32 temp;
1325 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1326 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1327 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1328 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1329}
1330
1331
1332static void intel_cleanup(void)
1333{
1334 u16 temp;
1335 struct aper_size_info_16 *previous_size;
1336
1337 previous_size = A_SIZE_16(agp_bridge->previous_size);
1338 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1339 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1340 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1341}
1342
1343
1344static void intel_8xx_cleanup(void)
1345{
1346 u16 temp;
1347 struct aper_size_info_8 *previous_size;
1348
1349 previous_size = A_SIZE_8(agp_bridge->previous_size);
1350 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1351 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1352 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1353}
1354
1355
1356static int intel_configure(void)
1357{
1358 u32 temp;
1359 u16 temp2;
1360 struct aper_size_info_16 *current_size;
1361
1362 current_size = A_SIZE_16(agp_bridge->current_size);
1363
1364 /* aperture size */
1365 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1366
1367 /* address to map to */
1368 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1369 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1370
1371 /* attbase - aperture base */
1372 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1373
1374 /* agpctrl */
1375 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1376
1377 /* paccfg/nbxcfg */
1378 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1379 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1380 (temp2 & ~(1 << 10)) | (1 << 9));
1381 /* clear any possible error conditions */
1382 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1383 return 0;
1384}
1385
1386static int intel_815_configure(void)
1387{
1388 u32 temp, addr;
1389 u8 temp2;
1390 struct aper_size_info_8 *current_size;
1391
1392 /* attbase - aperture base */
1393 /* the Intel 815 chipset spec. says that bits 29-31 in the
1394 * ATTBASE register are reserved -> try not to write them */
1395 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07001396 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001397 return -EINVAL;
1398 }
1399
1400 current_size = A_SIZE_8(agp_bridge->current_size);
1401
1402 /* aperture size */
1403 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1404 current_size->size_value);
1405
1406 /* address to map to */
1407 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1408 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1409
1410 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1411 addr &= INTEL_815_ATTBASE_MASK;
1412 addr |= agp_bridge->gatt_bus_addr;
1413 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1414
1415 /* agpctrl */
1416 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1417
1418 /* apcont */
1419 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1420 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1421
1422 /* clear any possible error conditions */
1423 /* Oddness : this chipset seems to have no ERRSTS register ! */
1424 return 0;
1425}
1426
1427static void intel_820_tlbflush(struct agp_memory *mem)
1428{
1429 return;
1430}
1431
1432static void intel_820_cleanup(void)
1433{
1434 u8 temp;
1435 struct aper_size_info_8 *previous_size;
1436
1437 previous_size = A_SIZE_8(agp_bridge->previous_size);
1438 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1439 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1440 temp & ~(1 << 1));
1441 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1442 previous_size->size_value);
1443}
1444
1445
1446static int intel_820_configure(void)
1447{
1448 u32 temp;
1449 u8 temp2;
1450 struct aper_size_info_8 *current_size;
1451
1452 current_size = A_SIZE_8(agp_bridge->current_size);
1453
1454 /* aperture size */
1455 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1456
1457 /* address to map to */
1458 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1459 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1460
1461 /* attbase - aperture base */
1462 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1463
1464 /* agpctrl */
1465 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1466
1467 /* global enable aperture access */
1468 /* This flag is not accessed through MCHCFG register as in */
1469 /* i850 chipset. */
1470 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1471 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1472 /* clear any possible AGP-related error conditions */
1473 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1474 return 0;
1475}
1476
1477static int intel_840_configure(void)
1478{
1479 u32 temp;
1480 u16 temp2;
1481 struct aper_size_info_8 *current_size;
1482
1483 current_size = A_SIZE_8(agp_bridge->current_size);
1484
1485 /* aperture size */
1486 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1487
1488 /* address to map to */
1489 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1490 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1491
1492 /* attbase - aperture base */
1493 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1494
1495 /* agpctrl */
1496 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1497
1498 /* mcgcfg */
1499 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1500 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1501 /* clear any possible error conditions */
1502 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1503 return 0;
1504}
1505
1506static int intel_845_configure(void)
1507{
1508 u32 temp;
1509 u8 temp2;
1510 struct aper_size_info_8 *current_size;
1511
1512 current_size = A_SIZE_8(agp_bridge->current_size);
1513
1514 /* aperture size */
1515 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1516
Matthew Garrettb0825482005-07-29 14:03:39 -07001517 if (agp_bridge->apbase_config != 0) {
1518 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1519 agp_bridge->apbase_config);
1520 } else {
1521 /* address to map to */
1522 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1523 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1524 agp_bridge->apbase_config = temp;
1525 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526
1527 /* attbase - aperture base */
1528 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1529
1530 /* agpctrl */
1531 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1532
1533 /* agpm */
1534 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1535 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1536 /* clear any possible error conditions */
1537 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
Dave Airlie2162e6a2007-11-21 16:36:31 +10001538
1539 intel_i830_setup_flush();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001540 return 0;
1541}
1542
1543static int intel_850_configure(void)
1544{
1545 u32 temp;
1546 u16 temp2;
1547 struct aper_size_info_8 *current_size;
1548
1549 current_size = A_SIZE_8(agp_bridge->current_size);
1550
1551 /* aperture size */
1552 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1553
1554 /* address to map to */
1555 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1556 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1557
1558 /* attbase - aperture base */
1559 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1560
1561 /* agpctrl */
1562 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1563
1564 /* mcgcfg */
1565 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1566 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1567 /* clear any possible AGP-related error conditions */
1568 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1569 return 0;
1570}
1571
1572static int intel_860_configure(void)
1573{
1574 u32 temp;
1575 u16 temp2;
1576 struct aper_size_info_8 *current_size;
1577
1578 current_size = A_SIZE_8(agp_bridge->current_size);
1579
1580 /* aperture size */
1581 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1582
1583 /* address to map to */
1584 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1585 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1586
1587 /* attbase - aperture base */
1588 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1589
1590 /* agpctrl */
1591 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1592
1593 /* mcgcfg */
1594 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1595 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1596 /* clear any possible AGP-related error conditions */
1597 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1598 return 0;
1599}
1600
1601static int intel_830mp_configure(void)
1602{
1603 u32 temp;
1604 u16 temp2;
1605 struct aper_size_info_8 *current_size;
1606
1607 current_size = A_SIZE_8(agp_bridge->current_size);
1608
1609 /* aperture size */
1610 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1611
1612 /* address to map to */
1613 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1614 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1615
1616 /* attbase - aperture base */
1617 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1618
1619 /* agpctrl */
1620 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1621
1622 /* gmch */
1623 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1624 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1625 /* clear any possible AGP-related error conditions */
1626 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1627 return 0;
1628}
1629
1630static int intel_7505_configure(void)
1631{
1632 u32 temp;
1633 u16 temp2;
1634 struct aper_size_info_8 *current_size;
1635
1636 current_size = A_SIZE_8(agp_bridge->current_size);
1637
1638 /* aperture size */
1639 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1640
1641 /* address to map to */
1642 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1643 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1644
1645 /* attbase - aperture base */
1646 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1647
1648 /* agpctrl */
1649 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1650
1651 /* mchcfg */
1652 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1653 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1654
1655 return 0;
1656}
1657
1658/* Setup function */
Dave Jonese5524f32007-02-22 18:41:28 -05001659static const struct gatt_mask intel_generic_masks[] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001660{
1661 {.mask = 0x00000017, .type = 0}
1662};
1663
Dave Jonese5524f32007-02-22 18:41:28 -05001664static const struct aper_size_info_8 intel_815_sizes[2] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001665{
1666 {64, 16384, 4, 0},
1667 {32, 8192, 3, 8},
1668};
1669
Dave Jonese5524f32007-02-22 18:41:28 -05001670static const struct aper_size_info_8 intel_8xx_sizes[7] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001671{
1672 {256, 65536, 6, 0},
1673 {128, 32768, 5, 32},
1674 {64, 16384, 4, 48},
1675 {32, 8192, 3, 56},
1676 {16, 4096, 2, 60},
1677 {8, 2048, 1, 62},
1678 {4, 1024, 0, 63}
1679};
1680
Dave Jonese5524f32007-02-22 18:41:28 -05001681static const struct aper_size_info_16 intel_generic_sizes[7] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001682{
1683 {256, 65536, 6, 0},
1684 {128, 32768, 5, 32},
1685 {64, 16384, 4, 48},
1686 {32, 8192, 3, 56},
1687 {16, 4096, 2, 60},
1688 {8, 2048, 1, 62},
1689 {4, 1024, 0, 63}
1690};
1691
Dave Jonese5524f32007-02-22 18:41:28 -05001692static const struct aper_size_info_8 intel_830mp_sizes[4] =
Linus Torvalds1da177e2005-04-16 15:20:36 -07001693{
1694 {256, 65536, 6, 0},
1695 {128, 32768, 5, 32},
1696 {64, 16384, 4, 48},
1697 {32, 8192, 3, 56}
1698};
1699
Dave Jonese5524f32007-02-22 18:41:28 -05001700static const struct agp_bridge_driver intel_generic_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001701 .owner = THIS_MODULE,
1702 .aperture_sizes = intel_generic_sizes,
1703 .size_type = U16_APER_SIZE,
1704 .num_aperture_sizes = 7,
1705 .configure = intel_configure,
1706 .fetch_size = intel_fetch_size,
1707 .cleanup = intel_cleanup,
1708 .tlb_flush = intel_tlbflush,
1709 .mask_memory = agp_generic_mask_memory,
1710 .masks = intel_generic_masks,
1711 .agp_enable = agp_generic_enable,
1712 .cache_flush = global_cache_flush,
1713 .create_gatt_table = agp_generic_create_gatt_table,
1714 .free_gatt_table = agp_generic_free_gatt_table,
1715 .insert_memory = agp_generic_insert_memory,
1716 .remove_memory = agp_generic_remove_memory,
1717 .alloc_by_type = agp_generic_alloc_by_type,
1718 .free_by_type = agp_generic_free_by_type,
1719 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001720 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001721 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001722 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001723 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001724};
1725
Dave Jonese5524f32007-02-22 18:41:28 -05001726static const struct agp_bridge_driver intel_810_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001727 .owner = THIS_MODULE,
1728 .aperture_sizes = intel_i810_sizes,
1729 .size_type = FIXED_APER_SIZE,
1730 .num_aperture_sizes = 2,
Joe Perchesc7258012008-03-26 14:10:02 -07001731 .needs_scratch_page = true,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001732 .configure = intel_i810_configure,
1733 .fetch_size = intel_i810_fetch_size,
1734 .cleanup = intel_i810_cleanup,
1735 .tlb_flush = intel_i810_tlbflush,
1736 .mask_memory = intel_i810_mask_memory,
1737 .masks = intel_i810_masks,
1738 .agp_enable = intel_i810_agp_enable,
1739 .cache_flush = global_cache_flush,
1740 .create_gatt_table = agp_generic_create_gatt_table,
1741 .free_gatt_table = agp_generic_free_gatt_table,
1742 .insert_memory = intel_i810_insert_entries,
1743 .remove_memory = intel_i810_remove_entries,
1744 .alloc_by_type = intel_i810_alloc_by_type,
1745 .free_by_type = intel_i810_free_by_type,
1746 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001747 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001748 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001749 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001750 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001751};
1752
Dave Jonese5524f32007-02-22 18:41:28 -05001753static const struct agp_bridge_driver intel_815_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001754 .owner = THIS_MODULE,
1755 .aperture_sizes = intel_815_sizes,
1756 .size_type = U8_APER_SIZE,
1757 .num_aperture_sizes = 2,
1758 .configure = intel_815_configure,
1759 .fetch_size = intel_815_fetch_size,
1760 .cleanup = intel_8xx_cleanup,
1761 .tlb_flush = intel_8xx_tlbflush,
1762 .mask_memory = agp_generic_mask_memory,
1763 .masks = intel_generic_masks,
1764 .agp_enable = agp_generic_enable,
1765 .cache_flush = global_cache_flush,
1766 .create_gatt_table = agp_generic_create_gatt_table,
1767 .free_gatt_table = agp_generic_free_gatt_table,
1768 .insert_memory = agp_generic_insert_memory,
1769 .remove_memory = agp_generic_remove_memory,
1770 .alloc_by_type = agp_generic_alloc_by_type,
1771 .free_by_type = agp_generic_free_by_type,
1772 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001773 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001774 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001775 .agp_destroy_pages = agp_generic_destroy_pages,
Dave Airlie62c96b92008-06-19 14:27:53 +10001776 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001777};
1778
Dave Jonese5524f32007-02-22 18:41:28 -05001779static const struct agp_bridge_driver intel_830_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001780 .owner = THIS_MODULE,
1781 .aperture_sizes = intel_i830_sizes,
1782 .size_type = FIXED_APER_SIZE,
Dave Jonesc14635e2006-09-06 11:59:35 -04001783 .num_aperture_sizes = 4,
Joe Perchesc7258012008-03-26 14:10:02 -07001784 .needs_scratch_page = true,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001785 .configure = intel_i830_configure,
1786 .fetch_size = intel_i830_fetch_size,
1787 .cleanup = intel_i830_cleanup,
1788 .tlb_flush = intel_i810_tlbflush,
1789 .mask_memory = intel_i810_mask_memory,
1790 .masks = intel_i810_masks,
1791 .agp_enable = intel_i810_agp_enable,
1792 .cache_flush = global_cache_flush,
1793 .create_gatt_table = intel_i830_create_gatt_table,
1794 .free_gatt_table = intel_i830_free_gatt_table,
1795 .insert_memory = intel_i830_insert_entries,
1796 .remove_memory = intel_i830_remove_entries,
1797 .alloc_by_type = intel_i830_alloc_by_type,
1798 .free_by_type = intel_i810_free_by_type,
1799 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001800 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001801 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001802 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001803 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
Dave Airlie2162e6a2007-11-21 16:36:31 +10001804 .chipset_flush = intel_i830_chipset_flush,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001805};
1806
Dave Jonese5524f32007-02-22 18:41:28 -05001807static const struct agp_bridge_driver intel_820_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001808 .owner = THIS_MODULE,
1809 .aperture_sizes = intel_8xx_sizes,
1810 .size_type = U8_APER_SIZE,
1811 .num_aperture_sizes = 7,
1812 .configure = intel_820_configure,
1813 .fetch_size = intel_8xx_fetch_size,
1814 .cleanup = intel_820_cleanup,
1815 .tlb_flush = intel_820_tlbflush,
1816 .mask_memory = agp_generic_mask_memory,
1817 .masks = intel_generic_masks,
1818 .agp_enable = agp_generic_enable,
1819 .cache_flush = global_cache_flush,
1820 .create_gatt_table = agp_generic_create_gatt_table,
1821 .free_gatt_table = agp_generic_free_gatt_table,
1822 .insert_memory = agp_generic_insert_memory,
1823 .remove_memory = agp_generic_remove_memory,
1824 .alloc_by_type = agp_generic_alloc_by_type,
1825 .free_by_type = agp_generic_free_by_type,
1826 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001827 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001828 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001829 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001830 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001831};
1832
Dave Jonese5524f32007-02-22 18:41:28 -05001833static const struct agp_bridge_driver intel_830mp_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001834 .owner = THIS_MODULE,
1835 .aperture_sizes = intel_830mp_sizes,
1836 .size_type = U8_APER_SIZE,
1837 .num_aperture_sizes = 4,
1838 .configure = intel_830mp_configure,
1839 .fetch_size = intel_8xx_fetch_size,
1840 .cleanup = intel_8xx_cleanup,
1841 .tlb_flush = intel_8xx_tlbflush,
1842 .mask_memory = agp_generic_mask_memory,
1843 .masks = intel_generic_masks,
1844 .agp_enable = agp_generic_enable,
1845 .cache_flush = global_cache_flush,
1846 .create_gatt_table = agp_generic_create_gatt_table,
1847 .free_gatt_table = agp_generic_free_gatt_table,
1848 .insert_memory = agp_generic_insert_memory,
1849 .remove_memory = agp_generic_remove_memory,
1850 .alloc_by_type = agp_generic_alloc_by_type,
1851 .free_by_type = agp_generic_free_by_type,
1852 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001853 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001854 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001855 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001856 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001857};
1858
Dave Jonese5524f32007-02-22 18:41:28 -05001859static const struct agp_bridge_driver intel_840_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001860 .owner = THIS_MODULE,
1861 .aperture_sizes = intel_8xx_sizes,
1862 .size_type = U8_APER_SIZE,
1863 .num_aperture_sizes = 7,
1864 .configure = intel_840_configure,
1865 .fetch_size = intel_8xx_fetch_size,
1866 .cleanup = intel_8xx_cleanup,
1867 .tlb_flush = intel_8xx_tlbflush,
1868 .mask_memory = agp_generic_mask_memory,
1869 .masks = intel_generic_masks,
1870 .agp_enable = agp_generic_enable,
1871 .cache_flush = global_cache_flush,
1872 .create_gatt_table = agp_generic_create_gatt_table,
1873 .free_gatt_table = agp_generic_free_gatt_table,
1874 .insert_memory = agp_generic_insert_memory,
1875 .remove_memory = agp_generic_remove_memory,
1876 .alloc_by_type = agp_generic_alloc_by_type,
1877 .free_by_type = agp_generic_free_by_type,
1878 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001879 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001880 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001881 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001882 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001883};
1884
Dave Jonese5524f32007-02-22 18:41:28 -05001885static const struct agp_bridge_driver intel_845_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001886 .owner = THIS_MODULE,
1887 .aperture_sizes = intel_8xx_sizes,
1888 .size_type = U8_APER_SIZE,
1889 .num_aperture_sizes = 7,
1890 .configure = intel_845_configure,
1891 .fetch_size = intel_8xx_fetch_size,
1892 .cleanup = intel_8xx_cleanup,
1893 .tlb_flush = intel_8xx_tlbflush,
1894 .mask_memory = agp_generic_mask_memory,
1895 .masks = intel_generic_masks,
1896 .agp_enable = agp_generic_enable,
1897 .cache_flush = global_cache_flush,
1898 .create_gatt_table = agp_generic_create_gatt_table,
1899 .free_gatt_table = agp_generic_free_gatt_table,
1900 .insert_memory = agp_generic_insert_memory,
1901 .remove_memory = agp_generic_remove_memory,
1902 .alloc_by_type = agp_generic_alloc_by_type,
1903 .free_by_type = agp_generic_free_by_type,
1904 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001905 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001906 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001907 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001908 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Dave Airlie2162e6a2007-11-21 16:36:31 +10001909 .chipset_flush = intel_i830_chipset_flush,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001910};
1911
Dave Jonese5524f32007-02-22 18:41:28 -05001912static const struct agp_bridge_driver intel_850_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001913 .owner = THIS_MODULE,
1914 .aperture_sizes = intel_8xx_sizes,
1915 .size_type = U8_APER_SIZE,
1916 .num_aperture_sizes = 7,
1917 .configure = intel_850_configure,
1918 .fetch_size = intel_8xx_fetch_size,
1919 .cleanup = intel_8xx_cleanup,
1920 .tlb_flush = intel_8xx_tlbflush,
1921 .mask_memory = agp_generic_mask_memory,
1922 .masks = intel_generic_masks,
1923 .agp_enable = agp_generic_enable,
1924 .cache_flush = global_cache_flush,
1925 .create_gatt_table = agp_generic_create_gatt_table,
1926 .free_gatt_table = agp_generic_free_gatt_table,
1927 .insert_memory = agp_generic_insert_memory,
1928 .remove_memory = agp_generic_remove_memory,
1929 .alloc_by_type = agp_generic_alloc_by_type,
1930 .free_by_type = agp_generic_free_by_type,
1931 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001932 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001933 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001934 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001935 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001936};
1937
Dave Jonese5524f32007-02-22 18:41:28 -05001938static const struct agp_bridge_driver intel_860_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001939 .owner = THIS_MODULE,
1940 .aperture_sizes = intel_8xx_sizes,
1941 .size_type = U8_APER_SIZE,
1942 .num_aperture_sizes = 7,
1943 .configure = intel_860_configure,
1944 .fetch_size = intel_8xx_fetch_size,
1945 .cleanup = intel_8xx_cleanup,
1946 .tlb_flush = intel_8xx_tlbflush,
1947 .mask_memory = agp_generic_mask_memory,
1948 .masks = intel_generic_masks,
1949 .agp_enable = agp_generic_enable,
1950 .cache_flush = global_cache_flush,
1951 .create_gatt_table = agp_generic_create_gatt_table,
1952 .free_gatt_table = agp_generic_free_gatt_table,
1953 .insert_memory = agp_generic_insert_memory,
1954 .remove_memory = agp_generic_remove_memory,
1955 .alloc_by_type = agp_generic_alloc_by_type,
1956 .free_by_type = agp_generic_free_by_type,
1957 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001958 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001959 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001960 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001961 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001962};
1963
Dave Jonese5524f32007-02-22 18:41:28 -05001964static const struct agp_bridge_driver intel_915_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001965 .owner = THIS_MODULE,
1966 .aperture_sizes = intel_i830_sizes,
1967 .size_type = FIXED_APER_SIZE,
Dave Jonesc14635e2006-09-06 11:59:35 -04001968 .num_aperture_sizes = 4,
Joe Perchesc7258012008-03-26 14:10:02 -07001969 .needs_scratch_page = true,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001970 .configure = intel_i915_configure,
Eric Anholtc41e0de2006-12-19 12:57:24 -08001971 .fetch_size = intel_i9xx_fetch_size,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001972 .cleanup = intel_i915_cleanup,
1973 .tlb_flush = intel_i810_tlbflush,
1974 .mask_memory = intel_i810_mask_memory,
1975 .masks = intel_i810_masks,
1976 .agp_enable = intel_i810_agp_enable,
1977 .cache_flush = global_cache_flush,
1978 .create_gatt_table = intel_i915_create_gatt_table,
1979 .free_gatt_table = intel_i830_free_gatt_table,
1980 .insert_memory = intel_i915_insert_entries,
1981 .remove_memory = intel_i915_remove_entries,
1982 .alloc_by_type = intel_i830_alloc_by_type,
1983 .free_by_type = intel_i810_free_by_type,
1984 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08001985 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001986 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08001987 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01001988 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
Dave Airlie6c00a612007-10-29 18:06:10 +10001989 .chipset_flush = intel_i915_chipset_flush,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001990};
1991
Dave Jonese5524f32007-02-22 18:41:28 -05001992static const struct agp_bridge_driver intel_i965_driver = {
Dave Airlie62c96b92008-06-19 14:27:53 +10001993 .owner = THIS_MODULE,
1994 .aperture_sizes = intel_i830_sizes,
1995 .size_type = FIXED_APER_SIZE,
1996 .num_aperture_sizes = 4,
1997 .needs_scratch_page = true,
Dave Airlie0e480e52008-06-19 14:57:31 +10001998 .configure = intel_i915_configure,
1999 .fetch_size = intel_i9xx_fetch_size,
Dave Airlie62c96b92008-06-19 14:27:53 +10002000 .cleanup = intel_i915_cleanup,
2001 .tlb_flush = intel_i810_tlbflush,
2002 .mask_memory = intel_i965_mask_memory,
2003 .masks = intel_i810_masks,
2004 .agp_enable = intel_i810_agp_enable,
2005 .cache_flush = global_cache_flush,
2006 .create_gatt_table = intel_i965_create_gatt_table,
2007 .free_gatt_table = intel_i830_free_gatt_table,
2008 .insert_memory = intel_i915_insert_entries,
2009 .remove_memory = intel_i915_remove_entries,
2010 .alloc_by_type = intel_i830_alloc_by_type,
2011 .free_by_type = intel_i810_free_by_type,
2012 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08002013 .agp_alloc_pages = agp_generic_alloc_pages,
Dave Airlie62c96b92008-06-19 14:27:53 +10002014 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08002015 .agp_destroy_pages = agp_generic_destroy_pages,
Dave Airlie62c96b92008-06-19 14:27:53 +10002016 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
Dave Airlie6c00a612007-10-29 18:06:10 +10002017 .chipset_flush = intel_i915_chipset_flush,
Eric Anholt65c25aa2006-09-06 11:57:18 -04002018};
Linus Torvalds1da177e2005-04-16 15:20:36 -07002019
Dave Jonese5524f32007-02-22 18:41:28 -05002020static const struct agp_bridge_driver intel_7505_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002021 .owner = THIS_MODULE,
2022 .aperture_sizes = intel_8xx_sizes,
2023 .size_type = U8_APER_SIZE,
2024 .num_aperture_sizes = 7,
2025 .configure = intel_7505_configure,
2026 .fetch_size = intel_8xx_fetch_size,
2027 .cleanup = intel_8xx_cleanup,
2028 .tlb_flush = intel_8xx_tlbflush,
2029 .mask_memory = agp_generic_mask_memory,
2030 .masks = intel_generic_masks,
2031 .agp_enable = agp_generic_enable,
2032 .cache_flush = global_cache_flush,
2033 .create_gatt_table = agp_generic_create_gatt_table,
2034 .free_gatt_table = agp_generic_free_gatt_table,
2035 .insert_memory = agp_generic_insert_memory,
2036 .remove_memory = agp_generic_remove_memory,
2037 .alloc_by_type = agp_generic_alloc_by_type,
2038 .free_by_type = agp_generic_free_by_type,
2039 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08002040 .agp_alloc_pages = agp_generic_alloc_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002041 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08002042 .agp_destroy_pages = agp_generic_destroy_pages,
Thomas Hellstroma030ce42007-01-23 10:33:43 +01002043 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002044};
2045
Wang Zhenyu874808c62007-06-06 11:16:25 +08002046static const struct agp_bridge_driver intel_g33_driver = {
Dave Airlie62c96b92008-06-19 14:27:53 +10002047 .owner = THIS_MODULE,
2048 .aperture_sizes = intel_i830_sizes,
2049 .size_type = FIXED_APER_SIZE,
2050 .num_aperture_sizes = 4,
2051 .needs_scratch_page = true,
2052 .configure = intel_i915_configure,
2053 .fetch_size = intel_i9xx_fetch_size,
2054 .cleanup = intel_i915_cleanup,
2055 .tlb_flush = intel_i810_tlbflush,
2056 .mask_memory = intel_i965_mask_memory,
2057 .masks = intel_i810_masks,
2058 .agp_enable = intel_i810_agp_enable,
2059 .cache_flush = global_cache_flush,
2060 .create_gatt_table = intel_i915_create_gatt_table,
2061 .free_gatt_table = intel_i830_free_gatt_table,
2062 .insert_memory = intel_i915_insert_entries,
2063 .remove_memory = intel_i915_remove_entries,
2064 .alloc_by_type = intel_i830_alloc_by_type,
2065 .free_by_type = intel_i810_free_by_type,
2066 .agp_alloc_page = agp_generic_alloc_page,
Shaohua Li37acee12008-08-21 10:46:11 +08002067 .agp_alloc_pages = agp_generic_alloc_pages,
Dave Airlie62c96b92008-06-19 14:27:53 +10002068 .agp_destroy_page = agp_generic_destroy_page,
Shaohua Libd079282008-08-21 10:46:17 +08002069 .agp_destroy_pages = agp_generic_destroy_pages,
Dave Airlie62c96b92008-06-19 14:27:53 +10002070 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
Dave Airlie6c00a612007-10-29 18:06:10 +10002071 .chipset_flush = intel_i915_chipset_flush,
Wang Zhenyu874808c62007-06-06 11:16:25 +08002072};
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002073
2074static int find_gmch(u16 device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002075{
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002076 struct pci_dev *gmch_device;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002077
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002078 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2079 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2080 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
Dave Airlief011ae72008-01-25 11:23:04 +10002081 device, gmch_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002082 }
2083
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002084 if (!gmch_device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002085 return 0;
2086
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002087 intel_private.pcidev = gmch_device;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002088 return 1;
2089}
2090
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002091/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
2092 * driver and gmch_driver must be non-null, and find_gmch will determine
2093 * which one should be used if a gmch_chip_id is present.
2094 */
2095static const struct intel_driver_description {
2096 unsigned int chip_id;
2097 unsigned int gmch_chip_id;
Wang Zhenyu88889852007-06-14 10:01:04 +08002098 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002099 char *name;
2100 const struct agp_bridge_driver *driver;
2101 const struct agp_bridge_driver *gmch_driver;
2102} intel_agp_chipsets[] = {
Wang Zhenyu88889852007-06-14 10:01:04 +08002103 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2104 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2105 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2106 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002107 NULL, &intel_810_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002108 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002109 NULL, &intel_810_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002110 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002111 NULL, &intel_810_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002112 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2113 &intel_815_driver, &intel_810_driver },
2114 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2115 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2116 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002117 &intel_830mp_driver, &intel_830_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002118 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2119 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2120 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002121 &intel_845_driver, &intel_830_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002122 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2123 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2124 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002125 &intel_845_driver, &intel_830_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002126 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2127 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002128 &intel_845_driver, &intel_830_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002129 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
Carlos Martíne914a362008-01-24 10:34:09 +10002130 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2131 NULL, &intel_915_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002132 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002133 NULL, &intel_915_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002134 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002135 NULL, &intel_915_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002136 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002137 NULL, &intel_915_driver },
Zhenyu Wangdde47872007-07-26 09:18:09 +08002138 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002139 NULL, &intel_915_driver },
Zhenyu Wangdde47872007-07-26 09:18:09 +08002140 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002141 NULL, &intel_915_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002142 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002143 NULL, &intel_i965_driver },
Zhenyu Wang9119f852008-01-23 15:49:26 +10002144 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002145 NULL, &intel_i965_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002146 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002147 NULL, &intel_i965_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002148 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002149 NULL, &intel_i965_driver },
Zhenyu Wangdde47872007-07-26 09:18:09 +08002150 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002151 NULL, &intel_i965_driver },
Zhenyu Wangdde47872007-07-26 09:18:09 +08002152 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002153 NULL, &intel_i965_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002154 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2155 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2156 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002157 NULL, &intel_g33_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002158 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002159 NULL, &intel_g33_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002160 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
Wang Zhenyu47d46372007-06-21 13:43:18 +08002161 NULL, &intel_g33_driver },
Zhenyu Wang99d32bd2008-07-30 12:26:50 -07002162 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
Eric Anholtb854b2a2008-12-22 18:56:27 -08002163 "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10002164 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2165 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2166 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2167 "Q45/Q43", NULL, &intel_i965_driver },
2168 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2169 "G45/G43", NULL, &intel_i965_driver },
Zhenyu Wanga50ccc62008-11-17 14:39:00 +08002170 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2171 "G41", NULL, &intel_i965_driver },
Wang Zhenyu88889852007-06-14 10:01:04 +08002172 { 0, 0, 0, NULL, NULL, NULL }
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002173};
2174
Linus Torvalds1da177e2005-04-16 15:20:36 -07002175static int __devinit agp_intel_probe(struct pci_dev *pdev,
2176 const struct pci_device_id *ent)
2177{
2178 struct agp_bridge_data *bridge;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002179 u8 cap_ptr = 0;
2180 struct resource *r;
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002181 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002182
2183 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2184
2185 bridge = agp_alloc_bridge();
2186 if (!bridge)
2187 return -ENOMEM;
2188
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002189 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2190 /* In case that multiple models of gfx chip may
2191 stand on same host bridge type, this can be
2192 sure we detect the right IGD. */
Wang Zhenyu88889852007-06-14 10:01:04 +08002193 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2194 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2195 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2196 bridge->driver =
2197 intel_agp_chipsets[i].gmch_driver;
2198 break;
2199 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2200 continue;
2201 } else {
2202 bridge->driver = intel_agp_chipsets[i].driver;
2203 break;
2204 }
2205 }
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002206 }
2207
2208 if (intel_agp_chipsets[i].name == NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002209 if (cap_ptr)
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002210 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2211 pdev->vendor, pdev->device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002212 agp_put_bridge(bridge);
2213 return -ENODEV;
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002214 }
2215
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002216 if (bridge->driver == NULL) {
Wang Zhenyu47d46372007-06-21 13:43:18 +08002217 /* bridge has no AGP and no IGD detected */
2218 if (cap_ptr)
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002219 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2220 intel_agp_chipsets[i].gmch_chip_id);
Wang Zhenyu9614ece2007-05-30 09:45:58 +08002221 agp_put_bridge(bridge);
2222 return -ENODEV;
Dave Airlief011ae72008-01-25 11:23:04 +10002223 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002224
2225 bridge->dev = pdev;
2226 bridge->capndx = cap_ptr;
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08002227 bridge->dev_private_data = &intel_private;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002228
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002229 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002230
2231 /*
2232 * The following fixes the case where the BIOS has "forgotten" to
2233 * provide an address range for the GART.
2234 * 20030610 - hamish@zot.org
2235 */
2236 r = &pdev->resource[0];
2237 if (!r->start && r->end) {
Dave Jones6a92a4e2006-02-28 00:54:25 -05002238 if (pci_assign_resource(pdev, 0)) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002239 dev_err(&pdev->dev, "can't assign resource 0\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002240 agp_put_bridge(bridge);
2241 return -ENODEV;
2242 }
2243 }
2244
2245 /*
2246 * If the device has not been properly setup, the following will catch
2247 * the problem and should stop the system from crashing.
2248 * 20030610 - hamish@zot.org
2249 */
2250 if (pci_enable_device(pdev)) {
Bjorn Helgaase3cf6952008-07-30 12:26:51 -07002251 dev_err(&pdev->dev, "can't enable PCI device\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002252 agp_put_bridge(bridge);
2253 return -ENODEV;
2254 }
2255
2256 /* Fill in the mode register */
2257 if (cap_ptr) {
2258 pci_read_config_dword(pdev,
2259 bridge->capndx+PCI_AGP_STATUS,
2260 &bridge->mode);
2261 }
2262
2263 pci_set_drvdata(pdev, bridge);
2264 return agp_add_bridge(bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002265}
2266
2267static void __devexit agp_intel_remove(struct pci_dev *pdev)
2268{
2269 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2270
2271 agp_remove_bridge(bridge);
2272
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08002273 if (intel_private.pcidev)
2274 pci_dev_put(intel_private.pcidev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002275
2276 agp_put_bridge(bridge);
2277}
2278
Alexey Dobriyan85be7d62006-08-12 02:02:02 +04002279#ifdef CONFIG_PM
Linus Torvalds1da177e2005-04-16 15:20:36 -07002280static int agp_intel_resume(struct pci_dev *pdev)
2281{
2282 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
Keith Packarda8c84df2008-07-31 15:48:07 +10002283 int ret_val;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002284
2285 pci_restore_state(pdev);
2286
Wang Zhenyu4b953202007-01-17 11:07:54 +08002287 /* We should restore our graphics device's config space,
2288 * as host bridge (00:00) resumes before graphics device (02:00),
2289 * then our access to its pci space can work right.
2290 */
Wang Zhenyuc4ca8812007-05-30 09:40:46 +08002291 if (intel_private.pcidev)
2292 pci_restore_state(intel_private.pcidev);
Wang Zhenyu4b953202007-01-17 11:07:54 +08002293
Linus Torvalds1da177e2005-04-16 15:20:36 -07002294 if (bridge->driver == &intel_generic_driver)
2295 intel_configure();
2296 else if (bridge->driver == &intel_850_driver)
2297 intel_850_configure();
2298 else if (bridge->driver == &intel_845_driver)
2299 intel_845_configure();
2300 else if (bridge->driver == &intel_830mp_driver)
2301 intel_830mp_configure();
2302 else if (bridge->driver == &intel_915_driver)
2303 intel_i915_configure();
2304 else if (bridge->driver == &intel_830_driver)
2305 intel_i830_configure();
2306 else if (bridge->driver == &intel_810_driver)
2307 intel_i810_configure();
Dave Jones08da3f42006-09-10 21:09:26 -04002308 else if (bridge->driver == &intel_i965_driver)
2309 intel_i915_configure();
Linus Torvalds1da177e2005-04-16 15:20:36 -07002310
Keith Packarda8c84df2008-07-31 15:48:07 +10002311 ret_val = agp_rebind_memory();
2312 if (ret_val != 0)
2313 return ret_val;
2314
Linus Torvalds1da177e2005-04-16 15:20:36 -07002315 return 0;
2316}
Alexey Dobriyan85be7d62006-08-12 02:02:02 +04002317#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002318
2319static struct pci_device_id agp_intel_pci_table[] = {
2320#define ID(x) \
2321 { \
2322 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2323 .class_mask = ~0, \
2324 .vendor = PCI_VENDOR_ID_INTEL, \
2325 .device = x, \
2326 .subvendor = PCI_ANY_ID, \
2327 .subdevice = PCI_ANY_ID, \
2328 }
2329 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2330 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2331 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2332 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2333 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2334 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2335 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2336 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2337 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2338 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2339 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2340 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2341 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2342 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2343 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2344 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2345 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2346 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2347 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2348 ID(PCI_DEVICE_ID_INTEL_7505_0),
2349 ID(PCI_DEVICE_ID_INTEL_7205_0),
Carlos Martíne914a362008-01-24 10:34:09 +10002350 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
Linus Torvalds1da177e2005-04-16 15:20:36 -07002351 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2352 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
Alan Hourihaned0de98f2005-05-31 19:50:49 +01002353 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
Alan Hourihane3b0e8ea2006-01-19 14:08:40 +00002354 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
Zhenyu Wangdde47872007-07-26 09:18:09 +08002355 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
Eric Anholt65c25aa2006-09-06 11:57:18 -04002356 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
Zhenyu Wang9119f852008-01-23 15:49:26 +10002357 ID(PCI_DEVICE_ID_INTEL_82G35_HB),
Eric Anholt65c25aa2006-09-06 11:57:18 -04002358 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2359 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
Wang Zhenyu4598af32007-04-09 08:51:36 +08002360 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
Zhenyu Wangdde47872007-07-26 09:18:09 +08002361 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
Wang Zhenyu874808c62007-06-06 11:16:25 +08002362 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2363 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2364 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
Zhenyu Wang99d32bd2008-07-30 12:26:50 -07002365 ID(PCI_DEVICE_ID_INTEL_GM45_HB),
Zhenyu Wang25ce77a2008-06-19 14:17:58 +10002366 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2367 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2368 ID(PCI_DEVICE_ID_INTEL_G45_HB),
Zhenyu Wanga50ccc62008-11-17 14:39:00 +08002369 ID(PCI_DEVICE_ID_INTEL_G41_HB),
Linus Torvalds1da177e2005-04-16 15:20:36 -07002370 { }
2371};
2372
2373MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2374
2375static struct pci_driver agp_intel_pci_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002376 .name = "agpgart-intel",
2377 .id_table = agp_intel_pci_table,
2378 .probe = agp_intel_probe,
2379 .remove = __devexit_p(agp_intel_remove),
Alexey Dobriyan85be7d62006-08-12 02:02:02 +04002380#ifdef CONFIG_PM
Linus Torvalds1da177e2005-04-16 15:20:36 -07002381 .resume = agp_intel_resume,
Alexey Dobriyan85be7d62006-08-12 02:02:02 +04002382#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002383};
2384
2385static int __init agp_intel_init(void)
2386{
2387 if (agp_off)
2388 return -EINVAL;
2389 return pci_register_driver(&agp_intel_pci_driver);
2390}
2391
2392static void __exit agp_intel_cleanup(void)
2393{
2394 pci_unregister_driver(&agp_intel_pci_driver);
2395}
2396
2397module_init(agp_intel_init);
2398module_exit(agp_intel_cleanup);
2399
Dave Jonesf4432c52008-10-20 13:31:45 -04002400MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002401MODULE_LICENSE("GPL and additional rights");