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Yoshinori Sato9d4436a2006-11-05 15:40:13 +09001/*
2 * SH7206 Setup
3 *
4 * Copyright (C) 2006 Yoshinori Sato
Paul Mundtf858abb2009-03-06 18:34:15 +09005 * Copyright (C) 2009 Paul Mundt
Yoshinori Sato9d4436a2006-11-05 15:40:13 +09006 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/serial.h>
Paul Mundt96de1a82008-02-26 14:52:45 +090014#include <linux/serial_sci.h>
Paul Mundt46a12f72009-05-03 17:57:17 +090015#include <linux/sh_timer.h>
Magnus Damm698aa992009-04-30 04:08:18 +000016#include <linux/io.h>
Yoshinori Sato9d4436a2006-11-05 15:40:13 +090017
Magnus Damm2eb03032007-08-17 00:53:41 +090018enum {
19 UNUSED = 0,
20
21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
24 ADC_ADI0, ADC_ADI1,
Magnus Damm2eb03032007-08-17 00:53:41 +090025
Paul Mundtf858abb2009-03-06 18:34:15 +090026 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
27
Magnus Damm2eb03032007-08-17 00:53:41 +090028 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
29 MTU3_ABCD, MTU4_ABCD, MTU5, POE2_12, MTU3S_ABCD, MTU4S_ABCD, MTU5S,
Paul Mundtf858abb2009-03-06 18:34:15 +090030 IIC3,
31
32 CMT0, CMT1, BSC, WDT,
33
34 MTU2_TCI3V, MTU2_TCI4V, MTU2S_TCI3V, MTU2S_TCI4V,
35
36 POE2_OEI3,
37
38 SCIF0, SCIF1, SCIF2, SCIF3,
39
40 /* interrupt groups */
41 PINT,
Magnus Damm2eb03032007-08-17 00:53:41 +090042};
43
44static struct intc_vect vectors[] __initdata = {
45 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
46 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
47 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
48 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
49 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
50 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
51 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
52 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
53 INTC_IRQ(ADC_ADI0, 92), INTC_IRQ(ADC_ADI1, 96),
Paul Mundtf858abb2009-03-06 18:34:15 +090054 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
55 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
56 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
57 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
58 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
59 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
60 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
61 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
Magnus Damm2eb03032007-08-17 00:53:41 +090062 INTC_IRQ(CMT0, 140), INTC_IRQ(CMT1, 144),
63 INTC_IRQ(BSC, 148), INTC_IRQ(WDT, 152),
Paul Mundtf858abb2009-03-06 18:34:15 +090064 INTC_IRQ(MTU0_ABCD, 156), INTC_IRQ(MTU0_ABCD, 157),
65 INTC_IRQ(MTU0_ABCD, 158), INTC_IRQ(MTU0_ABCD, 159),
66 INTC_IRQ(MTU0_VEF, 160), INTC_IRQ(MTU0_VEF, 161),
67 INTC_IRQ(MTU0_VEF, 162),
68 INTC_IRQ(MTU1_AB, 164), INTC_IRQ(MTU1_AB, 165),
69 INTC_IRQ(MTU1_VU, 168), INTC_IRQ(MTU1_VU, 169),
70 INTC_IRQ(MTU2_AB, 172), INTC_IRQ(MTU2_AB, 173),
71 INTC_IRQ(MTU2_VU, 176), INTC_IRQ(MTU2_VU, 177),
72 INTC_IRQ(MTU3_ABCD, 180), INTC_IRQ(MTU3_ABCD, 181),
73 INTC_IRQ(MTU3_ABCD, 182), INTC_IRQ(MTU3_ABCD, 183),
Magnus Damm2eb03032007-08-17 00:53:41 +090074 INTC_IRQ(MTU2_TCI3V, 184),
Paul Mundtf858abb2009-03-06 18:34:15 +090075 INTC_IRQ(MTU4_ABCD, 188), INTC_IRQ(MTU4_ABCD, 189),
76 INTC_IRQ(MTU4_ABCD, 190), INTC_IRQ(MTU4_ABCD, 191),
Magnus Damm2eb03032007-08-17 00:53:41 +090077 INTC_IRQ(MTU2_TCI4V, 192),
Paul Mundtf858abb2009-03-06 18:34:15 +090078 INTC_IRQ(MTU5, 196), INTC_IRQ(MTU5, 197),
79 INTC_IRQ(MTU5, 198),
80 INTC_IRQ(POE2_12, 200), INTC_IRQ(POE2_12, 201),
81 INTC_IRQ(MTU3S_ABCD, 204), INTC_IRQ(MTU3S_ABCD, 205),
82 INTC_IRQ(MTU3S_ABCD, 206), INTC_IRQ(MTU3S_ABCD, 207),
Magnus Damm2eb03032007-08-17 00:53:41 +090083 INTC_IRQ(MTU2S_TCI3V, 208),
Paul Mundtf858abb2009-03-06 18:34:15 +090084 INTC_IRQ(MTU4S_ABCD, 212), INTC_IRQ(MTU4S_ABCD, 213),
85 INTC_IRQ(MTU4S_ABCD, 214), INTC_IRQ(MTU4S_ABCD, 215),
Magnus Damm2eb03032007-08-17 00:53:41 +090086 INTC_IRQ(MTU2S_TCI4V, 216),
Paul Mundtf858abb2009-03-06 18:34:15 +090087 INTC_IRQ(MTU5S, 220), INTC_IRQ(MTU5S, 221),
88 INTC_IRQ(MTU5S, 222),
Magnus Damm2eb03032007-08-17 00:53:41 +090089 INTC_IRQ(POE2_OEI3, 224),
Paul Mundtf858abb2009-03-06 18:34:15 +090090 INTC_IRQ(IIC3, 228), INTC_IRQ(IIC3, 229),
91 INTC_IRQ(IIC3, 230), INTC_IRQ(IIC3, 231),
92 INTC_IRQ(IIC3, 232),
93 INTC_IRQ(SCIF0, 240), INTC_IRQ(SCIF0, 241),
94 INTC_IRQ(SCIF0, 242), INTC_IRQ(SCIF0, 243),
95 INTC_IRQ(SCIF1, 244), INTC_IRQ(SCIF1, 245),
96 INTC_IRQ(SCIF1, 246), INTC_IRQ(SCIF1, 247),
97 INTC_IRQ(SCIF2, 248), INTC_IRQ(SCIF2, 249),
98 INTC_IRQ(SCIF2, 250), INTC_IRQ(SCIF2, 251),
99 INTC_IRQ(SCIF3, 252), INTC_IRQ(SCIF3, 253),
100 INTC_IRQ(SCIF3, 254), INTC_IRQ(SCIF3, 255),
Magnus Damm2eb03032007-08-17 00:53:41 +0900101};
102
103static struct intc_group groups[] __initdata = {
104 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
105 PINT4, PINT5, PINT6, PINT7),
Magnus Damm2eb03032007-08-17 00:53:41 +0900106};
107
108static struct intc_prio_reg prio_registers[] __initdata = {
109 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
110 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
111 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI0, ADC_ADI1 } },
112 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
113 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
114 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { CMT0, CMT1, BSC, WDT } },
115 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { MTU0_ABCD, MTU0_VEF,
116 MTU1_AB, MTU1_VU } },
117 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU2_AB, MTU2_VU,
118 MTU3_ABCD, MTU2_TCI3V } },
119 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU4_ABCD, MTU2_TCI4V,
120 MTU5, POE2_12 } },
121 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU3S_ABCD, MTU2S_TCI3V,
122 MTU4S_ABCD, MTU2S_TCI4V } },
123 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU5S, POE2_OEI3, IIC3, 0 } },
124 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
125};
126
127static struct intc_mask_reg mask_registers[] __initdata = {
128 { 0xfffe0808, 0, 16, /* PINTER */
129 { 0, 0, 0, 0, 0, 0, 0, 0,
130 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
131};
132
133static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups,
Magnus Damm7f3edee2008-01-10 14:08:55 +0900134 mask_registers, prio_registers, NULL);
Magnus Damm2eb03032007-08-17 00:53:41 +0900135
Magnus Dammbe091d22009-12-14 12:29:56 +0000136static struct plat_sci_port scif0_platform_data = {
137 .mapbase = 0xfffe8000,
138 .flags = UPF_BOOT_AUTOCONF,
139 .type = PORT_SCIF,
140 .irqs = { 240, 240, 240, 240 },
Yoshinori Sato9d4436a2006-11-05 15:40:13 +0900141};
142
Magnus Dammbe091d22009-12-14 12:29:56 +0000143static struct platform_device scif0_device = {
Yoshinori Sato9d4436a2006-11-05 15:40:13 +0900144 .name = "sh-sci",
Magnus Dammbe091d22009-12-14 12:29:56 +0000145 .id = 0,
Yoshinori Sato9d4436a2006-11-05 15:40:13 +0900146 .dev = {
Magnus Dammbe091d22009-12-14 12:29:56 +0000147 .platform_data = &scif0_platform_data,
148 },
149};
150
151static struct plat_sci_port scif1_platform_data = {
152 .mapbase = 0xfffe8800,
153 .flags = UPF_BOOT_AUTOCONF,
154 .type = PORT_SCIF,
155 .irqs = { 244, 244, 244, 244 },
156};
157
158static struct platform_device scif1_device = {
159 .name = "sh-sci",
160 .id = 1,
161 .dev = {
162 .platform_data = &scif1_platform_data,
163 },
164};
165
166static struct plat_sci_port scif2_platform_data = {
167 .mapbase = 0xfffe9000,
168 .flags = UPF_BOOT_AUTOCONF,
169 .type = PORT_SCIF,
170 .irqs = { 248, 248, 248, 248 },
171};
172
173static struct platform_device scif2_device = {
174 .name = "sh-sci",
175 .id = 2,
176 .dev = {
177 .platform_data = &scif2_platform_data,
178 },
179};
180
181static struct plat_sci_port scif3_platform_data = {
182 .mapbase = 0xfffe9800,
183 .flags = UPF_BOOT_AUTOCONF,
184 .type = PORT_SCIF,
185 .irqs = { 252, 252, 252, 252 },
186};
187
188static struct platform_device scif3_device = {
189 .name = "sh-sci",
190 .id = 3,
191 .dev = {
192 .platform_data = &scif3_platform_data,
Yoshinori Sato9d4436a2006-11-05 15:40:13 +0900193 },
194};
195
Paul Mundt46a12f72009-05-03 17:57:17 +0900196static struct sh_timer_config cmt0_platform_data = {
Magnus Damm698aa992009-04-30 04:08:18 +0000197 .channel_offset = 0x02,
198 .timer_bit = 0,
Magnus Damm698aa992009-04-30 04:08:18 +0000199 .clockevent_rating = 125,
200 .clocksource_rating = 0, /* disabled due to code generation issues */
201};
202
203static struct resource cmt0_resources[] = {
204 [0] = {
Magnus Damm698aa992009-04-30 04:08:18 +0000205 .start = 0xfffec002,
206 .end = 0xfffec007,
207 .flags = IORESOURCE_MEM,
208 },
209 [1] = {
210 .start = 140,
211 .flags = IORESOURCE_IRQ,
212 },
213};
214
215static struct platform_device cmt0_device = {
216 .name = "sh_cmt",
217 .id = 0,
218 .dev = {
219 .platform_data = &cmt0_platform_data,
220 },
221 .resource = cmt0_resources,
222 .num_resources = ARRAY_SIZE(cmt0_resources),
223};
224
Paul Mundt46a12f72009-05-03 17:57:17 +0900225static struct sh_timer_config cmt1_platform_data = {
Magnus Damm698aa992009-04-30 04:08:18 +0000226 .channel_offset = 0x08,
227 .timer_bit = 1,
Magnus Damm698aa992009-04-30 04:08:18 +0000228 .clockevent_rating = 125,
229 .clocksource_rating = 0, /* disabled due to code generation issues */
230};
231
232static struct resource cmt1_resources[] = {
233 [0] = {
Magnus Damm698aa992009-04-30 04:08:18 +0000234 .start = 0xfffec008,
235 .end = 0xfffec00d,
236 .flags = IORESOURCE_MEM,
237 },
238 [1] = {
239 .start = 144,
240 .flags = IORESOURCE_IRQ,
241 },
242};
243
244static struct platform_device cmt1_device = {
245 .name = "sh_cmt",
246 .id = 1,
247 .dev = {
248 .platform_data = &cmt1_platform_data,
249 },
250 .resource = cmt1_resources,
251 .num_resources = ARRAY_SIZE(cmt1_resources),
252};
253
Paul Mundt46a12f72009-05-03 17:57:17 +0900254static struct sh_timer_config mtu2_0_platform_data = {
Magnus Dammda107c62009-04-30 07:06:26 +0000255 .channel_offset = -0x80,
256 .timer_bit = 0,
Magnus Dammda107c62009-04-30 07:06:26 +0000257 .clockevent_rating = 200,
258};
259
260static struct resource mtu2_0_resources[] = {
261 [0] = {
Magnus Dammda107c62009-04-30 07:06:26 +0000262 .start = 0xfffe4300,
263 .end = 0xfffe4326,
264 .flags = IORESOURCE_MEM,
265 },
266 [1] = {
267 .start = 156,
268 .flags = IORESOURCE_IRQ,
269 },
270};
271
272static struct platform_device mtu2_0_device = {
273 .name = "sh_mtu2",
274 .id = 0,
275 .dev = {
276 .platform_data = &mtu2_0_platform_data,
277 },
278 .resource = mtu2_0_resources,
279 .num_resources = ARRAY_SIZE(mtu2_0_resources),
280};
281
Paul Mundt46a12f72009-05-03 17:57:17 +0900282static struct sh_timer_config mtu2_1_platform_data = {
Magnus Dammda107c62009-04-30 07:06:26 +0000283 .channel_offset = -0x100,
284 .timer_bit = 1,
Magnus Dammda107c62009-04-30 07:06:26 +0000285 .clockevent_rating = 200,
286};
287
288static struct resource mtu2_1_resources[] = {
289 [0] = {
Magnus Dammda107c62009-04-30 07:06:26 +0000290 .start = 0xfffe4380,
291 .end = 0xfffe4390,
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
295 .start = 164,
296 .flags = IORESOURCE_IRQ,
297 },
298};
299
300static struct platform_device mtu2_1_device = {
301 .name = "sh_mtu2",
302 .id = 1,
303 .dev = {
304 .platform_data = &mtu2_1_platform_data,
305 },
306 .resource = mtu2_1_resources,
307 .num_resources = ARRAY_SIZE(mtu2_1_resources),
308};
309
Paul Mundt46a12f72009-05-03 17:57:17 +0900310static struct sh_timer_config mtu2_2_platform_data = {
Magnus Dammda107c62009-04-30 07:06:26 +0000311 .channel_offset = 0x80,
312 .timer_bit = 2,
Magnus Dammda107c62009-04-30 07:06:26 +0000313 .clockevent_rating = 200,
314};
315
316static struct resource mtu2_2_resources[] = {
317 [0] = {
Magnus Dammda107c62009-04-30 07:06:26 +0000318 .start = 0xfffe4000,
319 .end = 0xfffe400a,
320 .flags = IORESOURCE_MEM,
321 },
322 [1] = {
323 .start = 180,
324 .flags = IORESOURCE_IRQ,
325 },
326};
327
328static struct platform_device mtu2_2_device = {
329 .name = "sh_mtu2",
330 .id = 2,
331 .dev = {
332 .platform_data = &mtu2_2_platform_data,
333 },
334 .resource = mtu2_2_resources,
335 .num_resources = ARRAY_SIZE(mtu2_2_resources),
336};
337
Yoshinori Sato9d4436a2006-11-05 15:40:13 +0900338static struct platform_device *sh7206_devices[] __initdata = {
Magnus Dammbe091d22009-12-14 12:29:56 +0000339 &scif0_device,
340 &scif1_device,
341 &scif2_device,
342 &scif3_device,
Magnus Damm698aa992009-04-30 04:08:18 +0000343 &cmt0_device,
344 &cmt1_device,
Magnus Dammda107c62009-04-30 07:06:26 +0000345 &mtu2_0_device,
346 &mtu2_1_device,
347 &mtu2_2_device,
Yoshinori Sato9d4436a2006-11-05 15:40:13 +0900348};
349
350static int __init sh7206_devices_setup(void)
351{
352 return platform_add_devices(sh7206_devices,
353 ARRAY_SIZE(sh7206_devices));
354}
Magnus Dammba9a6332009-07-22 15:14:29 +0000355arch_initcall(sh7206_devices_setup);
Yoshinori Sato780a1562006-12-07 18:01:23 +0900356
Magnus Damm90015c82007-07-18 17:57:34 +0900357void __init plat_irq_setup(void)
Yoshinori Sato780a1562006-12-07 18:01:23 +0900358{
Magnus Damm2eb03032007-08-17 00:53:41 +0900359 register_intc_controller(&intc_desc);
Yoshinori Sato780a1562006-12-07 18:01:23 +0900360}
Magnus Damm698aa992009-04-30 04:08:18 +0000361
362static struct platform_device *sh7206_early_devices[] __initdata = {
Magnus Dammbe091d22009-12-14 12:29:56 +0000363 &scif0_device,
364 &scif1_device,
365 &scif2_device,
366 &scif3_device,
Magnus Damm698aa992009-04-30 04:08:18 +0000367 &cmt0_device,
368 &cmt1_device,
Magnus Dammda107c62009-04-30 07:06:26 +0000369 &mtu2_0_device,
370 &mtu2_1_device,
371 &mtu2_2_device,
Magnus Damm698aa992009-04-30 04:08:18 +0000372};
373
Magnus Dammda107c62009-04-30 07:06:26 +0000374#define STBCR3 0xfffe0408
Magnus Damm698aa992009-04-30 04:08:18 +0000375#define STBCR4 0xfffe040c
376
377void __init plat_early_device_setup(void)
378{
379 /* enable CMT clock */
380 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
381
Magnus Dammda107c62009-04-30 07:06:26 +0000382 /* enable MTU2 clock */
383 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
384
Magnus Damm698aa992009-04-30 04:08:18 +0000385 early_platform_add_devices(sh7206_early_devices,
386 ARRAY_SIZE(sh7206_early_devices));
387}