blob: 790ef0d87e129f90b5cd83b617dc2b23000a7219 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001#include <linux/module.h>
2#include <linux/smp.h>
3#include <linux/time.h>
4#include <linux/errno.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -08005#include <linux/timex.h>
Tony Luck0aa366f2007-07-20 11:22:30 -07006#include <linux/clocksource.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07007#include <asm/io.h>
8
9/* IBM Summit (EXA) Cyclone counter code*/
10#define CYCLONE_CBAR_ADDR 0xFEB00CD0
11#define CYCLONE_PMCC_OFFSET 0x51A0
12#define CYCLONE_MPMC_OFFSET 0x51D0
13#define CYCLONE_MPCS_OFFSET 0x51A8
14#define CYCLONE_TIMER_FREQ 100000000
15
16int use_cyclone;
17void __init cyclone_setup(void)
18{
19 use_cyclone = 1;
20}
21
Tony Luck0aa366f2007-07-20 11:22:30 -070022static void __iomem *cyclone_mc;
Linus Torvalds1da177e2005-04-16 15:20:36 -070023
Tony Luck0aa366f2007-07-20 11:22:30 -070024static cycle_t read_cyclone(void)
25{
26 return (cycle_t)readq((void __iomem *)cyclone_mc);
27}
28
29static struct clocksource clocksource_cyclone = {
30 .name = "cyclone",
31 .rating = 300,
32 .read = read_cyclone,
33 .mask = (1LL << 40) - 1,
34 .mult = 0, /*to be caluclated*/
35 .shift = 16,
36 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
Linus Torvalds1da177e2005-04-16 15:20:36 -070037};
38
39int __init init_cyclone_clock(void)
40{
Al Viro6aa8b042007-07-26 17:34:59 +010041 u64 __iomem *reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -070042 u64 base; /* saved cyclone base address */
43 u64 offset; /* offset from pageaddr to cyclone_timer register */
44 int i;
Al Viro6aa8b042007-07-26 17:34:59 +010045 u32 __iomem *cyclone_timer; /* Cyclone MPMC0 register */
Linus Torvalds1da177e2005-04-16 15:20:36 -070046
47 if (!use_cyclone)
Bjorn Helgaas6c5e6212006-03-03 15:33:47 -070048 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070049
50 printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");
51
52 /* find base address */
53 offset = (CYCLONE_CBAR_ADDR);
Al Viro6aa8b042007-07-26 17:34:59 +010054 reg = ioremap_nocache(offset, sizeof(u64));
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 if(!reg){
Tony Luck0aa366f2007-07-20 11:22:30 -070056 printk(KERN_ERR "Summit chipset: Could not find valid CBAR"
57 " register.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070058 use_cyclone = 0;
59 return -ENODEV;
60 }
61 base = readq(reg);
62 if(!base){
Tony Luck0aa366f2007-07-20 11:22:30 -070063 printk(KERN_ERR "Summit chipset: Could not find valid CBAR"
64 " value.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070065 use_cyclone = 0;
66 return -ENODEV;
67 }
68 iounmap(reg);
69
70 /* setup PMCC */
71 offset = (base + CYCLONE_PMCC_OFFSET);
Al Viro6aa8b042007-07-26 17:34:59 +010072 reg = ioremap_nocache(offset, sizeof(u64));
Linus Torvalds1da177e2005-04-16 15:20:36 -070073 if(!reg){
Tony Luck0aa366f2007-07-20 11:22:30 -070074 printk(KERN_ERR "Summit chipset: Could not find valid PMCC"
75 " register.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 use_cyclone = 0;
77 return -ENODEV;
78 }
79 writel(0x00000001,reg);
80 iounmap(reg);
81
82 /* setup MPCS */
83 offset = (base + CYCLONE_MPCS_OFFSET);
Al Viro6aa8b042007-07-26 17:34:59 +010084 reg = ioremap_nocache(offset, sizeof(u64));
Linus Torvalds1da177e2005-04-16 15:20:36 -070085 if(!reg){
Tony Luck0aa366f2007-07-20 11:22:30 -070086 printk(KERN_ERR "Summit chipset: Could not find valid MPCS"
87 " register.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 use_cyclone = 0;
89 return -ENODEV;
90 }
91 writel(0x00000001,reg);
92 iounmap(reg);
93
94 /* map in cyclone_timer */
95 offset = (base + CYCLONE_MPMC_OFFSET);
Al Viro6aa8b042007-07-26 17:34:59 +010096 cyclone_timer = ioremap_nocache(offset, sizeof(u32));
Linus Torvalds1da177e2005-04-16 15:20:36 -070097 if(!cyclone_timer){
Tony Luck0aa366f2007-07-20 11:22:30 -070098 printk(KERN_ERR "Summit chipset: Could not find valid MPMC"
99 " register.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100 use_cyclone = 0;
101 return -ENODEV;
102 }
103
104 /*quick test to make sure its ticking*/
105 for(i=0; i<3; i++){
106 u32 old = readl(cyclone_timer);
107 int stall = 100;
108 while(stall--) barrier();
109 if(readl(cyclone_timer) == old){
Tony Luck0aa366f2007-07-20 11:22:30 -0700110 printk(KERN_ERR "Summit chipset: Counter not counting!"
111 " DISABLED\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112 iounmap(cyclone_timer);
Al Viro6aa8b042007-07-26 17:34:59 +0100113 cyclone_timer = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 use_cyclone = 0;
115 return -ENODEV;
116 }
117 }
118 /* initialize last tick */
Tony Luck0aa366f2007-07-20 11:22:30 -0700119 cyclone_mc = cyclone_timer;
120 clocksource_cyclone.fsys_mmio = cyclone_timer;
121 clocksource_cyclone.mult = clocksource_hz2mult(CYCLONE_TIMER_FREQ,
122 clocksource_cyclone.shift);
123 clocksource_register(&clocksource_cyclone);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124
125 return 0;
126}
127
128__initcall(init_cyclone_clock);