blob: d29e69c156f0a75a48cd0322e688c1b5d6f3add8 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/sh/kernel/cpu/init.c
3 *
4 * CPU init code
5 *
Paul Mundtffe1b4e2007-03-12 16:15:22 +09006 * Copyright (C) 2002 - 2007 Paul Mundt
Richard Curnowb638d0b2006-09-27 14:09:26 +09007 * Copyright (C) 2003 Richard Curnow
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/kernel.h>
Paul Mundtaec5e0e2006-12-25 09:51:47 +090015#include <linux/mm.h>
Paul Mundtcd012042007-12-10 15:50:28 +090016#include <linux/log2.h>
Paul Mundtaec5e0e2006-12-25 09:51:47 +090017#include <asm/mmu_context.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <asm/processor.h>
19#include <asm/uaccess.h>
Paul Mundtf3c25752006-09-27 18:36:17 +090020#include <asm/page.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <asm/system.h>
22#include <asm/cacheflush.h>
23#include <asm/cache.h>
Paul Mundtcd012042007-12-10 15:50:28 +090024#include <asm/elf.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <asm/io.h>
Paul Mundtaba10302007-09-21 18:32:32 +090026#include <asm/smp.h>
Paul Mundtc881cbc2007-11-10 20:18:18 +090027#ifdef CONFIG_SUPERH32
28#include <asm/ubc.h>
29#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
31/*
32 * Generic wrapper for command line arguments to disable on-chip
33 * peripherals (nofpu, nodsp, and so forth).
34 */
35#define onchip_setup(x) \
36static int x##_disabled __initdata = 0; \
37 \
38static int __init x##_setup(char *opts) \
39{ \
40 x##_disabled = 1; \
OGAWA Hirofumi9b410462006-03-31 02:30:33 -080041 return 1; \
Linus Torvalds1da177e2005-04-16 15:20:36 -070042} \
43__setup("no" __stringify(x), x##_setup);
44
45onchip_setup(fpu);
46onchip_setup(dsp);
47
Paul Mundt45ed2852007-03-08 18:12:17 +090048#ifdef CONFIG_SPECULATIVE_EXECUTION
49#define CPUOPM 0xff2f0000
50#define CPUOPM_RABD (1 << 5)
51
52static void __init speculative_execution_init(void)
53{
54 /* Clear RABD */
55 ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
56
57 /* Flush the update */
58 (void)ctrl_inl(CPUOPM);
59 ctrl_barrier();
60}
61#else
62#define speculative_execution_init() do { } while (0)
63#endif
64
Linus Torvalds1da177e2005-04-16 15:20:36 -070065/*
66 * Generic first-level cache init
67 */
Paul Mundt27a511c2007-11-10 20:25:28 +090068#ifdef CONFIG_SUPERH32
Stuart Menefycbaa1182007-11-30 17:06:36 +090069static void __uses_jump_to_uncached cache_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070070{
71 unsigned long ccr, flags;
72
Stuart Menefycbaa1182007-11-30 17:06:36 +090073 jump_to_uncached();
Linus Torvalds1da177e2005-04-16 15:20:36 -070074 ccr = ctrl_inl(CCR);
75
76 /*
Richard Curnowb638d0b2006-09-27 14:09:26 +090077 * At this point we don't know whether the cache is enabled or not - a
78 * bootloader may have enabled it. There are at least 2 things that
79 * could be dirty in the cache at this point:
80 * 1. kernel command line set up by boot loader
81 * 2. spilled registers from the prolog of this function
82 * => before re-initialising the cache, we must do a purge of the whole
83 * cache out to memory for safety. As long as nothing is spilled
84 * during the loop to lines that have already been done, this is safe.
85 * - RPC
Linus Torvalds1da177e2005-04-16 15:20:36 -070086 */
87 if (ccr & CCR_CACHE_ENABLE) {
88 unsigned long ways, waysize, addrstart;
89
Paul Mundt11c19652006-12-25 10:19:56 +090090 waysize = current_cpu_data.dcache.sets;
Linus Torvalds1da177e2005-04-16 15:20:36 -070091
Yoshinori Sato9d4436a2006-11-05 15:40:13 +090092#ifdef CCR_CACHE_ORA
Linus Torvalds1da177e2005-04-16 15:20:36 -070093 /*
94 * If the OC is already in RAM mode, we only have
95 * half of the entries to flush..
96 */
97 if (ccr & CCR_CACHE_ORA)
98 waysize >>= 1;
Yoshinori Sato9d4436a2006-11-05 15:40:13 +090099#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100
Paul Mundt11c19652006-12-25 10:19:56 +0900101 waysize <<= current_cpu_data.dcache.entry_shift;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102
103#ifdef CCR_CACHE_EMODE
104 /* If EMODE is not set, we only have 1 way to flush. */
105 if (!(ccr & CCR_CACHE_EMODE))
106 ways = 1;
107 else
108#endif
Paul Mundt11c19652006-12-25 10:19:56 +0900109 ways = current_cpu_data.dcache.ways;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110
111 addrstart = CACHE_OC_ADDRESS_ARRAY;
112 do {
113 unsigned long addr;
114
115 for (addr = addrstart;
116 addr < addrstart + waysize;
Paul Mundt11c19652006-12-25 10:19:56 +0900117 addr += current_cpu_data.dcache.linesz)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118 ctrl_outl(0, addr);
119
Paul Mundt11c19652006-12-25 10:19:56 +0900120 addrstart += current_cpu_data.dcache.way_incr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121 } while (--ways);
122 }
123
124 /*
125 * Default CCR values .. enable the caches
126 * and invalidate them immediately..
127 */
128 flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE;
129
130#ifdef CCR_CACHE_EMODE
131 /* Force EMODE if possible */
Paul Mundt11c19652006-12-25 10:19:56 +0900132 if (current_cpu_data.dcache.ways > 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133 flags |= CCR_CACHE_EMODE;
Richard Curnowb638d0b2006-09-27 14:09:26 +0900134 else
135 flags &= ~CCR_CACHE_EMODE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136#endif
137
Paul Mundte7bd34a2007-07-31 17:07:28 +0900138#if defined(CONFIG_CACHE_WRITETHROUGH)
139 /* Write-through */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140 flags |= CCR_CACHE_WT;
Paul Mundte7bd34a2007-07-31 17:07:28 +0900141#elif defined(CONFIG_CACHE_WRITEBACK)
142 /* Write-back */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 flags |= CCR_CACHE_CB;
Paul Mundte7bd34a2007-07-31 17:07:28 +0900144#else
145 /* Off */
146 flags &= ~CCR_CACHE_ENABLE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147#endif
148
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149 ctrl_outl(flags, CCR);
Stuart Menefycbaa1182007-11-30 17:06:36 +0900150 back_to_cached();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151}
Paul Mundt27a511c2007-11-10 20:25:28 +0900152#else
153#define cache_init() do { } while (0)
154#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700155
Paul Mundtcd012042007-12-10 15:50:28 +0900156#define CSHAPE(totalsize, linesize, assoc) \
157 ((totalsize & ~0xff) | (linesize << 4) | assoc)
158
159#define CACHE_DESC_SHAPE(desc) \
160 CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways)
161
162static void detect_cache_shape(void)
163{
164 l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache);
165
166 if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED)
167 l1i_cache_shape = l1d_cache_shape;
168 else
169 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache);
170
171 if (current_cpu_data.flags & CPU_HAS_L2_CACHE)
172 l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache);
173 else
174 l2_cache_shape = -1; /* No S-cache */
175}
176
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177#ifdef CONFIG_SH_DSP
178static void __init release_dsp(void)
179{
180 unsigned long sr;
181
182 /* Clear SR.DSP bit */
183 __asm__ __volatile__ (
184 "stc\tsr, %0\n\t"
185 "and\t%1, %0\n\t"
186 "ldc\t%0, sr\n\t"
187 : "=&r" (sr)
188 : "r" (~SR_DSP)
189 );
190}
191
192static void __init dsp_init(void)
193{
194 unsigned long sr;
195
196 /*
197 * Set the SR.DSP bit, wait for one instruction, and then read
198 * back the SR value.
199 */
200 __asm__ __volatile__ (
201 "stc\tsr, %0\n\t"
202 "or\t%1, %0\n\t"
203 "ldc\t%0, sr\n\t"
204 "nop\n\t"
205 "stc\tsr, %0\n\t"
206 : "=&r" (sr)
207 : "r" (SR_DSP)
208 );
209
210 /* If the DSP bit is still set, this CPU has a DSP */
211 if (sr & SR_DSP)
Paul Mundt11c19652006-12-25 10:19:56 +0900212 current_cpu_data.flags |= CPU_HAS_DSP;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213
214 /* Now that we've determined the DSP status, clear the DSP bit. */
215 release_dsp();
216}
217#endif /* CONFIG_SH_DSP */
218
219/**
220 * sh_cpu_init
221 *
222 * This is our initial entry point for each CPU, and is invoked on the boot
223 * CPU prior to calling start_kernel(). For SMP, a combination of this and
224 * start_secondary() will bring up each processor to a ready state prior
225 * to hand forking the idle loop.
226 *
227 * We do all of the basic processor init here, including setting up the
228 * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is
229 * hit (and subsequently platform_setup()) things like determining the
230 * CPU subtype and initial configuration will all be done.
231 *
232 * Each processor family is still responsible for doing its own probing
233 * and cache configuration in detect_cpu_and_cache_system().
234 */
Paul Mundtaba10302007-09-21 18:32:32 +0900235
Paul Mundtb2839ed2008-03-06 12:43:38 +0900236asmlinkage void __init sh_cpu_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237{
Paul Mundtaba10302007-09-21 18:32:32 +0900238 current_thread_info()->cpu = hard_smp_processor_id();
239
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240 /* First, probe the CPU */
241 detect_cpu_and_cache_system();
242
Paul Mundtffe1b4e2007-03-12 16:15:22 +0900243 if (current_cpu_data.type == CPU_SH_NONE)
244 panic("Unknown CPU");
245
Paul Mundt27a511c2007-11-10 20:25:28 +0900246 /* First setup the rest of the I-cache info */
247 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
248 current_cpu_data.icache.linesz;
249
250 current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
251 current_cpu_data.icache.linesz;
252
253 /* And the D-cache too */
254 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
255 current_cpu_data.dcache.linesz;
256
257 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
258 current_cpu_data.dcache.linesz;
259
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260 /* Init the cache */
261 cache_init();
262
Paul Mundtcd012042007-12-10 15:50:28 +0900263 if (raw_smp_processor_id() == 0) {
Paul Mundt4a4a9be2008-11-12 13:17:38 +0900264#ifdef CONFIG_MMU
Paul Mundtaba10302007-09-21 18:32:32 +0900265 shm_align_mask = max_t(unsigned long,
266 current_cpu_data.dcache.way_size - 1,
267 PAGE_SIZE - 1);
Paul Mundt4a4a9be2008-11-12 13:17:38 +0900268#endif
Paul Mundtf3c25752006-09-27 18:36:17 +0900269
Paul Mundtcd012042007-12-10 15:50:28 +0900270 /* Boot CPU sets the cache shape */
271 detect_cache_shape();
272 }
273
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274 /* Disable the FPU */
275 if (fpu_disabled) {
276 printk("FPU Disabled\n");
Paul Mundt11c19652006-12-25 10:19:56 +0900277 current_cpu_data.flags &= ~CPU_HAS_FPU;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278 disable_fpu();
279 }
280
281 /* FPU initialization */
Paul Mundt11c19652006-12-25 10:19:56 +0900282 if ((current_cpu_data.flags & CPU_HAS_FPU)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283 clear_thread_flag(TIF_USEDFPU);
284 clear_used_math();
285 }
286
Paul Mundtaec5e0e2006-12-25 09:51:47 +0900287 /*
288 * Initialize the per-CPU ASID cache very early, since the
289 * TLB flushing routines depend on this being setup.
290 */
291 current_cpu_data.asid_cache = NO_CONTEXT;
292
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293#ifdef CONFIG_SH_DSP
294 /* Probe for DSP */
295 dsp_init();
296
297 /* Disable the DSP */
298 if (dsp_disabled) {
299 printk("DSP Disabled\n");
Paul Mundt11c19652006-12-25 10:19:56 +0900300 current_cpu_data.flags &= ~CPU_HAS_DSP;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301 release_dsp();
302 }
303#endif
304
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305 /*
306 * Some brain-damaged loaders decided it would be a good idea to put
307 * the UBC to sleep. This causes some issues when it comes to things
308 * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So ..
309 * we wake it up and hope that all is well.
310 */
Paul Mundtc881cbc2007-11-10 20:18:18 +0900311#ifdef CONFIG_SUPERH32
Paul Mundtaba10302007-09-21 18:32:32 +0900312 if (raw_smp_processor_id() == 0)
313 ubc_wakeup();
Paul Mundtc881cbc2007-11-10 20:18:18 +0900314#endif
315
Paul Mundt45ed2852007-03-08 18:12:17 +0900316 speculative_execution_init();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317}