Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * arch/sh/kernel/cpu/init.c |
| 3 | * |
| 4 | * CPU init code |
| 5 | * |
Paul Mundt | ffe1b4e | 2007-03-12 16:15:22 +0900 | [diff] [blame] | 6 | * Copyright (C) 2002 - 2007 Paul Mundt |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 7 | * Copyright (C) 2003 Richard Curnow |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * |
| 9 | * This file is subject to the terms and conditions of the GNU General Public |
| 10 | * License. See the file "COPYING" in the main directory of this archive |
| 11 | * for more details. |
| 12 | */ |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/kernel.h> |
Paul Mundt | aec5e0e | 2006-12-25 09:51:47 +0900 | [diff] [blame] | 15 | #include <linux/mm.h> |
Paul Mundt | cd01204 | 2007-12-10 15:50:28 +0900 | [diff] [blame] | 16 | #include <linux/log2.h> |
Paul Mundt | aec5e0e | 2006-12-25 09:51:47 +0900 | [diff] [blame] | 17 | #include <asm/mmu_context.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <asm/processor.h> |
| 19 | #include <asm/uaccess.h> |
Paul Mundt | f3c2575 | 2006-09-27 18:36:17 +0900 | [diff] [blame] | 20 | #include <asm/page.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #include <asm/system.h> |
| 22 | #include <asm/cacheflush.h> |
| 23 | #include <asm/cache.h> |
Paul Mundt | cd01204 | 2007-12-10 15:50:28 +0900 | [diff] [blame] | 24 | #include <asm/elf.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | #include <asm/io.h> |
Paul Mundt | aba1030 | 2007-09-21 18:32:32 +0900 | [diff] [blame] | 26 | #include <asm/smp.h> |
Paul Mundt | c881cbc | 2007-11-10 20:18:18 +0900 | [diff] [blame] | 27 | #ifdef CONFIG_SUPERH32 |
| 28 | #include <asm/ubc.h> |
| 29 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | |
| 31 | /* |
| 32 | * Generic wrapper for command line arguments to disable on-chip |
| 33 | * peripherals (nofpu, nodsp, and so forth). |
| 34 | */ |
| 35 | #define onchip_setup(x) \ |
| 36 | static int x##_disabled __initdata = 0; \ |
| 37 | \ |
| 38 | static int __init x##_setup(char *opts) \ |
| 39 | { \ |
| 40 | x##_disabled = 1; \ |
OGAWA Hirofumi | 9b41046 | 2006-03-31 02:30:33 -0800 | [diff] [blame] | 41 | return 1; \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | } \ |
| 43 | __setup("no" __stringify(x), x##_setup); |
| 44 | |
| 45 | onchip_setup(fpu); |
| 46 | onchip_setup(dsp); |
| 47 | |
Paul Mundt | 45ed285 | 2007-03-08 18:12:17 +0900 | [diff] [blame] | 48 | #ifdef CONFIG_SPECULATIVE_EXECUTION |
| 49 | #define CPUOPM 0xff2f0000 |
| 50 | #define CPUOPM_RABD (1 << 5) |
| 51 | |
| 52 | static void __init speculative_execution_init(void) |
| 53 | { |
| 54 | /* Clear RABD */ |
| 55 | ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); |
| 56 | |
| 57 | /* Flush the update */ |
| 58 | (void)ctrl_inl(CPUOPM); |
| 59 | ctrl_barrier(); |
| 60 | } |
| 61 | #else |
| 62 | #define speculative_execution_init() do { } while (0) |
| 63 | #endif |
| 64 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 | /* |
| 66 | * Generic first-level cache init |
| 67 | */ |
Paul Mundt | 27a511c | 2007-11-10 20:25:28 +0900 | [diff] [blame] | 68 | #ifdef CONFIG_SUPERH32 |
Stuart Menefy | cbaa118 | 2007-11-30 17:06:36 +0900 | [diff] [blame] | 69 | static void __uses_jump_to_uncached cache_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | { |
| 71 | unsigned long ccr, flags; |
| 72 | |
Stuart Menefy | cbaa118 | 2007-11-30 17:06:36 +0900 | [diff] [blame] | 73 | jump_to_uncached(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | ccr = ctrl_inl(CCR); |
| 75 | |
| 76 | /* |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 77 | * At this point we don't know whether the cache is enabled or not - a |
| 78 | * bootloader may have enabled it. There are at least 2 things that |
| 79 | * could be dirty in the cache at this point: |
| 80 | * 1. kernel command line set up by boot loader |
| 81 | * 2. spilled registers from the prolog of this function |
| 82 | * => before re-initialising the cache, we must do a purge of the whole |
| 83 | * cache out to memory for safety. As long as nothing is spilled |
| 84 | * during the loop to lines that have already been done, this is safe. |
| 85 | * - RPC |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 86 | */ |
| 87 | if (ccr & CCR_CACHE_ENABLE) { |
| 88 | unsigned long ways, waysize, addrstart; |
| 89 | |
Paul Mundt | 11c1965 | 2006-12-25 10:19:56 +0900 | [diff] [blame] | 90 | waysize = current_cpu_data.dcache.sets; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | |
Yoshinori Sato | 9d4436a | 2006-11-05 15:40:13 +0900 | [diff] [blame] | 92 | #ifdef CCR_CACHE_ORA |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 93 | /* |
| 94 | * If the OC is already in RAM mode, we only have |
| 95 | * half of the entries to flush.. |
| 96 | */ |
| 97 | if (ccr & CCR_CACHE_ORA) |
| 98 | waysize >>= 1; |
Yoshinori Sato | 9d4436a | 2006-11-05 15:40:13 +0900 | [diff] [blame] | 99 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | |
Paul Mundt | 11c1965 | 2006-12-25 10:19:56 +0900 | [diff] [blame] | 101 | waysize <<= current_cpu_data.dcache.entry_shift; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | |
| 103 | #ifdef CCR_CACHE_EMODE |
| 104 | /* If EMODE is not set, we only have 1 way to flush. */ |
| 105 | if (!(ccr & CCR_CACHE_EMODE)) |
| 106 | ways = 1; |
| 107 | else |
| 108 | #endif |
Paul Mundt | 11c1965 | 2006-12-25 10:19:56 +0900 | [diff] [blame] | 109 | ways = current_cpu_data.dcache.ways; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | |
| 111 | addrstart = CACHE_OC_ADDRESS_ARRAY; |
| 112 | do { |
| 113 | unsigned long addr; |
| 114 | |
| 115 | for (addr = addrstart; |
| 116 | addr < addrstart + waysize; |
Paul Mundt | 11c1965 | 2006-12-25 10:19:56 +0900 | [diff] [blame] | 117 | addr += current_cpu_data.dcache.linesz) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | ctrl_outl(0, addr); |
| 119 | |
Paul Mundt | 11c1965 | 2006-12-25 10:19:56 +0900 | [diff] [blame] | 120 | addrstart += current_cpu_data.dcache.way_incr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 121 | } while (--ways); |
| 122 | } |
| 123 | |
| 124 | /* |
| 125 | * Default CCR values .. enable the caches |
| 126 | * and invalidate them immediately.. |
| 127 | */ |
| 128 | flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE; |
| 129 | |
| 130 | #ifdef CCR_CACHE_EMODE |
| 131 | /* Force EMODE if possible */ |
Paul Mundt | 11c1965 | 2006-12-25 10:19:56 +0900 | [diff] [blame] | 132 | if (current_cpu_data.dcache.ways > 1) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 133 | flags |= CCR_CACHE_EMODE; |
Richard Curnow | b638d0b | 2006-09-27 14:09:26 +0900 | [diff] [blame] | 134 | else |
| 135 | flags &= ~CCR_CACHE_EMODE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 136 | #endif |
| 137 | |
Paul Mundt | e7bd34a | 2007-07-31 17:07:28 +0900 | [diff] [blame] | 138 | #if defined(CONFIG_CACHE_WRITETHROUGH) |
| 139 | /* Write-through */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 140 | flags |= CCR_CACHE_WT; |
Paul Mundt | e7bd34a | 2007-07-31 17:07:28 +0900 | [diff] [blame] | 141 | #elif defined(CONFIG_CACHE_WRITEBACK) |
| 142 | /* Write-back */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | flags |= CCR_CACHE_CB; |
Paul Mundt | e7bd34a | 2007-07-31 17:07:28 +0900 | [diff] [blame] | 144 | #else |
| 145 | /* Off */ |
| 146 | flags &= ~CCR_CACHE_ENABLE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 147 | #endif |
| 148 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 149 | ctrl_outl(flags, CCR); |
Stuart Menefy | cbaa118 | 2007-11-30 17:06:36 +0900 | [diff] [blame] | 150 | back_to_cached(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | } |
Paul Mundt | 27a511c | 2007-11-10 20:25:28 +0900 | [diff] [blame] | 152 | #else |
| 153 | #define cache_init() do { } while (0) |
| 154 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | |
Paul Mundt | cd01204 | 2007-12-10 15:50:28 +0900 | [diff] [blame] | 156 | #define CSHAPE(totalsize, linesize, assoc) \ |
| 157 | ((totalsize & ~0xff) | (linesize << 4) | assoc) |
| 158 | |
| 159 | #define CACHE_DESC_SHAPE(desc) \ |
| 160 | CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways) |
| 161 | |
| 162 | static void detect_cache_shape(void) |
| 163 | { |
| 164 | l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache); |
| 165 | |
| 166 | if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED) |
| 167 | l1i_cache_shape = l1d_cache_shape; |
| 168 | else |
| 169 | l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache); |
| 170 | |
| 171 | if (current_cpu_data.flags & CPU_HAS_L2_CACHE) |
| 172 | l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache); |
| 173 | else |
| 174 | l2_cache_shape = -1; /* No S-cache */ |
| 175 | } |
| 176 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 177 | #ifdef CONFIG_SH_DSP |
| 178 | static void __init release_dsp(void) |
| 179 | { |
| 180 | unsigned long sr; |
| 181 | |
| 182 | /* Clear SR.DSP bit */ |
| 183 | __asm__ __volatile__ ( |
| 184 | "stc\tsr, %0\n\t" |
| 185 | "and\t%1, %0\n\t" |
| 186 | "ldc\t%0, sr\n\t" |
| 187 | : "=&r" (sr) |
| 188 | : "r" (~SR_DSP) |
| 189 | ); |
| 190 | } |
| 191 | |
| 192 | static void __init dsp_init(void) |
| 193 | { |
| 194 | unsigned long sr; |
| 195 | |
| 196 | /* |
| 197 | * Set the SR.DSP bit, wait for one instruction, and then read |
| 198 | * back the SR value. |
| 199 | */ |
| 200 | __asm__ __volatile__ ( |
| 201 | "stc\tsr, %0\n\t" |
| 202 | "or\t%1, %0\n\t" |
| 203 | "ldc\t%0, sr\n\t" |
| 204 | "nop\n\t" |
| 205 | "stc\tsr, %0\n\t" |
| 206 | : "=&r" (sr) |
| 207 | : "r" (SR_DSP) |
| 208 | ); |
| 209 | |
| 210 | /* If the DSP bit is still set, this CPU has a DSP */ |
| 211 | if (sr & SR_DSP) |
Paul Mundt | 11c1965 | 2006-12-25 10:19:56 +0900 | [diff] [blame] | 212 | current_cpu_data.flags |= CPU_HAS_DSP; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | |
| 214 | /* Now that we've determined the DSP status, clear the DSP bit. */ |
| 215 | release_dsp(); |
| 216 | } |
| 217 | #endif /* CONFIG_SH_DSP */ |
| 218 | |
| 219 | /** |
| 220 | * sh_cpu_init |
| 221 | * |
| 222 | * This is our initial entry point for each CPU, and is invoked on the boot |
| 223 | * CPU prior to calling start_kernel(). For SMP, a combination of this and |
| 224 | * start_secondary() will bring up each processor to a ready state prior |
| 225 | * to hand forking the idle loop. |
| 226 | * |
| 227 | * We do all of the basic processor init here, including setting up the |
| 228 | * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is |
| 229 | * hit (and subsequently platform_setup()) things like determining the |
| 230 | * CPU subtype and initial configuration will all be done. |
| 231 | * |
| 232 | * Each processor family is still responsible for doing its own probing |
| 233 | * and cache configuration in detect_cpu_and_cache_system(). |
| 234 | */ |
Paul Mundt | aba1030 | 2007-09-21 18:32:32 +0900 | [diff] [blame] | 235 | |
Paul Mundt | b2839ed | 2008-03-06 12:43:38 +0900 | [diff] [blame] | 236 | asmlinkage void __init sh_cpu_init(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | { |
Paul Mundt | aba1030 | 2007-09-21 18:32:32 +0900 | [diff] [blame] | 238 | current_thread_info()->cpu = hard_smp_processor_id(); |
| 239 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 240 | /* First, probe the CPU */ |
| 241 | detect_cpu_and_cache_system(); |
| 242 | |
Paul Mundt | ffe1b4e | 2007-03-12 16:15:22 +0900 | [diff] [blame] | 243 | if (current_cpu_data.type == CPU_SH_NONE) |
| 244 | panic("Unknown CPU"); |
| 245 | |
Paul Mundt | 27a511c | 2007-11-10 20:25:28 +0900 | [diff] [blame] | 246 | /* First setup the rest of the I-cache info */ |
| 247 | current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - |
| 248 | current_cpu_data.icache.linesz; |
| 249 | |
| 250 | current_cpu_data.icache.way_size = current_cpu_data.icache.sets * |
| 251 | current_cpu_data.icache.linesz; |
| 252 | |
| 253 | /* And the D-cache too */ |
| 254 | current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr - |
| 255 | current_cpu_data.dcache.linesz; |
| 256 | |
| 257 | current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets * |
| 258 | current_cpu_data.dcache.linesz; |
| 259 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 260 | /* Init the cache */ |
| 261 | cache_init(); |
| 262 | |
Paul Mundt | cd01204 | 2007-12-10 15:50:28 +0900 | [diff] [blame] | 263 | if (raw_smp_processor_id() == 0) { |
Paul Mundt | 4a4a9be | 2008-11-12 13:17:38 +0900 | [diff] [blame] | 264 | #ifdef CONFIG_MMU |
Paul Mundt | aba1030 | 2007-09-21 18:32:32 +0900 | [diff] [blame] | 265 | shm_align_mask = max_t(unsigned long, |
| 266 | current_cpu_data.dcache.way_size - 1, |
| 267 | PAGE_SIZE - 1); |
Paul Mundt | 4a4a9be | 2008-11-12 13:17:38 +0900 | [diff] [blame] | 268 | #endif |
Paul Mundt | f3c2575 | 2006-09-27 18:36:17 +0900 | [diff] [blame] | 269 | |
Paul Mundt | cd01204 | 2007-12-10 15:50:28 +0900 | [diff] [blame] | 270 | /* Boot CPU sets the cache shape */ |
| 271 | detect_cache_shape(); |
| 272 | } |
| 273 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | /* Disable the FPU */ |
| 275 | if (fpu_disabled) { |
| 276 | printk("FPU Disabled\n"); |
Paul Mundt | 11c1965 | 2006-12-25 10:19:56 +0900 | [diff] [blame] | 277 | current_cpu_data.flags &= ~CPU_HAS_FPU; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 278 | disable_fpu(); |
| 279 | } |
| 280 | |
| 281 | /* FPU initialization */ |
Paul Mundt | 11c1965 | 2006-12-25 10:19:56 +0900 | [diff] [blame] | 282 | if ((current_cpu_data.flags & CPU_HAS_FPU)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | clear_thread_flag(TIF_USEDFPU); |
| 284 | clear_used_math(); |
| 285 | } |
| 286 | |
Paul Mundt | aec5e0e | 2006-12-25 09:51:47 +0900 | [diff] [blame] | 287 | /* |
| 288 | * Initialize the per-CPU ASID cache very early, since the |
| 289 | * TLB flushing routines depend on this being setup. |
| 290 | */ |
| 291 | current_cpu_data.asid_cache = NO_CONTEXT; |
| 292 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | #ifdef CONFIG_SH_DSP |
| 294 | /* Probe for DSP */ |
| 295 | dsp_init(); |
| 296 | |
| 297 | /* Disable the DSP */ |
| 298 | if (dsp_disabled) { |
| 299 | printk("DSP Disabled\n"); |
Paul Mundt | 11c1965 | 2006-12-25 10:19:56 +0900 | [diff] [blame] | 300 | current_cpu_data.flags &= ~CPU_HAS_DSP; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 301 | release_dsp(); |
| 302 | } |
| 303 | #endif |
| 304 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 305 | /* |
| 306 | * Some brain-damaged loaders decided it would be a good idea to put |
| 307 | * the UBC to sleep. This causes some issues when it comes to things |
| 308 | * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So .. |
| 309 | * we wake it up and hope that all is well. |
| 310 | */ |
Paul Mundt | c881cbc | 2007-11-10 20:18:18 +0900 | [diff] [blame] | 311 | #ifdef CONFIG_SUPERH32 |
Paul Mundt | aba1030 | 2007-09-21 18:32:32 +0900 | [diff] [blame] | 312 | if (raw_smp_processor_id() == 0) |
| 313 | ubc_wakeup(); |
Paul Mundt | c881cbc | 2007-11-10 20:18:18 +0900 | [diff] [blame] | 314 | #endif |
| 315 | |
Paul Mundt | 45ed285 | 2007-03-08 18:12:17 +0900 | [diff] [blame] | 316 | speculative_execution_init(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 317 | } |