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Ralf Baechle73b43902008-07-16 16:12:25 +01001#ifndef __ASM_RC32434_IRQ_H
2#define __ASM_RC32434_IRQ_H
3
4#define NR_IRQS 256
5
6#include <asm/mach-generic/irq.h>
Florian Fainelli606a0832008-08-23 18:53:50 +02007#include <asm/mach-rc32434/rb.h>
8
9/* Interrupt Controller */
10#define IC_GROUP0_PEND (REGBASE + 0x38000)
11#define IC_GROUP0_MASK (REGBASE + 0x38008)
12#define IC_GROUP_OFFSET 0x0C
13
14#define NUM_INTR_GROUPS 5
15
16/* 16550 UARTs */
17#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
18 /* GRP3 IRQ numbers start here */
19#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32)
20 /* GRP4 IRQ numbers start here */
21#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32)
22 /* GRP5 IRQ numbers start here */
23#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)
24#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
25
26#define UART0_IRQ (GROUP3_IRQ_BASE + 0)
Ralf Baechle73b43902008-07-16 16:12:25 +010027
Florian Fainelli3cd4e062008-08-22 17:00:22 +020028#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0)
29#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1)
30#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
31#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
32
Phil Sutter4aa0f4d2008-11-28 20:45:10 +010033#define GPIO_MAPPED_IRQ_BASE GROUP4_IRQ_BASE
34#define GPIO_MAPPED_IRQ_GROUP 4
35
Ralf Baechle73b43902008-07-16 16:12:25 +010036#endif /* __ASM_RC32434_IRQ_H */