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Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001/*
2 * linux/arch/arm/plat-omap/dma.c
3 *
Tony Lindgren97b7f712008-07-03 12:24:37 +03004 * Copyright (C) 2003 - 2008 Nokia Corporation
Jan Engelhardt96de0e22007-10-19 23:21:04 +02005 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01006 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
Anand Gadiyarf8151e52007-12-01 12:14:11 -08009 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
Tony Lindgren1a8bfa12005-11-10 14:26:50 +000010 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010011 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
Santosh Shilimkar44169072009-05-28 14:16:04 -070013 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 *
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010016 * Support functions for the OMAP internal DMA channels.
17 *
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -080018 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
21 *
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010022 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25 *
26 */
27
28#include <linux/module.h>
29#include <linux/init.h>
30#include <linux/sched.h>
31#include <linux/spinlock.h>
32#include <linux/errno.h>
33#include <linux/interrupt.h>
Thomas Gleixner418ca1f2006-07-01 22:32:41 +010034#include <linux/irq.h>
Tony Lindgren97b7f712008-07-03 12:24:37 +030035#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090036#include <linux/slab.h>
Peter Ujfalusi0e4905c2010-10-11 14:18:56 -070037#include <linux/delay.h>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010038
Russell Kinga09e64f2008-08-05 16:14:15 +010039#include <mach/hardware.h>
Tony Lindgrence491cf2009-10-20 09:40:47 -070040#include <plat/dma.h>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010041
Tony Lindgrence491cf2009-10-20 09:40:47 -070042#include <plat/tc.h>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010043
Paul Walmsleybc4d8b52012-04-13 06:34:30 -060044/*
45 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
46 * channels that an instance of the SDMA IP block can support. Used
47 * to size arrays. (The actual maximum on a particular SoC may be less
48 * than this -- for example, OMAP1 SDMA instances only support 17 logical
49 * DMA channels.)
50 */
51#define MAX_LOGICAL_DMA_CH_COUNT 32
52
Anand Gadiyarf8151e52007-12-01 12:14:11 -080053#undef DEBUG
54
55#ifndef CONFIG_ARCH_OMAP1
56enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
57 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
58};
59
60enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
Tony Lindgren1a8bfa12005-11-10 14:26:50 +000061#endif
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010062
Tony Lindgren97b7f712008-07-03 12:24:37 +030063#define OMAP_DMA_ACTIVE 0x01
Adrian Hunter4fb699b2010-11-24 13:23:21 +020064#define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010065
Tony Lindgren97b7f712008-07-03 12:24:37 +030066#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010067
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -080068static struct omap_system_dma_plat_info *p;
69static struct omap_dma_dev_attr *d;
70
Tony Lindgren97b7f712008-07-03 12:24:37 +030071static int enable_1510_mode;
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -080072static u32 errata;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010073
Tero Kristof2d11852008-08-28 13:13:31 +000074static struct omap_dma_global_context_registers {
75 u32 dma_irqenable_l0;
76 u32 dma_ocp_sysconfig;
77 u32 dma_gcr;
78} omap_dma_global_context;
79
Anand Gadiyarf8151e52007-12-01 12:14:11 -080080struct dma_link_info {
81 int *linked_dmach_q;
82 int no_of_lchs_linked;
83
84 int q_count;
85 int q_tail;
86 int q_head;
87
88 int chain_state;
89 int chain_mode;
90
91};
92
Tony Lindgren4d963722008-07-03 12:24:31 +030093static struct dma_link_info *dma_linked_lch;
94
95#ifndef CONFIG_ARCH_OMAP1
Anand Gadiyarf8151e52007-12-01 12:14:11 -080096
97/* Chain handling macros */
98#define OMAP_DMA_CHAIN_QINIT(chain_id) \
99 do { \
100 dma_linked_lch[chain_id].q_head = \
101 dma_linked_lch[chain_id].q_tail = \
102 dma_linked_lch[chain_id].q_count = 0; \
103 } while (0)
104#define OMAP_DMA_CHAIN_QFULL(chain_id) \
105 (dma_linked_lch[chain_id].no_of_lchs_linked == \
106 dma_linked_lch[chain_id].q_count)
107#define OMAP_DMA_CHAIN_QLAST(chain_id) \
108 do { \
109 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
110 dma_linked_lch[chain_id].q_count) \
111 } while (0)
112#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
113 (0 == dma_linked_lch[chain_id].q_count)
114#define __OMAP_DMA_CHAIN_INCQ(end) \
115 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
116#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
117 do { \
118 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
119 dma_linked_lch[chain_id].q_count--; \
120 } while (0)
121
122#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
123 do { \
124 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
125 dma_linked_lch[chain_id].q_count++; \
126 } while (0)
127#endif
Tony Lindgren4d963722008-07-03 12:24:31 +0300128
129static int dma_lch_count;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100130static int dma_chan_count;
Santosh Shilimkar2263f022009-03-23 18:07:48 -0700131static int omap_dma_reserve_channels;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100132
133static spinlock_t dma_chan_lock;
Tony Lindgren4d963722008-07-03 12:24:31 +0300134static struct omap_dma_lch *dma_chan;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100135
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800136static inline void disable_lnk(int lch);
137static void omap_disable_channel_irq(int lch);
138static inline void omap_enable_channel_irq(int lch);
139
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000140#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
Harvey Harrison8e86f422008-03-04 15:08:02 -0800141 __func__);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000142
143#ifdef CONFIG_ARCH_OMAP15XX
144/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
Aaro Koskinenc7767582011-01-27 16:39:43 -0800145static int omap_dma_in_1510_mode(void)
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000146{
147 return enable_1510_mode;
148}
149#else
150#define omap_dma_in_1510_mode() 0
151#endif
152
153#ifdef CONFIG_ARCH_OMAP1
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100154static inline int get_gdma_dev(int req)
155{
156 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
157 int shift = ((req - 1) % 5) * 6;
158
159 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
160}
161
162static inline void set_gdma_dev(int req, int dev)
163{
164 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
165 int shift = ((req - 1) % 5) * 6;
166 u32 l;
167
168 l = omap_readl(reg);
169 l &= ~(0x3f << shift);
170 l |= (dev - 1) << shift;
171 omap_writel(l, reg);
172}
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000173#else
174#define set_gdma_dev(req, dev) do {} while (0)
Tony Lindgren2c799ce2012-02-24 10:34:35 -0800175#define omap_readl(reg) 0
176#define omap_writel(val, reg) do {} while (0)
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000177#endif
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100178
Tony Lindgren709eb3e52006-09-25 12:45:45 +0300179void omap_set_dma_priority(int lch, int dst_port, int priority)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100180{
181 unsigned long reg;
182 u32 l;
183
Tony Lindgren709eb3e52006-09-25 12:45:45 +0300184 if (cpu_class_is_omap1()) {
185 switch (dst_port) {
186 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
187 reg = OMAP_TC_OCPT1_PRIOR;
188 break;
189 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
190 reg = OMAP_TC_OCPT2_PRIOR;
191 break;
192 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
193 reg = OMAP_TC_EMIFF_PRIOR;
194 break;
195 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
196 reg = OMAP_TC_EMIFS_PRIOR;
197 break;
198 default:
199 BUG();
200 return;
201 }
202 l = omap_readl(reg);
203 l &= ~(0xf << 8);
204 l |= (priority & 0xf) << 8;
205 omap_writel(l, reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100206 }
Tony Lindgren709eb3e52006-09-25 12:45:45 +0300207
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800208 if (cpu_class_is_omap2()) {
Tony Lindgren0499bde2008-07-03 12:24:36 +0300209 u32 ccr;
210
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800211 ccr = p->dma_read(CCR, lch);
Tony Lindgren709eb3e52006-09-25 12:45:45 +0300212 if (priority)
Tony Lindgren0499bde2008-07-03 12:24:36 +0300213 ccr |= (1 << 6);
Tony Lindgren709eb3e52006-09-25 12:45:45 +0300214 else
Tony Lindgren0499bde2008-07-03 12:24:36 +0300215 ccr &= ~(1 << 6);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800216 p->dma_write(ccr, CCR, lch);
Tony Lindgren709eb3e52006-09-25 12:45:45 +0300217 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100218}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300219EXPORT_SYMBOL(omap_set_dma_priority);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100220
221void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000222 int frame_count, int sync_mode,
223 int dma_trigger, int src_or_dst_synch)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100224{
Tony Lindgren0499bde2008-07-03 12:24:36 +0300225 u32 l;
226
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800227 l = p->dma_read(CSDP, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300228 l &= ~0x03;
229 l |= data_type;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800230 p->dma_write(l, CSDP, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100231
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000232 if (cpu_class_is_omap1()) {
Tony Lindgren0499bde2008-07-03 12:24:36 +0300233 u16 ccr;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100234
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800235 ccr = p->dma_read(CCR, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300236 ccr &= ~(1 << 5);
237 if (sync_mode == OMAP_DMA_SYNC_FRAME)
238 ccr |= 1 << 5;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800239 p->dma_write(ccr, CCR, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300240
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800241 ccr = p->dma_read(CCR2, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300242 ccr &= ~(1 << 2);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000243 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
Tony Lindgren0499bde2008-07-03 12:24:36 +0300244 ccr |= 1 << 2;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800245 p->dma_write(ccr, CCR2, lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000246 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100247
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800248 if (cpu_class_is_omap2() && dma_trigger) {
Tony Lindgren0499bde2008-07-03 12:24:36 +0300249 u32 val;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100250
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800251 val = p->dma_read(CCR, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100252
Anand Gadiyar4b3cf442009-01-15 13:09:53 +0200253 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
Samu Onkalo72a11792010-08-02 14:21:40 +0300254 val &= ~((1 << 23) | (3 << 19) | 0x1f);
Anand Gadiyar4b3cf442009-01-15 13:09:53 +0200255 val |= (dma_trigger & ~0x1f) << 14;
256 val |= dma_trigger & 0x1f;
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000257
258 if (sync_mode & OMAP_DMA_SYNC_FRAME)
259 val |= 1 << 5;
Peter Ujfalusieca9e562006-06-26 16:16:06 -0700260 else
261 val &= ~(1 << 5);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000262
263 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
264 val |= 1 << 18;
Peter Ujfalusieca9e562006-06-26 16:16:06 -0700265 else
266 val &= ~(1 << 18);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000267
Samu Onkalo72a11792010-08-02 14:21:40 +0300268 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000269 val &= ~(1 << 24); /* dest synch */
Samu Onkalo72a11792010-08-02 14:21:40 +0300270 val |= (1 << 23); /* Prefetch */
271 } else if (src_or_dst_synch) {
272 val |= 1 << 24; /* source synch */
273 } else {
274 val &= ~(1 << 24); /* dest synch */
275 }
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800276 p->dma_write(val, CCR, lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000277 }
278
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800279 p->dma_write(elem_count, CEN, lch);
280 p->dma_write(frame_count, CFN, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100281}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300282EXPORT_SYMBOL(omap_set_dma_transfer_params);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000283
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100284void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
285{
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100286 BUG_ON(omap_dma_in_1510_mode());
287
Tomi Valkeinen0815f8e2009-05-28 13:23:51 -0700288 if (cpu_class_is_omap1()) {
289 u16 w;
290
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800291 w = p->dma_read(CCR2, lch);
Tomi Valkeinen0815f8e2009-05-28 13:23:51 -0700292 w &= ~0x03;
293
294 switch (mode) {
295 case OMAP_DMA_CONSTANT_FILL:
296 w |= 0x01;
297 break;
298 case OMAP_DMA_TRANSPARENT_COPY:
299 w |= 0x02;
300 break;
301 case OMAP_DMA_COLOR_DIS:
302 break;
303 default:
304 BUG();
305 }
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800306 p->dma_write(w, CCR2, lch);
Tomi Valkeinen0815f8e2009-05-28 13:23:51 -0700307
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800308 w = p->dma_read(LCH_CTRL, lch);
Tomi Valkeinen0815f8e2009-05-28 13:23:51 -0700309 w &= ~0x0f;
310 /* Default is channel type 2D */
311 if (mode) {
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800312 p->dma_write(color, COLOR, lch);
Tomi Valkeinen0815f8e2009-05-28 13:23:51 -0700313 w |= 1; /* Channel type G */
314 }
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800315 p->dma_write(w, LCH_CTRL, lch);
Tomi Valkeinen0815f8e2009-05-28 13:23:51 -0700316 }
317
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800318 if (cpu_class_is_omap2()) {
Tomi Valkeinen0815f8e2009-05-28 13:23:51 -0700319 u32 val;
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000320
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800321 val = p->dma_read(CCR, lch);
Tomi Valkeinen0815f8e2009-05-28 13:23:51 -0700322 val &= ~((1 << 17) | (1 << 16));
Tony Lindgren0499bde2008-07-03 12:24:36 +0300323
Tomi Valkeinen0815f8e2009-05-28 13:23:51 -0700324 switch (mode) {
325 case OMAP_DMA_CONSTANT_FILL:
326 val |= 1 << 16;
327 break;
328 case OMAP_DMA_TRANSPARENT_COPY:
329 val |= 1 << 17;
330 break;
331 case OMAP_DMA_COLOR_DIS:
332 break;
333 default:
334 BUG();
335 }
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800336 p->dma_write(val, CCR, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100337
Tomi Valkeinen0815f8e2009-05-28 13:23:51 -0700338 color &= 0xffffff;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800339 p->dma_write(color, COLOR, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100340 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100341}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300342EXPORT_SYMBOL(omap_set_dma_color_mode);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100343
Tony Lindgren709eb3e52006-09-25 12:45:45 +0300344void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
345{
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800346 if (cpu_class_is_omap2()) {
Tony Lindgren0499bde2008-07-03 12:24:36 +0300347 u32 csdp;
348
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800349 csdp = p->dma_read(CSDP, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300350 csdp &= ~(0x3 << 16);
351 csdp |= (mode << 16);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800352 p->dma_write(csdp, CSDP, lch);
Tony Lindgren709eb3e52006-09-25 12:45:45 +0300353 }
354}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300355EXPORT_SYMBOL(omap_set_dma_write_mode);
Tony Lindgren709eb3e52006-09-25 12:45:45 +0300356
Tony Lindgren0499bde2008-07-03 12:24:36 +0300357void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
358{
359 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
360 u32 l;
361
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800362 l = p->dma_read(LCH_CTRL, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300363 l &= ~0x7;
364 l |= mode;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800365 p->dma_write(l, LCH_CTRL, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300366 }
367}
368EXPORT_SYMBOL(omap_set_dma_channel_mode);
369
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000370/* Note that src_port is only for omap1 */
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100371void omap_set_dma_src_params(int lch, int src_port, int src_amode,
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000372 unsigned long src_start,
373 int src_ei, int src_fi)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100374{
Tony Lindgren97b7f712008-07-03 12:24:37 +0300375 u32 l;
376
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000377 if (cpu_class_is_omap1()) {
Tony Lindgren0499bde2008-07-03 12:24:36 +0300378 u16 w;
379
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800380 w = p->dma_read(CSDP, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300381 w &= ~(0x1f << 2);
382 w |= src_port << 2;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800383 p->dma_write(w, CSDP, lch);
Tony Lindgren97b7f712008-07-03 12:24:37 +0300384 }
Tony Lindgren0499bde2008-07-03 12:24:36 +0300385
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800386 l = p->dma_read(CCR, lch);
Tony Lindgren97b7f712008-07-03 12:24:37 +0300387 l &= ~(0x03 << 12);
388 l |= src_amode << 12;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800389 p->dma_write(l, CCR, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300390
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800391 p->dma_write(src_start, CSSA, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100392
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800393 p->dma_write(src_ei, CSEI, lch);
394 p->dma_write(src_fi, CSFI, lch);
Tony Lindgren97b7f712008-07-03 12:24:37 +0300395}
396EXPORT_SYMBOL(omap_set_dma_src_params);
397
398void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000399{
400 omap_set_dma_transfer_params(lch, params->data_type,
401 params->elem_count, params->frame_count,
402 params->sync_mode, params->trigger,
403 params->src_or_dst_synch);
404 omap_set_dma_src_params(lch, params->src_port,
405 params->src_amode, params->src_start,
406 params->src_ei, params->src_fi);
407
408 omap_set_dma_dest_params(lch, params->dst_port,
409 params->dst_amode, params->dst_start,
410 params->dst_ei, params->dst_fi);
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800411 if (params->read_prio || params->write_prio)
412 omap_dma_set_prio_lch(lch, params->read_prio,
413 params->write_prio);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100414}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300415EXPORT_SYMBOL(omap_set_dma_params);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100416
417void omap_set_dma_src_index(int lch, int eidx, int fidx)
418{
Tony Lindgren97b7f712008-07-03 12:24:37 +0300419 if (cpu_class_is_omap2())
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000420 return;
Tony Lindgren97b7f712008-07-03 12:24:37 +0300421
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800422 p->dma_write(eidx, CSEI, lch);
423 p->dma_write(fidx, CSFI, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100424}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300425EXPORT_SYMBOL(omap_set_dma_src_index);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100426
427void omap_set_dma_src_data_pack(int lch, int enable)
428{
Tony Lindgren0499bde2008-07-03 12:24:36 +0300429 u32 l;
430
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800431 l = p->dma_read(CSDP, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300432 l &= ~(1 << 6);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000433 if (enable)
Tony Lindgren0499bde2008-07-03 12:24:36 +0300434 l |= (1 << 6);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800435 p->dma_write(l, CSDP, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100436}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300437EXPORT_SYMBOL(omap_set_dma_src_data_pack);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100438
439void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
440{
Kyungmin Park6dc3c8f2006-06-26 16:16:14 -0700441 unsigned int burst = 0;
Tony Lindgren0499bde2008-07-03 12:24:36 +0300442 u32 l;
443
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800444 l = p->dma_read(CSDP, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300445 l &= ~(0x03 << 7);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100446
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100447 switch (burst_mode) {
448 case OMAP_DMA_DATA_BURST_DIS:
449 break;
450 case OMAP_DMA_DATA_BURST_4:
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800451 if (cpu_class_is_omap2())
Kyungmin Park6dc3c8f2006-06-26 16:16:14 -0700452 burst = 0x1;
453 else
454 burst = 0x2;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100455 break;
456 case OMAP_DMA_DATA_BURST_8:
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800457 if (cpu_class_is_omap2()) {
Kyungmin Park6dc3c8f2006-06-26 16:16:14 -0700458 burst = 0x2;
459 break;
460 }
manjugk manjugkea221a62010-05-14 12:05:25 -0700461 /*
462 * not supported by current hardware on OMAP1
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100463 * w |= (0x03 << 7);
464 * fall through
465 */
Kyungmin Park6dc3c8f2006-06-26 16:16:14 -0700466 case OMAP_DMA_DATA_BURST_16:
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800467 if (cpu_class_is_omap2()) {
Kyungmin Park6dc3c8f2006-06-26 16:16:14 -0700468 burst = 0x3;
469 break;
470 }
manjugk manjugkea221a62010-05-14 12:05:25 -0700471 /*
472 * OMAP1 don't support burst 16
Kyungmin Park6dc3c8f2006-06-26 16:16:14 -0700473 * fall through
474 */
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100475 default:
476 BUG();
477 }
Tony Lindgren0499bde2008-07-03 12:24:36 +0300478
479 l |= (burst << 7);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800480 p->dma_write(l, CSDP, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100481}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300482EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100483
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000484/* Note that dest_port is only for OMAP1 */
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100485void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000486 unsigned long dest_start,
487 int dst_ei, int dst_fi)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100488{
Tony Lindgren0499bde2008-07-03 12:24:36 +0300489 u32 l;
490
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000491 if (cpu_class_is_omap1()) {
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800492 l = p->dma_read(CSDP, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300493 l &= ~(0x1f << 9);
494 l |= dest_port << 9;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800495 p->dma_write(l, CSDP, lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000496 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100497
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800498 l = p->dma_read(CCR, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300499 l &= ~(0x03 << 14);
500 l |= dest_amode << 14;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800501 p->dma_write(l, CCR, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100502
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800503 p->dma_write(dest_start, CDSA, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100504
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800505 p->dma_write(dst_ei, CDEI, lch);
506 p->dma_write(dst_fi, CDFI, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100507}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300508EXPORT_SYMBOL(omap_set_dma_dest_params);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100509
510void omap_set_dma_dest_index(int lch, int eidx, int fidx)
511{
Tony Lindgren97b7f712008-07-03 12:24:37 +0300512 if (cpu_class_is_omap2())
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000513 return;
Tony Lindgren97b7f712008-07-03 12:24:37 +0300514
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800515 p->dma_write(eidx, CDEI, lch);
516 p->dma_write(fidx, CDFI, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100517}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300518EXPORT_SYMBOL(omap_set_dma_dest_index);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100519
520void omap_set_dma_dest_data_pack(int lch, int enable)
521{
Tony Lindgren0499bde2008-07-03 12:24:36 +0300522 u32 l;
523
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800524 l = p->dma_read(CSDP, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300525 l &= ~(1 << 13);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000526 if (enable)
Tony Lindgren0499bde2008-07-03 12:24:36 +0300527 l |= 1 << 13;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800528 p->dma_write(l, CSDP, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100529}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300530EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100531
532void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
533{
Kyungmin Park6dc3c8f2006-06-26 16:16:14 -0700534 unsigned int burst = 0;
Tony Lindgren0499bde2008-07-03 12:24:36 +0300535 u32 l;
536
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800537 l = p->dma_read(CSDP, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300538 l &= ~(0x03 << 14);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100539
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100540 switch (burst_mode) {
541 case OMAP_DMA_DATA_BURST_DIS:
542 break;
543 case OMAP_DMA_DATA_BURST_4:
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800544 if (cpu_class_is_omap2())
Kyungmin Park6dc3c8f2006-06-26 16:16:14 -0700545 burst = 0x1;
546 else
547 burst = 0x2;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100548 break;
549 case OMAP_DMA_DATA_BURST_8:
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800550 if (cpu_class_is_omap2())
Kyungmin Park6dc3c8f2006-06-26 16:16:14 -0700551 burst = 0x2;
552 else
553 burst = 0x3;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100554 break;
Kyungmin Park6dc3c8f2006-06-26 16:16:14 -0700555 case OMAP_DMA_DATA_BURST_16:
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800556 if (cpu_class_is_omap2()) {
Kyungmin Park6dc3c8f2006-06-26 16:16:14 -0700557 burst = 0x3;
558 break;
559 }
manjugk manjugkea221a62010-05-14 12:05:25 -0700560 /*
561 * OMAP1 don't support burst 16
Kyungmin Park6dc3c8f2006-06-26 16:16:14 -0700562 * fall through
563 */
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100564 default:
565 printk(KERN_ERR "Invalid DMA burst mode\n");
566 BUG();
567 return;
568 }
Tony Lindgren0499bde2008-07-03 12:24:36 +0300569 l |= (burst << 14);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800570 p->dma_write(l, CSDP, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100571}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300572EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100573
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000574static inline void omap_enable_channel_irq(int lch)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100575{
Tony Lindgren7ff879d2006-06-26 16:16:15 -0700576 /* Clear CSR */
577 if (cpu_class_is_omap1())
Oleg Matcovschibedfb7a2012-05-15 14:35:08 -0700578 p->dma_read(CSR, lch);
579 else
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800580 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000581
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100582 /* Enable some nice interrupts. */
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800583 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100584}
585
Oleg Matcovschibedfb7a2012-05-15 14:35:08 -0700586static inline void omap_disable_channel_irq(int lch)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100587{
Oleg Matcovschibedfb7a2012-05-15 14:35:08 -0700588 /* disable channel interrupts */
589 p->dma_write(0, CICR, lch);
590 /* Clear CSR */
591 if (cpu_class_is_omap1())
592 p->dma_read(CSR, lch);
593 else
594 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100595}
596
597void omap_enable_dma_irq(int lch, u16 bits)
598{
599 dma_chan[lch].enabled_irqs |= bits;
600}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300601EXPORT_SYMBOL(omap_enable_dma_irq);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100602
603void omap_disable_dma_irq(int lch, u16 bits)
604{
605 dma_chan[lch].enabled_irqs &= ~bits;
606}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300607EXPORT_SYMBOL(omap_disable_dma_irq);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100608
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000609static inline void enable_lnk(int lch)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100610{
Tony Lindgren0499bde2008-07-03 12:24:36 +0300611 u32 l;
612
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800613 l = p->dma_read(CLNK_CTRL, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300614
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000615 if (cpu_class_is_omap1())
Tony Lindgren0499bde2008-07-03 12:24:36 +0300616 l &= ~(1 << 14);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100617
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000618 /* Set the ENABLE_LNK bits */
619 if (dma_chan[lch].next_lch != -1)
Tony Lindgren0499bde2008-07-03 12:24:36 +0300620 l = dma_chan[lch].next_lch | (1 << 15);
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800621
622#ifndef CONFIG_ARCH_OMAP1
Tony Lindgren97b7f712008-07-03 12:24:37 +0300623 if (cpu_class_is_omap2())
624 if (dma_chan[lch].next_linked_ch != -1)
625 l = dma_chan[lch].next_linked_ch | (1 << 15);
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800626#endif
Tony Lindgren0499bde2008-07-03 12:24:36 +0300627
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800628 p->dma_write(l, CLNK_CTRL, lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100629}
630
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000631static inline void disable_lnk(int lch)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100632{
Tony Lindgren0499bde2008-07-03 12:24:36 +0300633 u32 l;
634
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800635 l = p->dma_read(CLNK_CTRL, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300636
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000637 /* Disable interrupts */
Oleg Matcovschibedfb7a2012-05-15 14:35:08 -0700638 omap_disable_channel_irq(lch);
639
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000640 if (cpu_class_is_omap1()) {
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000641 /* Set the STOP_LNK bit */
Tony Lindgren0499bde2008-07-03 12:24:36 +0300642 l |= 1 << 14;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100643 }
644
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800645 if (cpu_class_is_omap2()) {
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000646 /* Clear the ENABLE_LNK bit */
Tony Lindgren0499bde2008-07-03 12:24:36 +0300647 l &= ~(1 << 15);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000648 }
649
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800650 p->dma_write(l, CLNK_CTRL, lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000651 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
652}
653
654static inline void omap2_enable_irq_lch(int lch)
655{
656 u32 val;
Tao Huee907322009-11-10 18:55:17 -0800657 unsigned long flags;
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000658
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800659 if (!cpu_class_is_omap2())
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000660 return;
661
Tao Huee907322009-11-10 18:55:17 -0800662 spin_lock_irqsave(&dma_chan_lock, flags);
Oleg Matcovschibedfb7a2012-05-15 14:35:08 -0700663 /* clear IRQ STATUS */
664 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
665 /* Enable interrupt */
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800666 val = p->dma_read(IRQENABLE_L0, lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000667 val |= 1 << lch;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800668 p->dma_write(val, IRQENABLE_L0, lch);
Tao Huee907322009-11-10 18:55:17 -0800669 spin_unlock_irqrestore(&dma_chan_lock, flags);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100670}
671
Mika Westerbergada8d4a2010-05-14 12:05:25 -0700672static inline void omap2_disable_irq_lch(int lch)
673{
674 u32 val;
675 unsigned long flags;
676
677 if (!cpu_class_is_omap2())
678 return;
679
680 spin_lock_irqsave(&dma_chan_lock, flags);
Oleg Matcovschibedfb7a2012-05-15 14:35:08 -0700681 /* Disable interrupt */
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800682 val = p->dma_read(IRQENABLE_L0, lch);
Mika Westerbergada8d4a2010-05-14 12:05:25 -0700683 val &= ~(1 << lch);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800684 p->dma_write(val, IRQENABLE_L0, lch);
Oleg Matcovschibedfb7a2012-05-15 14:35:08 -0700685 /* clear IRQ STATUS */
686 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
Mika Westerbergada8d4a2010-05-14 12:05:25 -0700687 spin_unlock_irqrestore(&dma_chan_lock, flags);
688}
689
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100690int omap_request_dma(int dev_id, const char *dev_name,
Tony Lindgren97b7f712008-07-03 12:24:37 +0300691 void (*callback)(int lch, u16 ch_status, void *data),
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100692 void *data, int *dma_ch_out)
693{
694 int ch, free_ch = -1;
695 unsigned long flags;
696 struct omap_dma_lch *chan;
697
698 spin_lock_irqsave(&dma_chan_lock, flags);
699 for (ch = 0; ch < dma_chan_count; ch++) {
700 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
701 free_ch = ch;
702 if (dev_id == 0)
703 break;
704 }
705 }
706 if (free_ch == -1) {
707 spin_unlock_irqrestore(&dma_chan_lock, flags);
708 return -EBUSY;
709 }
710 chan = dma_chan + free_ch;
711 chan->dev_id = dev_id;
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000712
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800713 if (p->clear_lch_regs)
714 p->clear_lch_regs(free_ch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000715
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800716 if (cpu_class_is_omap2())
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000717 omap_clear_dma(free_ch);
718
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100719 spin_unlock_irqrestore(&dma_chan_lock, flags);
720
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100721 chan->dev_name = dev_name;
722 chan->callback = callback;
723 chan->data = data;
Jarkko Nikulaa92fda12009-01-29 08:57:12 -0800724 chan->flags = 0;
Tony Lindgren97b7f712008-07-03 12:24:37 +0300725
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800726#ifndef CONFIG_ARCH_OMAP1
Tony Lindgren97b7f712008-07-03 12:24:37 +0300727 if (cpu_class_is_omap2()) {
728 chan->chain_id = -1;
729 chan->next_linked_ch = -1;
730 }
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800731#endif
Tony Lindgren97b7f712008-07-03 12:24:37 +0300732
Tony Lindgren7ff879d2006-06-26 16:16:15 -0700733 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000734
Tony Lindgren7ff879d2006-06-26 16:16:15 -0700735 if (cpu_class_is_omap1())
736 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800737 else if (cpu_class_is_omap2())
Tony Lindgren7ff879d2006-06-26 16:16:15 -0700738 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
739 OMAP2_DMA_TRANS_ERR_IRQ;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100740
741 if (cpu_is_omap16xx()) {
742 /* If the sync device is set, configure it dynamically. */
743 if (dev_id != 0) {
744 set_gdma_dev(free_ch + 1, dev_id);
745 dev_id = free_ch + 1;
746 }
Tony Lindgren97b7f712008-07-03 12:24:37 +0300747 /*
748 * Disable the 1510 compatibility mode and set the sync device
749 * id.
750 */
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800751 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
Zebediah C. McClure557096f2009-03-23 18:07:44 -0700752 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800753 p->dma_write(dev_id, CCR, free_ch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100754 }
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000755
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800756 if (cpu_class_is_omap2()) {
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000757 omap_enable_channel_irq(free_ch);
Oleg Matcovschibedfb7a2012-05-15 14:35:08 -0700758 omap2_enable_irq_lch(free_ch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000759 }
760
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100761 *dma_ch_out = free_ch;
762
763 return 0;
764}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300765EXPORT_SYMBOL(omap_request_dma);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100766
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000767void omap_free_dma(int lch)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100768{
769 unsigned long flags;
770
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000771 if (dma_chan[lch].dev_id == -1) {
Tony Lindgren97b7f712008-07-03 12:24:37 +0300772 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000773 lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100774 return;
775 }
Tony Lindgren97b7f712008-07-03 12:24:37 +0300776
Oleg Matcovschibedfb7a2012-05-15 14:35:08 -0700777 /* Disable interrupt for logical channel */
778 if (cpu_class_is_omap2())
Mika Westerbergada8d4a2010-05-14 12:05:25 -0700779 omap2_disable_irq_lch(lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000780
Oleg Matcovschibedfb7a2012-05-15 14:35:08 -0700781 /* Disable all DMA interrupts for the channel. */
782 omap_disable_channel_irq(lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000783
Oleg Matcovschibedfb7a2012-05-15 14:35:08 -0700784 /* Make sure the DMA transfer is stopped. */
785 p->dma_write(0, CCR, lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000786
Oleg Matcovschibedfb7a2012-05-15 14:35:08 -0700787 /* Clear registers */
788 if (cpu_class_is_omap2())
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000789 omap_clear_dma(lch);
Santosh Shilimkarda1b94e2009-04-23 11:10:40 -0700790
791 spin_lock_irqsave(&dma_chan_lock, flags);
792 dma_chan[lch].dev_id = -1;
793 dma_chan[lch].next_lch = -1;
794 dma_chan[lch].callback = NULL;
795 spin_unlock_irqrestore(&dma_chan_lock, flags);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100796}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300797EXPORT_SYMBOL(omap_free_dma);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100798
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800799/**
800 * @brief omap_dma_set_global_params : Set global priority settings for dma
801 *
802 * @param arb_rate
803 * @param max_fifo_depth
Anuj Aggarwal70cf6442009-10-14 09:56:34 -0700804 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
805 * DMA_THREAD_RESERVE_ONET
806 * DMA_THREAD_RESERVE_TWOT
807 * DMA_THREAD_RESERVE_THREET
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800808 */
809void
810omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
811{
812 u32 reg;
813
814 if (!cpu_class_is_omap2()) {
Harvey Harrison8e86f422008-03-04 15:08:02 -0800815 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800816 return;
817 }
818
Anuj Aggarwal70cf6442009-10-14 09:56:34 -0700819 if (max_fifo_depth == 0)
820 max_fifo_depth = 1;
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800821 if (arb_rate == 0)
822 arb_rate = 1;
823
Anuj Aggarwal70cf6442009-10-14 09:56:34 -0700824 reg = 0xff & max_fifo_depth;
825 reg |= (0x3 & tparams) << 12;
826 reg |= (arb_rate & 0xff) << 16;
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800827
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800828 p->dma_write(reg, GCR, 0);
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800829}
830EXPORT_SYMBOL(omap_dma_set_global_params);
831
832/**
833 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
834 *
835 * @param lch
836 * @param read_prio - Read priority
837 * @param write_prio - Write priority
838 * Both of the above can be set with one of the following values :
839 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
840 */
841int
842omap_dma_set_prio_lch(int lch, unsigned char read_prio,
843 unsigned char write_prio)
844{
Tony Lindgren0499bde2008-07-03 12:24:36 +0300845 u32 l;
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800846
Tony Lindgren4d963722008-07-03 12:24:31 +0300847 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800848 printk(KERN_ERR "Invalid channel id\n");
849 return -EINVAL;
850 }
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800851 l = p->dma_read(CCR, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300852 l &= ~((1 << 6) | (1 << 26));
Santosh Shilimkard07c3df2012-04-28 20:19:10 +0530853 if (cpu_class_is_omap2() && !cpu_is_omap242x())
Tony Lindgren0499bde2008-07-03 12:24:36 +0300854 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800855 else
Tony Lindgren0499bde2008-07-03 12:24:36 +0300856 l |= ((read_prio & 0x1) << 6);
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800857
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800858 p->dma_write(l, CCR, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300859
Anand Gadiyarf8151e52007-12-01 12:14:11 -0800860 return 0;
861}
862EXPORT_SYMBOL(omap_dma_set_prio_lch);
863
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000864/*
865 * Clears any DMA state so the DMA engine is ready to restart with new buffers
866 * through omap_start_dma(). Any buffers in flight are discarded.
867 */
868void omap_clear_dma(int lch)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100869{
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000870 unsigned long flags;
871
872 local_irq_save(flags);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800873 p->clear_dma(lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000874 local_irq_restore(flags);
875}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300876EXPORT_SYMBOL(omap_clear_dma);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000877
878void omap_start_dma(int lch)
879{
Tony Lindgren0499bde2008-07-03 12:24:36 +0300880 u32 l;
881
manjugk manjugk519e6162010-03-04 07:11:56 +0000882 /*
883 * The CPC/CDAC register needs to be initialized to zero
884 * before starting dma transfer.
885 */
886 if (cpu_is_omap15xx())
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800887 p->dma_write(0, CPC, lch);
manjugk manjugk519e6162010-03-04 07:11:56 +0000888 else
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800889 p->dma_write(0, CDAC, lch);
manjugk manjugk519e6162010-03-04 07:11:56 +0000890
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000891 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
892 int next_lch, cur_lch;
Paul Walmsleybc4d8b52012-04-13 06:34:30 -0600893 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000894
895 dma_chan_link_map[lch] = 1;
896 /* Set the link register of the first channel */
897 enable_lnk(lch);
898
899 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
900 cur_lch = dma_chan[lch].next_lch;
901 do {
902 next_lch = dma_chan[cur_lch].next_lch;
903
904 /* The loop case: we've been here already */
905 if (dma_chan_link_map[cur_lch])
906 break;
907 /* Mark the current channel */
908 dma_chan_link_map[cur_lch] = 1;
909
910 enable_lnk(cur_lch);
911 omap_enable_channel_irq(cur_lch);
912
913 cur_lch = next_lch;
914 } while (next_lch != -1);
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -0800915 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800916 p->dma_write(lch, CLNK_CTRL, lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000917
918 omap_enable_channel_irq(lch);
919
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800920 l = p->dma_read(CCR, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +0300921
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -0800922 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
923 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
Tony Lindgren0499bde2008-07-03 12:24:36 +0300924 l |= OMAP_DMA_CCR_EN;
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -0800925
Russell King35453582012-04-14 18:57:10 +0100926 /*
927 * As dma_write() uses IO accessors which are weakly ordered, there
928 * is no guarantee that data in coherent DMA memory will be visible
929 * to the DMA device. Add a memory barrier here to ensure that any
930 * such data is visible prior to enabling DMA.
931 */
932 mb();
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800933 p->dma_write(l, CCR, lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000934
935 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
936}
Tony Lindgren97b7f712008-07-03 12:24:37 +0300937EXPORT_SYMBOL(omap_start_dma);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000938
939void omap_stop_dma(int lch)
940{
Tony Lindgren0499bde2008-07-03 12:24:36 +0300941 u32 l;
942
Santosh Shilimkar9da65a92009-10-22 14:46:31 -0700943 /* Disable all interrupts on the channel */
Oleg Matcovschibedfb7a2012-05-15 14:35:08 -0700944 omap_disable_channel_irq(lch);
Santosh Shilimkar9da65a92009-10-22 14:46:31 -0700945
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800946 l = p->dma_read(CCR, lch);
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -0800947 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
948 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
Peter Ujfalusi0e4905c2010-10-11 14:18:56 -0700949 int i = 0;
950 u32 sys_cf;
951
952 /* Configure No-Standby */
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800953 l = p->dma_read(OCP_SYSCONFIG, lch);
Peter Ujfalusi0e4905c2010-10-11 14:18:56 -0700954 sys_cf = l;
955 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
956 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800957 p->dma_write(l , OCP_SYSCONFIG, 0);
Peter Ujfalusi0e4905c2010-10-11 14:18:56 -0700958
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800959 l = p->dma_read(CCR, lch);
Peter Ujfalusi0e4905c2010-10-11 14:18:56 -0700960 l &= ~OMAP_DMA_CCR_EN;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800961 p->dma_write(l, CCR, lch);
Peter Ujfalusi0e4905c2010-10-11 14:18:56 -0700962
963 /* Wait for sDMA FIFO drain */
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800964 l = p->dma_read(CCR, lch);
Peter Ujfalusi0e4905c2010-10-11 14:18:56 -0700965 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
966 OMAP_DMA_CCR_WR_ACTIVE))) {
967 udelay(5);
968 i++;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800969 l = p->dma_read(CCR, lch);
Peter Ujfalusi0e4905c2010-10-11 14:18:56 -0700970 }
971 if (i >= 100)
972 printk(KERN_ERR "DMA drain did not complete on "
973 "lch %d\n", lch);
974 /* Restore OCP_SYSCONFIG */
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800975 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
Peter Ujfalusi0e4905c2010-10-11 14:18:56 -0700976 } else {
977 l &= ~OMAP_DMA_CCR_EN;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -0800978 p->dma_write(l, CCR, lch);
Peter Ujfalusi0e4905c2010-10-11 14:18:56 -0700979 }
Santosh Shilimkar9da65a92009-10-22 14:46:31 -0700980
Russell King35453582012-04-14 18:57:10 +0100981 /*
982 * Ensure that data transferred by DMA is visible to any access
983 * after DMA has been disabled. This is important for coherent
984 * DMA regions.
985 */
986 mb();
987
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000988 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
989 int next_lch, cur_lch = lch;
Paul Walmsleybc4d8b52012-04-13 06:34:30 -0600990 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000991
992 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
993 do {
994 /* The loop case: we've been here already */
995 if (dma_chan_link_map[cur_lch])
996 break;
997 /* Mark the current channel */
998 dma_chan_link_map[cur_lch] = 1;
999
1000 disable_lnk(cur_lch);
1001
1002 next_lch = dma_chan[cur_lch].next_lch;
1003 cur_lch = next_lch;
1004 } while (next_lch != -1);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001005 }
1006
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001007 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1008}
Tony Lindgren97b7f712008-07-03 12:24:37 +03001009EXPORT_SYMBOL(omap_stop_dma);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001010
1011/*
Tony Lindgren709eb3e52006-09-25 12:45:45 +03001012 * Allows changing the DMA callback function or data. This may be needed if
1013 * the driver shares a single DMA channel for multiple dma triggers.
1014 */
1015int omap_set_dma_callback(int lch,
Tony Lindgren97b7f712008-07-03 12:24:37 +03001016 void (*callback)(int lch, u16 ch_status, void *data),
Tony Lindgren709eb3e52006-09-25 12:45:45 +03001017 void *data)
1018{
1019 unsigned long flags;
1020
1021 if (lch < 0)
1022 return -ENODEV;
1023
1024 spin_lock_irqsave(&dma_chan_lock, flags);
1025 if (dma_chan[lch].dev_id == -1) {
1026 printk(KERN_ERR "DMA callback for not set for free channel\n");
1027 spin_unlock_irqrestore(&dma_chan_lock, flags);
1028 return -EINVAL;
1029 }
1030 dma_chan[lch].callback = callback;
1031 dma_chan[lch].data = data;
1032 spin_unlock_irqrestore(&dma_chan_lock, flags);
1033
1034 return 0;
1035}
Tony Lindgren97b7f712008-07-03 12:24:37 +03001036EXPORT_SYMBOL(omap_set_dma_callback);
Tony Lindgren709eb3e52006-09-25 12:45:45 +03001037
1038/*
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001039 * Returns current physical source address for the given DMA channel.
1040 * If the channel is running the caller must disable interrupts prior calling
1041 * this function and process the returned value before re-enabling interrupt to
1042 * prevent races with the interrupt handler. Note that in continuous mode there
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001043 * is a chance for CSSA_L register overflow between the two reads resulting
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001044 * in incorrect return value.
1045 */
1046dma_addr_t omap_get_dma_src_pos(int lch)
1047{
Tony Lindgren0695de32007-05-07 18:24:14 -07001048 dma_addr_t offset = 0;
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001049
Tony Lindgren0499bde2008-07-03 12:24:36 +03001050 if (cpu_is_omap15xx())
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001051 offset = p->dma_read(CPC, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +03001052 else
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001053 offset = p->dma_read(CSAC, lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001054
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -08001055 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001056 offset = p->dma_read(CSAC, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +03001057
Peter Ujfalusi7ba96682011-12-09 13:38:00 -08001058 if (!cpu_is_omap15xx()) {
1059 /*
1060 * CDAC == 0 indicates that the DMA transfer on the channel has
1061 * not been started (no data has been transferred so far).
1062 * Return the programmed source start address in this case.
1063 */
1064 if (likely(p->dma_read(CDAC, lch)))
1065 offset = p->dma_read(CSAC, lch);
1066 else
1067 offset = p->dma_read(CSSA, lch);
1068 }
1069
Tony Lindgren0499bde2008-07-03 12:24:36 +03001070 if (cpu_class_is_omap1())
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001071 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001072
1073 return offset;
1074}
Tony Lindgren97b7f712008-07-03 12:24:37 +03001075EXPORT_SYMBOL(omap_get_dma_src_pos);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001076
1077/*
1078 * Returns current physical destination address for the given DMA channel.
1079 * If the channel is running the caller must disable interrupts prior calling
1080 * this function and process the returned value before re-enabling interrupt to
1081 * prevent races with the interrupt handler. Note that in continuous mode there
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001082 * is a chance for CDSA_L register overflow between the two reads resulting
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001083 * in incorrect return value.
1084 */
1085dma_addr_t omap_get_dma_dst_pos(int lch)
1086{
Tony Lindgren0695de32007-05-07 18:24:14 -07001087 dma_addr_t offset = 0;
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001088
Tony Lindgren0499bde2008-07-03 12:24:36 +03001089 if (cpu_is_omap15xx())
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001090 offset = p->dma_read(CPC, lch);
Tony Lindgren0499bde2008-07-03 12:24:36 +03001091 else
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001092 offset = p->dma_read(CDAC, lch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001093
Tony Lindgren0499bde2008-07-03 12:24:36 +03001094 /*
1095 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1096 * read before the DMA controller finished disabling the channel.
1097 */
Peter Ujfalusi06e80772011-12-09 13:38:00 -08001098 if (!cpu_is_omap15xx() && offset == 0) {
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001099 offset = p->dma_read(CDAC, lch);
Peter Ujfalusi06e80772011-12-09 13:38:00 -08001100 /*
1101 * CDAC == 0 indicates that the DMA transfer on the channel has
1102 * not been started (no data has been transferred so far).
1103 * Return the programmed destination start address in this case.
1104 */
1105 if (unlikely(!offset))
1106 offset = p->dma_read(CDSA, lch);
1107 }
Tony Lindgren0499bde2008-07-03 12:24:36 +03001108
1109 if (cpu_class_is_omap1())
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001110 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001111
1112 return offset;
1113}
Tony Lindgren97b7f712008-07-03 12:24:37 +03001114EXPORT_SYMBOL(omap_get_dma_dst_pos);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001115
Tony Lindgren0499bde2008-07-03 12:24:36 +03001116int omap_get_dma_active_status(int lch)
1117{
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001118 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
Tony Lindgren0499bde2008-07-03 12:24:36 +03001119}
1120EXPORT_SYMBOL(omap_get_dma_active_status);
1121
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001122int omap_dma_running(void)
1123{
1124 int lch;
1125
Janusz Krzysztofikf8e9e982009-12-11 16:16:33 -08001126 if (cpu_class_is_omap1())
1127 if (omap_lcd_dma_running())
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001128 return 1;
1129
1130 for (lch = 0; lch < dma_chan_count; lch++)
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001131 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001132 return 1;
1133
1134 return 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001135}
1136
1137/*
1138 * lch_queue DMA will start right after lch_head one is finished.
1139 * For this DMA link to start, you still need to start (see omap_start_dma)
1140 * the first one. That will fire up the entire queue.
1141 */
Tony Lindgren97b7f712008-07-03 12:24:37 +03001142void omap_dma_link_lch(int lch_head, int lch_queue)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001143{
1144 if (omap_dma_in_1510_mode()) {
Janusz Krzysztofik9f0f4ae2009-08-23 17:56:12 +02001145 if (lch_head == lch_queue) {
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001146 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
G, Manjunath Kondaiaha4c537c2010-12-20 18:27:17 -08001147 CCR, lch_head);
Janusz Krzysztofik9f0f4ae2009-08-23 17:56:12 +02001148 return;
1149 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001150 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1151 BUG();
1152 return;
1153 }
1154
1155 if ((dma_chan[lch_head].dev_id == -1) ||
1156 (dma_chan[lch_queue].dev_id == -1)) {
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001157 printk(KERN_ERR "omap_dma: trying to link "
1158 "non requested channels\n");
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001159 dump_stack();
1160 }
1161
1162 dma_chan[lch_head].next_lch = lch_queue;
1163}
Tony Lindgren97b7f712008-07-03 12:24:37 +03001164EXPORT_SYMBOL(omap_dma_link_lch);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001165
1166/*
1167 * Once the DMA queue is stopped, we can destroy it.
1168 */
Tony Lindgren97b7f712008-07-03 12:24:37 +03001169void omap_dma_unlink_lch(int lch_head, int lch_queue)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001170{
1171 if (omap_dma_in_1510_mode()) {
Janusz Krzysztofik9f0f4ae2009-08-23 17:56:12 +02001172 if (lch_head == lch_queue) {
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001173 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
G, Manjunath Kondaiaha4c537c2010-12-20 18:27:17 -08001174 CCR, lch_head);
Janusz Krzysztofik9f0f4ae2009-08-23 17:56:12 +02001175 return;
1176 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001177 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1178 BUG();
1179 return;
1180 }
1181
1182 if (dma_chan[lch_head].next_lch != lch_queue ||
1183 dma_chan[lch_head].next_lch == -1) {
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001184 printk(KERN_ERR "omap_dma: trying to unlink "
1185 "non linked channels\n");
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001186 dump_stack();
1187 }
1188
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001189 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
Roel Kluin247421f2010-01-13 18:10:29 -08001190 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001191 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1192 "before unlinking\n");
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001193 dump_stack();
1194 }
1195
1196 dma_chan[lch_head].next_lch = -1;
1197}
Tony Lindgren97b7f712008-07-03 12:24:37 +03001198EXPORT_SYMBOL(omap_dma_unlink_lch);
1199
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001200#ifndef CONFIG_ARCH_OMAP1
1201/* Create chain of DMA channesls */
1202static void create_dma_lch_chain(int lch_head, int lch_queue)
1203{
Tony Lindgren0499bde2008-07-03 12:24:36 +03001204 u32 l;
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001205
1206 /* Check if this is the first link in chain */
1207 if (dma_chan[lch_head].next_linked_ch == -1) {
1208 dma_chan[lch_head].next_linked_ch = lch_queue;
1209 dma_chan[lch_head].prev_linked_ch = lch_queue;
1210 dma_chan[lch_queue].next_linked_ch = lch_head;
1211 dma_chan[lch_queue].prev_linked_ch = lch_head;
1212 }
1213
1214 /* a link exists, link the new channel in circular chain */
1215 else {
1216 dma_chan[lch_queue].next_linked_ch =
1217 dma_chan[lch_head].next_linked_ch;
1218 dma_chan[lch_queue].prev_linked_ch = lch_head;
1219 dma_chan[lch_head].next_linked_ch = lch_queue;
1220 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1221 lch_queue;
1222 }
1223
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001224 l = p->dma_read(CLNK_CTRL, lch_head);
Tony Lindgren0499bde2008-07-03 12:24:36 +03001225 l &= ~(0x1f);
1226 l |= lch_queue;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001227 p->dma_write(l, CLNK_CTRL, lch_head);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001228
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001229 l = p->dma_read(CLNK_CTRL, lch_queue);
Tony Lindgren0499bde2008-07-03 12:24:36 +03001230 l &= ~(0x1f);
1231 l |= (dma_chan[lch_queue].next_linked_ch);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001232 p->dma_write(l, CLNK_CTRL, lch_queue);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001233}
1234
1235/**
1236 * @brief omap_request_dma_chain : Request a chain of DMA channels
1237 *
1238 * @param dev_id - Device id using the dma channel
1239 * @param dev_name - Device name
1240 * @param callback - Call back function
1241 * @chain_id -
1242 * @no_of_chans - Number of channels requested
1243 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1244 * OMAP_DMA_DYNAMIC_CHAIN
1245 * @params - Channel parameters
1246 *
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02001247 * @return - Success : 0
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001248 * Failure: -EINVAL/-ENOMEM
1249 */
1250int omap_request_dma_chain(int dev_id, const char *dev_name,
Santosh Shilimkar279b9182009-05-28 13:23:52 -07001251 void (*callback) (int lch, u16 ch_status,
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001252 void *data),
1253 int *chain_id, int no_of_chans, int chain_mode,
1254 struct omap_dma_channel_params params)
1255{
1256 int *channels;
1257 int i, err;
1258
1259 /* Is the chain mode valid ? */
1260 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1261 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1262 printk(KERN_ERR "Invalid chain mode requested\n");
1263 return -EINVAL;
1264 }
1265
1266 if (unlikely((no_of_chans < 1
Tony Lindgren4d963722008-07-03 12:24:31 +03001267 || no_of_chans > dma_lch_count))) {
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001268 printk(KERN_ERR "Invalid Number of channels requested\n");
1269 return -EINVAL;
1270 }
1271
manjugk manjugkea221a62010-05-14 12:05:25 -07001272 /*
1273 * Allocate a queue to maintain the status of the channels
1274 * in the chain
1275 */
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001276 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1277 if (channels == NULL) {
1278 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1279 return -ENOMEM;
1280 }
1281
1282 /* request and reserve DMA channels for the chain */
1283 for (i = 0; i < no_of_chans; i++) {
1284 err = omap_request_dma(dev_id, dev_name,
Russell Kingc0fc18c52008-09-05 15:10:27 +01001285 callback, NULL, &channels[i]);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001286 if (err < 0) {
1287 int j;
1288 for (j = 0; j < i; j++)
1289 omap_free_dma(channels[j]);
1290 kfree(channels);
1291 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1292 return err;
1293 }
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001294 dma_chan[channels[i]].prev_linked_ch = -1;
1295 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1296
1297 /*
1298 * Allowing client drivers to set common parameters now,
1299 * so that later only relevant (src_start, dest_start
1300 * and element count) can be set
1301 */
1302 omap_set_dma_params(channels[i], &params);
1303 }
1304
1305 *chain_id = channels[0];
1306 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1307 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1308 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1309 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1310
1311 for (i = 0; i < no_of_chans; i++)
1312 dma_chan[channels[i]].chain_id = *chain_id;
1313
1314 /* Reset the Queue pointers */
1315 OMAP_DMA_CHAIN_QINIT(*chain_id);
1316
1317 /* Set up the chain */
1318 if (no_of_chans == 1)
1319 create_dma_lch_chain(channels[0], channels[0]);
1320 else {
1321 for (i = 0; i < (no_of_chans - 1); i++)
1322 create_dma_lch_chain(channels[i], channels[i + 1]);
1323 }
Tony Lindgren97b7f712008-07-03 12:24:37 +03001324
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001325 return 0;
1326}
1327EXPORT_SYMBOL(omap_request_dma_chain);
1328
1329/**
1330 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1331 * params after setting it. Dont do this while dma is running!!
1332 *
1333 * @param chain_id - Chained logical channel id.
1334 * @param params
1335 *
1336 * @return - Success : 0
1337 * Failure : -EINVAL
1338 */
1339int omap_modify_dma_chain_params(int chain_id,
1340 struct omap_dma_channel_params params)
1341{
1342 int *channels;
1343 u32 i;
1344
1345 /* Check for input params */
1346 if (unlikely((chain_id < 0
Tony Lindgren4d963722008-07-03 12:24:31 +03001347 || chain_id >= dma_lch_count))) {
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001348 printk(KERN_ERR "Invalid chain id\n");
1349 return -EINVAL;
1350 }
1351
1352 /* Check if the chain exists */
1353 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1354 printk(KERN_ERR "Chain doesn't exists\n");
1355 return -EINVAL;
1356 }
1357 channels = dma_linked_lch[chain_id].linked_dmach_q;
1358
1359 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1360 /*
1361 * Allowing client drivers to set common parameters now,
1362 * so that later only relevant (src_start, dest_start
1363 * and element count) can be set
1364 */
1365 omap_set_dma_params(channels[i], &params);
1366 }
Tony Lindgren97b7f712008-07-03 12:24:37 +03001367
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001368 return 0;
1369}
1370EXPORT_SYMBOL(omap_modify_dma_chain_params);
1371
1372/**
1373 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1374 *
1375 * @param chain_id
1376 *
1377 * @return - Success : 0
1378 * Failure : -EINVAL
1379 */
1380int omap_free_dma_chain(int chain_id)
1381{
1382 int *channels;
1383 u32 i;
1384
1385 /* Check for input params */
Tony Lindgren4d963722008-07-03 12:24:31 +03001386 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001387 printk(KERN_ERR "Invalid chain id\n");
1388 return -EINVAL;
1389 }
1390
1391 /* Check if the chain exists */
1392 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1393 printk(KERN_ERR "Chain doesn't exists\n");
1394 return -EINVAL;
1395 }
1396
1397 channels = dma_linked_lch[chain_id].linked_dmach_q;
1398 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1399 dma_chan[channels[i]].next_linked_ch = -1;
1400 dma_chan[channels[i]].prev_linked_ch = -1;
1401 dma_chan[channels[i]].chain_id = -1;
1402 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1403 omap_free_dma(channels[i]);
1404 }
1405
1406 kfree(channels);
1407
1408 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1409 dma_linked_lch[chain_id].chain_mode = -1;
1410 dma_linked_lch[chain_id].chain_state = -1;
Tony Lindgren97b7f712008-07-03 12:24:37 +03001411
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001412 return (0);
1413}
1414EXPORT_SYMBOL(omap_free_dma_chain);
1415
1416/**
1417 * @brief omap_dma_chain_status - Check if the chain is in
1418 * active / inactive state.
1419 * @param chain_id
1420 *
1421 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1422 * Failure : -EINVAL
1423 */
1424int omap_dma_chain_status(int chain_id)
1425{
1426 /* Check for input params */
Tony Lindgren4d963722008-07-03 12:24:31 +03001427 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001428 printk(KERN_ERR "Invalid chain id\n");
1429 return -EINVAL;
1430 }
1431
1432 /* Check if the chain exists */
1433 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1434 printk(KERN_ERR "Chain doesn't exists\n");
1435 return -EINVAL;
1436 }
1437 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1438 dma_linked_lch[chain_id].q_count);
1439
1440 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1441 return OMAP_DMA_CHAIN_INACTIVE;
Tony Lindgren97b7f712008-07-03 12:24:37 +03001442
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001443 return OMAP_DMA_CHAIN_ACTIVE;
1444}
1445EXPORT_SYMBOL(omap_dma_chain_status);
1446
1447/**
1448 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1449 * set the params and start the transfer.
1450 *
1451 * @param chain_id
1452 * @param src_start - buffer start address
1453 * @param dest_start - Dest address
1454 * @param elem_count
1455 * @param frame_count
1456 * @param callbk_data - channel callback parameter data.
1457 *
Anand Gadiyarf4b6a7e2008-03-11 01:10:35 +05301458 * @return - Success : 0
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001459 * Failure: -EINVAL/-EBUSY
1460 */
1461int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1462 int elem_count, int frame_count, void *callbk_data)
1463{
1464 int *channels;
Tony Lindgren0499bde2008-07-03 12:24:36 +03001465 u32 l, lch;
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001466 int start_dma = 0;
1467
Tony Lindgren97b7f712008-07-03 12:24:37 +03001468 /*
1469 * if buffer size is less than 1 then there is
1470 * no use of starting the chain
1471 */
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001472 if (elem_count < 1) {
1473 printk(KERN_ERR "Invalid buffer size\n");
1474 return -EINVAL;
1475 }
1476
1477 /* Check for input params */
1478 if (unlikely((chain_id < 0
Tony Lindgren4d963722008-07-03 12:24:31 +03001479 || chain_id >= dma_lch_count))) {
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001480 printk(KERN_ERR "Invalid chain id\n");
1481 return -EINVAL;
1482 }
1483
1484 /* Check if the chain exists */
1485 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1486 printk(KERN_ERR "Chain doesn't exist\n");
1487 return -EINVAL;
1488 }
1489
1490 /* Check if all the channels in chain are in use */
1491 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1492 return -EBUSY;
1493
1494 /* Frame count may be negative in case of indexed transfers */
1495 channels = dma_linked_lch[chain_id].linked_dmach_q;
1496
1497 /* Get a free channel */
1498 lch = channels[dma_linked_lch[chain_id].q_tail];
1499
1500 /* Store the callback data */
1501 dma_chan[lch].data = callbk_data;
1502
1503 /* Increment the q_tail */
1504 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1505
1506 /* Set the params to the free channel */
1507 if (src_start != 0)
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001508 p->dma_write(src_start, CSSA, lch);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001509 if (dest_start != 0)
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001510 p->dma_write(dest_start, CDSA, lch);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001511
1512 /* Write the buffer size */
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001513 p->dma_write(elem_count, CEN, lch);
1514 p->dma_write(frame_count, CFN, lch);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001515
Tony Lindgren97b7f712008-07-03 12:24:37 +03001516 /*
1517 * If the chain is dynamically linked,
1518 * then we may have to start the chain if its not active
1519 */
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001520 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1521
Tony Lindgren97b7f712008-07-03 12:24:37 +03001522 /*
1523 * In Dynamic chain, if the chain is not started,
1524 * queue the channel
1525 */
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001526 if (dma_linked_lch[chain_id].chain_state ==
1527 DMA_CHAIN_NOTSTARTED) {
1528 /* Enable the link in previous channel */
1529 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1530 DMA_CH_QUEUED)
1531 enable_lnk(dma_chan[lch].prev_linked_ch);
1532 dma_chan[lch].state = DMA_CH_QUEUED;
1533 }
1534
Tony Lindgren97b7f712008-07-03 12:24:37 +03001535 /*
1536 * Chain is already started, make sure its active,
1537 * if not then start the chain
1538 */
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001539 else {
1540 start_dma = 1;
1541
1542 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1543 DMA_CH_STARTED) {
1544 enable_lnk(dma_chan[lch].prev_linked_ch);
1545 dma_chan[lch].state = DMA_CH_QUEUED;
1546 start_dma = 0;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001547 if (0 == ((1 << 7) & p->dma_read(
G, Manjunath Kondaiaha4c537c2010-12-20 18:27:17 -08001548 CCR, dma_chan[lch].prev_linked_ch))) {
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001549 disable_lnk(dma_chan[lch].
1550 prev_linked_ch);
1551 pr_debug("\n prev ch is stopped\n");
1552 start_dma = 1;
1553 }
1554 }
1555
1556 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1557 == DMA_CH_QUEUED) {
1558 enable_lnk(dma_chan[lch].prev_linked_ch);
1559 dma_chan[lch].state = DMA_CH_QUEUED;
1560 start_dma = 0;
1561 }
1562 omap_enable_channel_irq(lch);
1563
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001564 l = p->dma_read(CCR, lch);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001565
Tony Lindgren0499bde2008-07-03 12:24:36 +03001566 if ((0 == (l & (1 << 24))))
1567 l &= ~(1 << 25);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001568 else
Tony Lindgren0499bde2008-07-03 12:24:36 +03001569 l |= (1 << 25);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001570 if (start_dma == 1) {
Tony Lindgren0499bde2008-07-03 12:24:36 +03001571 if (0 == (l & (1 << 7))) {
1572 l |= (1 << 7);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001573 dma_chan[lch].state = DMA_CH_STARTED;
1574 pr_debug("starting %d\n", lch);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001575 p->dma_write(l, CCR, lch);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001576 } else
1577 start_dma = 0;
1578 } else {
Tony Lindgren0499bde2008-07-03 12:24:36 +03001579 if (0 == (l & (1 << 7)))
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001580 p->dma_write(l, CCR, lch);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001581 }
1582 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1583 }
1584 }
Tony Lindgren97b7f712008-07-03 12:24:37 +03001585
Anand Gadiyarf4b6a7e2008-03-11 01:10:35 +05301586 return 0;
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001587}
1588EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1589
1590/**
1591 * @brief omap_start_dma_chain_transfers - Start the chain
1592 *
1593 * @param chain_id
1594 *
1595 * @return - Success : 0
1596 * Failure : -EINVAL/-EBUSY
1597 */
1598int omap_start_dma_chain_transfers(int chain_id)
1599{
1600 int *channels;
Tony Lindgren0499bde2008-07-03 12:24:36 +03001601 u32 l, i;
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001602
Tony Lindgren4d963722008-07-03 12:24:31 +03001603 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001604 printk(KERN_ERR "Invalid chain id\n");
1605 return -EINVAL;
1606 }
1607
1608 channels = dma_linked_lch[chain_id].linked_dmach_q;
1609
1610 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1611 printk(KERN_ERR "Chain is already started\n");
1612 return -EBUSY;
1613 }
1614
1615 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1616 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1617 i++) {
1618 enable_lnk(channels[i]);
1619 omap_enable_channel_irq(channels[i]);
1620 }
1621 } else {
1622 omap_enable_channel_irq(channels[0]);
1623 }
1624
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001625 l = p->dma_read(CCR, channels[0]);
Tony Lindgren0499bde2008-07-03 12:24:36 +03001626 l |= (1 << 7);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001627 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1628 dma_chan[channels[0]].state = DMA_CH_STARTED;
1629
Tony Lindgren0499bde2008-07-03 12:24:36 +03001630 if ((0 == (l & (1 << 24))))
1631 l &= ~(1 << 25);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001632 else
Tony Lindgren0499bde2008-07-03 12:24:36 +03001633 l |= (1 << 25);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001634 p->dma_write(l, CCR, channels[0]);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001635
1636 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
Tony Lindgren97b7f712008-07-03 12:24:37 +03001637
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001638 return 0;
1639}
1640EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1641
1642/**
1643 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1644 *
1645 * @param chain_id
1646 *
1647 * @return - Success : 0
1648 * Failure : EINVAL
1649 */
1650int omap_stop_dma_chain_transfers(int chain_id)
1651{
1652 int *channels;
Tony Lindgren0499bde2008-07-03 12:24:36 +03001653 u32 l, i;
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -08001654 u32 sys_cf = 0;
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001655
1656 /* Check for input params */
Tony Lindgren4d963722008-07-03 12:24:31 +03001657 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001658 printk(KERN_ERR "Invalid chain id\n");
1659 return -EINVAL;
1660 }
1661
1662 /* Check if the chain exists */
1663 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1664 printk(KERN_ERR "Chain doesn't exists\n");
1665 return -EINVAL;
1666 }
1667 channels = dma_linked_lch[chain_id].linked_dmach_q;
1668
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -08001669 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001670 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -08001671 l = sys_cf;
1672 /* Middle mode reg set no Standby */
1673 l &= ~((1 << 12)|(1 << 13));
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001674 p->dma_write(l, OCP_SYSCONFIG, 0);
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -08001675 }
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001676
1677 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1678
1679 /* Stop the Channel transmission */
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001680 l = p->dma_read(CCR, channels[i]);
Tony Lindgren0499bde2008-07-03 12:24:36 +03001681 l &= ~(1 << 7);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001682 p->dma_write(l, CCR, channels[i]);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001683
1684 /* Disable the link in all the channels */
1685 disable_lnk(channels[i]);
1686 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1687
1688 }
1689 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1690
1691 /* Reset the Queue pointers */
1692 OMAP_DMA_CHAIN_QINIT(chain_id);
1693
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -08001694 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001695 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
Tony Lindgren97b7f712008-07-03 12:24:37 +03001696
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001697 return 0;
1698}
1699EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1700
1701/* Get the index of the ongoing DMA in chain */
1702/**
1703 * @brief omap_get_dma_chain_index - Get the element and frame index
1704 * of the ongoing DMA in chain
1705 *
1706 * @param chain_id
1707 * @param ei - Element index
1708 * @param fi - Frame index
1709 *
1710 * @return - Success : 0
1711 * Failure : -EINVAL
1712 */
1713int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1714{
1715 int lch;
1716 int *channels;
1717
1718 /* Check for input params */
Tony Lindgren4d963722008-07-03 12:24:31 +03001719 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001720 printk(KERN_ERR "Invalid chain id\n");
1721 return -EINVAL;
1722 }
1723
1724 /* Check if the chain exists */
1725 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1726 printk(KERN_ERR "Chain doesn't exists\n");
1727 return -EINVAL;
1728 }
1729 if ((!ei) || (!fi))
1730 return -EINVAL;
1731
1732 channels = dma_linked_lch[chain_id].linked_dmach_q;
1733
1734 /* Get the current channel */
1735 lch = channels[dma_linked_lch[chain_id].q_head];
1736
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001737 *ei = p->dma_read(CCEN, lch);
1738 *fi = p->dma_read(CCFN, lch);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001739
1740 return 0;
1741}
1742EXPORT_SYMBOL(omap_get_dma_chain_index);
1743
1744/**
1745 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1746 * ongoing DMA in chain
1747 *
1748 * @param chain_id
1749 *
1750 * @return - Success : Destination position
1751 * Failure : -EINVAL
1752 */
1753int omap_get_dma_chain_dst_pos(int chain_id)
1754{
1755 int lch;
1756 int *channels;
1757
1758 /* Check for input params */
Tony Lindgren4d963722008-07-03 12:24:31 +03001759 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001760 printk(KERN_ERR "Invalid chain id\n");
1761 return -EINVAL;
1762 }
1763
1764 /* Check if the chain exists */
1765 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1766 printk(KERN_ERR "Chain doesn't exists\n");
1767 return -EINVAL;
1768 }
1769
1770 channels = dma_linked_lch[chain_id].linked_dmach_q;
1771
1772 /* Get the current channel */
1773 lch = channels[dma_linked_lch[chain_id].q_head];
1774
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001775 return p->dma_read(CDAC, lch);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001776}
1777EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1778
1779/**
1780 * @brief omap_get_dma_chain_src_pos - Get the source position
1781 * of the ongoing DMA in chain
1782 * @param chain_id
1783 *
1784 * @return - Success : Destination position
1785 * Failure : -EINVAL
1786 */
1787int omap_get_dma_chain_src_pos(int chain_id)
1788{
1789 int lch;
1790 int *channels;
1791
1792 /* Check for input params */
Tony Lindgren4d963722008-07-03 12:24:31 +03001793 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001794 printk(KERN_ERR "Invalid chain id\n");
1795 return -EINVAL;
1796 }
1797
1798 /* Check if the chain exists */
1799 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1800 printk(KERN_ERR "Chain doesn't exists\n");
1801 return -EINVAL;
1802 }
1803
1804 channels = dma_linked_lch[chain_id].linked_dmach_q;
1805
1806 /* Get the current channel */
1807 lch = channels[dma_linked_lch[chain_id].q_head];
1808
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001809 return p->dma_read(CSAC, lch);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001810}
1811EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
Tony Lindgren97b7f712008-07-03 12:24:37 +03001812#endif /* ifndef CONFIG_ARCH_OMAP1 */
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001813
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001814/*----------------------------------------------------------------------------*/
1815
1816#ifdef CONFIG_ARCH_OMAP1
1817
1818static int omap1_dma_handle_ch(int ch)
1819{
Tony Lindgren0499bde2008-07-03 12:24:36 +03001820 u32 csr;
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001821
1822 if (enable_1510_mode && ch >= 6) {
1823 csr = dma_chan[ch].saved_csr;
1824 dma_chan[ch].saved_csr = 0;
1825 } else
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001826 csr = p->dma_read(CSR, ch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001827 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1828 dma_chan[ch + 6].saved_csr = csr >> 7;
1829 csr &= 0x7f;
1830 }
1831 if ((csr & 0x3f) == 0)
1832 return 0;
1833 if (unlikely(dma_chan[ch].dev_id == -1)) {
1834 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1835 "%d (CSR %04x)\n", ch, csr);
1836 return 0;
1837 }
Tony Lindgren7ff879d2006-06-26 16:16:15 -07001838 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001839 printk(KERN_WARNING "DMA timeout with device %d\n",
1840 dma_chan[ch].dev_id);
1841 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1842 printk(KERN_WARNING "DMA synchronization event drop occurred "
1843 "with device %d\n", dma_chan[ch].dev_id);
1844 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1845 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1846 if (likely(dma_chan[ch].callback != NULL))
1847 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
Tony Lindgren97b7f712008-07-03 12:24:37 +03001848
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001849 return 1;
1850}
1851
Linus Torvalds0cd61b62006-10-06 10:53:39 -07001852static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001853{
1854 int ch = ((int) dev_id) - 1;
1855 int handled = 0;
1856
1857 for (;;) {
1858 int handled_now = 0;
1859
1860 handled_now += omap1_dma_handle_ch(ch);
1861 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1862 handled_now += omap1_dma_handle_ch(ch + 6);
1863 if (!handled_now)
1864 break;
1865 handled += handled_now;
1866 }
1867
1868 return handled ? IRQ_HANDLED : IRQ_NONE;
1869}
1870
1871#else
1872#define omap1_dma_irq_handler NULL
1873#endif
1874
Tony Lindgren140455f2010-02-12 12:26:48 -08001875#ifdef CONFIG_ARCH_OMAP2PLUS
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001876
1877static int omap2_dma_handle_ch(int ch)
1878{
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001879 u32 status = p->dma_read(CSR, ch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001880
Juha Yrjola31513692006-12-06 17:13:47 -08001881 if (!status) {
1882 if (printk_ratelimit())
Tony Lindgren97b7f712008-07-03 12:24:37 +03001883 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1884 ch);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001885 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001886 return 0;
Juha Yrjola31513692006-12-06 17:13:47 -08001887 }
1888 if (unlikely(dma_chan[ch].dev_id == -1)) {
1889 if (printk_ratelimit())
1890 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1891 "channel %d\n", status, ch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001892 return 0;
Juha Yrjola31513692006-12-06 17:13:47 -08001893 }
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001894 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1895 printk(KERN_INFO
1896 "DMA synchronization event drop occurred with device "
1897 "%d\n", dma_chan[ch].dev_id);
Santosh Shilimkara50f18c2008-12-10 17:36:53 -08001898 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001899 printk(KERN_INFO "DMA transaction error with device %d\n",
1900 dma_chan[ch].dev_id);
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -08001901 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
Santosh Shilimkara50f18c2008-12-10 17:36:53 -08001902 u32 ccr;
1903
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001904 ccr = p->dma_read(CCR, ch);
Santosh Shilimkara50f18c2008-12-10 17:36:53 -08001905 ccr &= ~OMAP_DMA_CCR_EN;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001906 p->dma_write(ccr, CCR, ch);
Santosh Shilimkara50f18c2008-12-10 17:36:53 -08001907 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1908 }
1909 }
Tony Lindgren7ff879d2006-06-26 16:16:15 -07001910 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1911 printk(KERN_INFO "DMA secure error with device %d\n",
1912 dma_chan[ch].dev_id);
1913 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1914 printk(KERN_INFO "DMA misaligned error with device %d\n",
1915 dma_chan[ch].dev_id);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001916
Adrian Hunter4fb699b2010-11-24 13:23:21 +02001917 p->dma_write(status, CSR, ch);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001918 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
Mathias Nymane860e6d2010-10-25 14:35:24 +00001919 /* read back the register to flush the write */
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001920 p->dma_read(IRQSTATUS_L0, ch);
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001921
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001922 /* If the ch is not chained then chain_id will be -1 */
1923 if (dma_chan[ch].chain_id != -1) {
1924 int chain_id = dma_chan[ch].chain_id;
1925 dma_chan[ch].state = DMA_CH_NOTSTARTED;
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001926 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001927 dma_chan[dma_chan[ch].next_linked_ch].state =
1928 DMA_CH_STARTED;
1929 if (dma_linked_lch[chain_id].chain_mode ==
1930 OMAP_DMA_DYNAMIC_CHAIN)
1931 disable_lnk(ch);
1932
1933 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1934 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1935
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001936 status = p->dma_read(CSR, ch);
Adrian Hunter4fb699b2010-11-24 13:23:21 +02001937 p->dma_write(status, CSR, ch);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001938 }
1939
Jarkko Nikula538528d2008-02-13 11:47:29 +02001940 if (likely(dma_chan[ch].callback != NULL))
1941 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
Anand Gadiyarf8151e52007-12-01 12:14:11 -08001942
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001943 return 0;
1944}
1945
1946/* STATUS register count is from 1-32 while our is 0-31 */
Linus Torvalds0cd61b62006-10-06 10:53:39 -07001947static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001948{
Santosh Shilimkar52176e72009-03-23 18:07:49 -07001949 u32 val, enable_reg;
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001950 int i;
1951
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001952 val = p->dma_read(IRQSTATUS_L0, 0);
Juha Yrjola31513692006-12-06 17:13:47 -08001953 if (val == 0) {
1954 if (printk_ratelimit())
1955 printk(KERN_WARNING "Spurious DMA IRQ\n");
1956 return IRQ_HANDLED;
1957 }
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001958 enable_reg = p->dma_read(IRQENABLE_L0, 0);
Santosh Shilimkar52176e72009-03-23 18:07:49 -07001959 val &= enable_reg; /* Dispatch only relevant interrupts */
Tony Lindgren4d963722008-07-03 12:24:31 +03001960 for (i = 0; i < dma_lch_count && val != 0; i++) {
Juha Yrjola31513692006-12-06 17:13:47 -08001961 if (val & 1)
1962 omap2_dma_handle_ch(i);
1963 val >>= 1;
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001964 }
1965
1966 return IRQ_HANDLED;
1967}
1968
1969static struct irqaction omap24xx_dma_irq = {
1970 .name = "DMA",
1971 .handler = omap2_dma_irq_handler,
Thomas Gleixner52e405e2006-07-03 02:20:05 +02001972 .flags = IRQF_DISABLED
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00001973};
1974
1975#else
1976static struct irqaction omap24xx_dma_irq;
1977#endif
1978
1979/*----------------------------------------------------------------------------*/
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001980
Tero Kristof2d11852008-08-28 13:13:31 +00001981void omap_dma_global_context_save(void)
1982{
1983 omap_dma_global_context.dma_irqenable_l0 =
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001984 p->dma_read(IRQENABLE_L0, 0);
Tero Kristof2d11852008-08-28 13:13:31 +00001985 omap_dma_global_context.dma_ocp_sysconfig =
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001986 p->dma_read(OCP_SYSCONFIG, 0);
1987 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
Tero Kristof2d11852008-08-28 13:13:31 +00001988}
1989
1990void omap_dma_global_context_restore(void)
1991{
Aaro Koskinenbf07c9f2009-05-20 16:58:30 +03001992 int ch;
1993
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001994 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1995 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
G, Manjunath Kondaiaha4c537c2010-12-20 18:27:17 -08001996 OCP_SYSCONFIG, 0);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08001997 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
G, Manjunath Kondaiaha4c537c2010-12-20 18:27:17 -08001998 IRQENABLE_L0, 0);
Tero Kristof2d11852008-08-28 13:13:31 +00001999
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -08002000 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002001 p->dma_write(0x3 , IRQSTATUS_L0, 0);
Aaro Koskinenbf07c9f2009-05-20 16:58:30 +03002002
2003 for (ch = 0; ch < dma_chan_count; ch++)
2004 if (dma_chan[ch].dev_id != -1)
2005 omap_clear_dma(ch);
Tero Kristof2d11852008-08-28 13:13:31 +00002006}
2007
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002008static int __devinit omap_system_dma_probe(struct platform_device *pdev)
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -08002009{
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002010 int ch, ret = 0;
2011 int dma_irq;
2012 char irq_name[4];
2013 int irq_rel;
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -08002014
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002015 p = pdev->dev.platform_data;
2016 if (!p) {
2017 dev_err(&pdev->dev, "%s: System DMA initialized without"
2018 "platform data\n", __func__);
2019 return -EINVAL;
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -08002020 }
2021
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002022 d = p->dma_attr;
2023 errata = p->errata;
G, Manjunath Kondaiahd3c9be22010-12-20 18:27:18 -08002024
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002025 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
Santosh Shilimkar2263f022009-03-23 18:07:48 -07002026 && (omap_dma_reserve_channels <= dma_lch_count))
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002027 d->lch_count = omap_dma_reserve_channels;
Santosh Shilimkar2263f022009-03-23 18:07:48 -07002028
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002029 dma_lch_count = d->lch_count;
2030 dma_chan_count = dma_lch_count;
2031 dma_chan = d->chan;
2032 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
Tony Lindgren4d963722008-07-03 12:24:31 +03002033
2034 if (cpu_class_is_omap2()) {
2035 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2036 dma_lch_count, GFP_KERNEL);
2037 if (!dma_linked_lch) {
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002038 ret = -ENOMEM;
2039 goto exit_dma_lch_fail;
Tony Lindgren4d963722008-07-03 12:24:31 +03002040 }
2041 }
2042
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01002043 spin_lock_init(&dma_chan_lock);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01002044 for (ch = 0; ch < dma_chan_count; ch++) {
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00002045 omap_clear_dma(ch);
Mika Westerbergada8d4a2010-05-14 12:05:25 -07002046 if (cpu_class_is_omap2())
2047 omap2_disable_irq_lch(ch);
2048
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01002049 dma_chan[ch].dev_id = -1;
2050 dma_chan[ch].next_lch = -1;
2051
2052 if (ch >= 6 && enable_1510_mode)
2053 continue;
2054
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00002055 if (cpu_class_is_omap1()) {
Tony Lindgren97b7f712008-07-03 12:24:37 +03002056 /*
2057 * request_irq() doesn't like dev_id (ie. ch) being
2058 * zero, so we have to kludge around this.
2059 */
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002060 sprintf(&irq_name[0], "%d", ch);
2061 dma_irq = platform_get_irq_byname(pdev, irq_name);
2062
2063 if (dma_irq < 0) {
2064 ret = dma_irq;
2065 goto exit_dma_irq_fail;
2066 }
2067
2068 /* INT_DMA_LCD is handled in lcd_dma.c */
2069 if (dma_irq == INT_DMA_LCD)
2070 continue;
2071
2072 ret = request_irq(dma_irq,
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00002073 omap1_dma_irq_handler, 0, "DMA",
2074 (void *) (ch + 1));
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002075 if (ret != 0)
2076 goto exit_dma_irq_fail;
Tony Lindgren1a8bfa12005-11-10 14:26:50 +00002077 }
2078 }
2079
Santosh Shilimkard07c3df2012-04-28 20:19:10 +05302080 if (cpu_class_is_omap2() && !cpu_is_omap242x())
Anand Gadiyarf8151e52007-12-01 12:14:11 -08002081 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2082 DMA_DEFAULT_FIFO_DEPTH, 0);
2083
Santosh Shilimkar44169072009-05-28 14:16:04 -07002084 if (cpu_class_is_omap2()) {
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002085 strcpy(irq_name, "0");
2086 dma_irq = platform_get_irq_byname(pdev, irq_name);
2087 if (dma_irq < 0) {
2088 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2089 goto exit_dma_lch_fail;
2090 }
2091 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2092 if (ret) {
2093 dev_err(&pdev->dev, "set_up failed for IRQ %d"
2094 "for DMA (error %d)\n", dma_irq, ret);
2095 goto exit_dma_lch_fail;
Kalle Jokiniemiba50ea72009-03-26 15:59:00 +02002096 }
Kalle Jokiniemiaecedb92009-06-23 13:30:24 +03002097 }
2098
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002099 /* reserve dma channels 0 and 1 in high security devices */
2100 if (cpu_is_omap34xx() &&
2101 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2102 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2103 "HS ROM code\n");
2104 dma_chan[0].dev_id = 0;
2105 dma_chan[1].dev_id = 1;
2106 }
2107 p->show_dma_caps();
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01002108 return 0;
Tony Lindgren7e9bf842009-10-19 15:25:15 -07002109
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002110exit_dma_irq_fail:
2111 dev_err(&pdev->dev, "unable to request IRQ %d"
2112 "for DMA (error %d)\n", dma_irq, ret);
2113 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2114 dma_irq = platform_get_irq(pdev, irq_rel);
2115 free_irq(dma_irq, (void *)(irq_rel + 1));
2116 }
2117
2118exit_dma_lch_fail:
2119 kfree(p);
2120 kfree(d);
Tony Lindgren7e9bf842009-10-19 15:25:15 -07002121 kfree(dma_chan);
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002122 return ret;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01002123}
2124
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002125static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2126{
2127 int dma_irq;
2128
2129 if (cpu_class_is_omap2()) {
2130 char irq_name[4];
2131 strcpy(irq_name, "0");
2132 dma_irq = platform_get_irq_byname(pdev, irq_name);
2133 remove_irq(dma_irq, &omap24xx_dma_irq);
2134 } else {
2135 int irq_rel = 0;
2136 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2137 dma_irq = platform_get_irq(pdev, irq_rel);
2138 free_irq(dma_irq, (void *)(irq_rel + 1));
2139 }
2140 }
2141 kfree(p);
2142 kfree(d);
2143 kfree(dma_chan);
2144 return 0;
2145}
2146
2147static struct platform_driver omap_system_dma_driver = {
2148 .probe = omap_system_dma_probe,
Tony Lindgren3e2e6132012-02-23 14:58:08 -08002149 .remove = __devexit_p(omap_system_dma_remove),
G, Manjunath Kondaiahf31cc962010-12-20 18:27:19 -08002150 .driver = {
2151 .name = "omap_dma_system"
2152 },
2153};
2154
2155static int __init omap_system_dma_init(void)
2156{
2157 return platform_driver_register(&omap_system_dma_driver);
2158}
2159arch_initcall(omap_system_dma_init);
2160
2161static void __exit omap_system_dma_exit(void)
2162{
2163 platform_driver_unregister(&omap_system_dma_driver);
2164}
2165
2166MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2167MODULE_LICENSE("GPL");
2168MODULE_ALIAS("platform:" DRIVER_NAME);
2169MODULE_AUTHOR("Texas Instruments Inc");
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01002170
Santosh Shilimkar2263f022009-03-23 18:07:48 -07002171/*
2172 * Reserve the omap SDMA channels using cmdline bootarg
2173 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2174 */
2175static int __init omap_dma_cmdline_reserve_ch(char *str)
2176{
2177 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2178 omap_dma_reserve_channels = 0;
2179 return 1;
2180}
2181
2182__setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2183
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01002184