Pawel Moll | bfd5200 | 2011-12-09 18:41:27 +0000 | [diff] [blame] | 1 | /* |
| 2 | * ARM Ltd. Versatile Express |
| 3 | * |
| 4 | * CoreTile Express A5x2 |
| 5 | * Cortex-A5 MPCore (V2P-CA5s) |
| 6 | * |
| 7 | * HBI-0225B |
| 8 | */ |
| 9 | |
| 10 | /dts-v1/; |
| 11 | |
| 12 | / { |
| 13 | model = "V2P-CA5s"; |
| 14 | arm,hbi = <0x225>; |
| 15 | compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; |
| 16 | interrupt-parent = <&gic>; |
| 17 | #address-cells = <1>; |
| 18 | #size-cells = <1>; |
| 19 | |
| 20 | chosen { }; |
| 21 | |
| 22 | aliases { |
| 23 | serial0 = &v2m_serial0; |
| 24 | serial1 = &v2m_serial1; |
| 25 | serial2 = &v2m_serial2; |
| 26 | serial3 = &v2m_serial3; |
| 27 | i2c0 = &v2m_i2c_dvi; |
| 28 | i2c1 = &v2m_i2c_pcie; |
| 29 | }; |
| 30 | |
| 31 | cpus { |
| 32 | #address-cells = <1>; |
| 33 | #size-cells = <0>; |
| 34 | |
| 35 | cpu@0 { |
| 36 | device_type = "cpu"; |
| 37 | compatible = "arm,cortex-a5"; |
| 38 | reg = <0>; |
| 39 | next-level-cache = <&L2>; |
| 40 | }; |
| 41 | |
| 42 | cpu@1 { |
| 43 | device_type = "cpu"; |
| 44 | compatible = "arm,cortex-a5"; |
| 45 | reg = <1>; |
| 46 | next-level-cache = <&L2>; |
| 47 | }; |
| 48 | }; |
| 49 | |
| 50 | memory@80000000 { |
| 51 | device_type = "memory"; |
| 52 | reg = <0x80000000 0x40000000>; |
| 53 | }; |
| 54 | |
| 55 | hdlcd@2a110000 { |
| 56 | compatible = "arm,hdlcd"; |
| 57 | reg = <0x2a110000 0x1000>; |
| 58 | interrupts = <0 85 4>; |
| 59 | }; |
| 60 | |
| 61 | memory-controller@2a150000 { |
| 62 | compatible = "arm,pl341", "arm,primecell"; |
| 63 | reg = <0x2a150000 0x1000>; |
| 64 | }; |
| 65 | |
| 66 | memory-controller@2a190000 { |
| 67 | compatible = "arm,pl354", "arm,primecell"; |
| 68 | reg = <0x2a190000 0x1000>; |
| 69 | interrupts = <0 86 4>, |
| 70 | <0 87 4>; |
| 71 | }; |
| 72 | |
| 73 | scu@2c000000 { |
| 74 | compatible = "arm,cortex-a5-scu"; |
| 75 | reg = <0x2c000000 0x58>; |
| 76 | }; |
| 77 | |
| 78 | timer@2c000600 { |
| 79 | compatible = "arm,cortex-a5-twd-timer"; |
Pawel Moll | e29b65d | 2012-05-10 17:12:07 +0100 | [diff] [blame] | 80 | reg = <0x2c000600 0x20>; |
| 81 | interrupts = <1 13 0x304>; |
| 82 | }; |
| 83 | |
| 84 | watchdog@2c000620 { |
| 85 | compatible = "arm,cortex-a5-twd-wdt"; |
| 86 | reg = <0x2c000620 0x20>; |
| 87 | interrupts = <1 14 0x304>; |
Pawel Moll | bfd5200 | 2011-12-09 18:41:27 +0000 | [diff] [blame] | 88 | }; |
| 89 | |
| 90 | gic: interrupt-controller@2c001000 { |
Pawel Moll | e29b65d | 2012-05-10 17:12:07 +0100 | [diff] [blame] | 91 | compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic"; |
Pawel Moll | bfd5200 | 2011-12-09 18:41:27 +0000 | [diff] [blame] | 92 | #interrupt-cells = <3>; |
| 93 | #address-cells = <0>; |
| 94 | interrupt-controller; |
| 95 | reg = <0x2c001000 0x1000>, |
| 96 | <0x2c000100 0x100>; |
| 97 | }; |
| 98 | |
| 99 | L2: cache-controller@2c0f0000 { |
| 100 | compatible = "arm,pl310-cache"; |
| 101 | reg = <0x2c0f0000 0x1000>; |
| 102 | interrupts = <0 84 4>; |
| 103 | cache-level = <2>; |
| 104 | }; |
| 105 | |
| 106 | pmu { |
| 107 | compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu"; |
| 108 | interrupts = <0 68 4>, |
| 109 | <0 69 4>; |
| 110 | }; |
| 111 | |
| 112 | motherboard { |
| 113 | ranges = <0 0 0x08000000 0x04000000>, |
| 114 | <1 0 0x14000000 0x04000000>, |
| 115 | <2 0 0x18000000 0x04000000>, |
| 116 | <3 0 0x1c000000 0x04000000>, |
| 117 | <4 0 0x0c000000 0x04000000>, |
| 118 | <5 0 0x10000000 0x04000000>; |
| 119 | |
| 120 | interrupt-map-mask = <0 0 63>; |
| 121 | interrupt-map = <0 0 0 &gic 0 0 4>, |
| 122 | <0 0 1 &gic 0 1 4>, |
| 123 | <0 0 2 &gic 0 2 4>, |
| 124 | <0 0 3 &gic 0 3 4>, |
| 125 | <0 0 4 &gic 0 4 4>, |
| 126 | <0 0 5 &gic 0 5 4>, |
| 127 | <0 0 6 &gic 0 6 4>, |
| 128 | <0 0 7 &gic 0 7 4>, |
| 129 | <0 0 8 &gic 0 8 4>, |
| 130 | <0 0 9 &gic 0 9 4>, |
| 131 | <0 0 10 &gic 0 10 4>, |
| 132 | <0 0 11 &gic 0 11 4>, |
| 133 | <0 0 12 &gic 0 12 4>, |
| 134 | <0 0 13 &gic 0 13 4>, |
| 135 | <0 0 14 &gic 0 14 4>, |
| 136 | <0 0 15 &gic 0 15 4>, |
| 137 | <0 0 16 &gic 0 16 4>, |
| 138 | <0 0 17 &gic 0 17 4>, |
| 139 | <0 0 18 &gic 0 18 4>, |
| 140 | <0 0 19 &gic 0 19 4>, |
| 141 | <0 0 20 &gic 0 20 4>, |
| 142 | <0 0 21 &gic 0 21 4>, |
| 143 | <0 0 22 &gic 0 22 4>, |
| 144 | <0 0 23 &gic 0 23 4>, |
| 145 | <0 0 24 &gic 0 24 4>, |
| 146 | <0 0 25 &gic 0 25 4>, |
| 147 | <0 0 26 &gic 0 26 4>, |
| 148 | <0 0 27 &gic 0 27 4>, |
| 149 | <0 0 28 &gic 0 28 4>, |
| 150 | <0 0 29 &gic 0 29 4>, |
| 151 | <0 0 30 &gic 0 30 4>, |
| 152 | <0 0 31 &gic 0 31 4>, |
| 153 | <0 0 32 &gic 0 32 4>, |
| 154 | <0 0 33 &gic 0 33 4>, |
| 155 | <0 0 34 &gic 0 34 4>, |
| 156 | <0 0 35 &gic 0 35 4>, |
| 157 | <0 0 36 &gic 0 36 4>, |
| 158 | <0 0 37 &gic 0 37 4>, |
| 159 | <0 0 38 &gic 0 38 4>, |
| 160 | <0 0 39 &gic 0 39 4>, |
| 161 | <0 0 40 &gic 0 40 4>, |
| 162 | <0 0 41 &gic 0 41 4>, |
| 163 | <0 0 42 &gic 0 42 4>; |
| 164 | }; |
| 165 | }; |
| 166 | |
| 167 | /include/ "vexpress-v2m-rs1.dtsi" |