Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This program is free software; you can redistribute it and/or modify |
| 3 | * it under the terms of the GNU General Public License as published by |
| 4 | * the Free Software Foundation; either version 2 of the License, or |
| 5 | * (at your option) any later version. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | * You should have received a copy of the GNU General Public License |
| 13 | * along with this program; if not, write to the Free Software |
| 14 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 15 | */ |
| 16 | /* DO NOT EDIT!! - this file automatically generated |
| 17 | * from .s file by awk -f s2h.awk |
| 18 | */ |
| 19 | /************************************************************************** |
John Anthony Kazos Jr | 121e70b | 2007-05-09 08:30:57 +0200 | [diff] [blame] | 20 | * * Copyright © ARM Limited 1998. All rights reserved. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | * ***********************************************************************/ |
| 22 | /* ************************************************************************ |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 23 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | * Integrator address map |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 25 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | * NOTE: This is a multi-hosted header file for use with uHAL and |
| 27 | * supported debuggers. |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 28 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | * ***********************************************************************/ |
| 30 | |
| 31 | #ifndef __address_h |
| 32 | #define __address_h 1 |
| 33 | |
| 34 | /* ======================================================================== |
| 35 | * Integrator definitions |
| 36 | * ======================================================================== |
| 37 | * ------------------------------------------------------------------------ |
| 38 | * Memory definitions |
| 39 | * ------------------------------------------------------------------------ |
| 40 | * Integrator memory map |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 41 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | */ |
| 43 | #define INTEGRATOR_BOOT_ROM_LO 0x00000000 |
| 44 | #define INTEGRATOR_BOOT_ROM_HI 0x20000000 |
| 45 | #define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */ |
| 46 | #define INTEGRATOR_BOOT_ROM_SIZE SZ_512K |
| 47 | |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 48 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | * New Core Modules have different amounts of SSRAM, the amount of SSRAM |
| 50 | * fitted can be found in HDR_STAT. |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 51 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to |
| 53 | * the minimum amount of SSRAM fitted on any core module. |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 54 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | * New Core Modules also alias the SSRAM. |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 56 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 57 | */ |
| 58 | #define INTEGRATOR_SSRAM_BASE 0x00000000 |
| 59 | #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000 |
| 60 | #define INTEGRATOR_SSRAM_SIZE SZ_256K |
| 61 | |
| 62 | #define INTEGRATOR_FLASH_BASE 0x24000000 |
| 63 | #define INTEGRATOR_FLASH_SIZE SZ_32M |
| 64 | |
| 65 | #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000 |
| 66 | #define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K |
| 67 | |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 68 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | * SDRAM is a SIMM therefore the size is not known. |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 70 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | */ |
| 72 | #define INTEGRATOR_SDRAM_BASE 0x00040000 |
| 73 | |
| 74 | #define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000 |
| 75 | #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 |
| 76 | #define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000 |
| 77 | #define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000 |
| 78 | #define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000 |
| 79 | |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 80 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 81 | * Logic expansion modules |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 82 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | */ |
| 84 | #define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000 |
| 85 | #define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000 |
| 86 | #define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000 |
| 87 | #define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000 |
| 88 | #define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000 |
| 89 | |
| 90 | /* ------------------------------------------------------------------------ |
| 91 | * Integrator header card registers |
| 92 | * ------------------------------------------------------------------------ |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 93 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 94 | */ |
| 95 | #define INTEGRATOR_HDR_ID_OFFSET 0x00 |
| 96 | #define INTEGRATOR_HDR_PROC_OFFSET 0x04 |
| 97 | #define INTEGRATOR_HDR_OSC_OFFSET 0x08 |
| 98 | #define INTEGRATOR_HDR_CTRL_OFFSET 0x0C |
| 99 | #define INTEGRATOR_HDR_STAT_OFFSET 0x10 |
| 100 | #define INTEGRATOR_HDR_LOCK_OFFSET 0x14 |
| 101 | #define INTEGRATOR_HDR_SDRAM_OFFSET 0x20 |
| 102 | #define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */ |
| 103 | #define INTEGRATOR_HDR_IC_OFFSET 0x40 |
| 104 | #define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100 |
| 105 | #define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200 |
| 106 | |
| 107 | #define INTEGRATOR_HDR_BASE 0x10000000 |
| 108 | #define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET) |
| 109 | #define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET) |
| 110 | #define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET) |
| 111 | #define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET) |
| 112 | #define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET) |
| 113 | #define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET) |
| 114 | #define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET) |
| 115 | #define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET) |
| 116 | #define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET) |
| 117 | #define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET) |
| 118 | #define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET) |
| 119 | |
| 120 | #define INTEGRATOR_HDR_CTRL_LED 0x01 |
| 121 | #define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02 |
| 122 | #define INTEGRATOR_HDR_CTRL_REMAP 0x04 |
| 123 | #define INTEGRATOR_HDR_CTRL_RESET 0x08 |
| 124 | #define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10 |
| 125 | #define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20 |
| 126 | #define INTEGRATOR_HDR_CTRL_FASTBUS 0x40 |
| 127 | #define INTEGRATOR_HDR_CTRL_SYNC 0x80 |
| 128 | |
| 129 | #define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102 |
| 130 | #define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107 |
| 131 | #define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C |
| 132 | #define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111 |
| 133 | #define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116 |
| 134 | #define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B |
| 135 | #define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120 |
| 136 | #define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125 |
| 137 | #define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A |
| 138 | #define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F |
| 139 | #define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134 |
| 140 | #define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139 |
| 141 | #define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E |
| 142 | #define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143 |
| 143 | #define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148 |
| 144 | #define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D |
| 145 | #define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152 |
| 146 | #define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157 |
| 147 | #define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C |
| 148 | #define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161 |
| 149 | #define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166 |
| 150 | #define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B |
| 151 | #define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170 |
| 152 | #define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175 |
| 153 | #define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A |
| 154 | #define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F |
| 155 | #define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184 |
| 156 | #define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189 |
| 157 | #define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E |
| 158 | #define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193 |
| 159 | #define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198 |
| 160 | #define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF |
| 161 | |
| 162 | #define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000 |
| 163 | #define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000 |
| 164 | #define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000 |
| 165 | #define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000 |
| 166 | #define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000 |
| 167 | #define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000 |
| 168 | #define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000 |
| 169 | #define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000 |
| 170 | #define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000 |
| 171 | #define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000 |
| 172 | #define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000 |
| 173 | |
| 174 | #define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0 |
| 175 | #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000 |
| 176 | #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000 |
| 177 | #define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000 |
| 178 | #define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000 |
| 179 | |
| 180 | #define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5) |
| 181 | |
| 182 | |
| 183 | /* ------------------------------------------------------------------------ |
| 184 | * Integrator system registers |
| 185 | * ------------------------------------------------------------------------ |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 186 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 187 | */ |
| 188 | |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 189 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 190 | * System Controller |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 191 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 192 | */ |
| 193 | #define INTEGRATOR_SC_ID_OFFSET 0x00 |
| 194 | #define INTEGRATOR_SC_OSC_OFFSET 0x04 |
| 195 | #define INTEGRATOR_SC_CTRLS_OFFSET 0x08 |
| 196 | #define INTEGRATOR_SC_CTRLC_OFFSET 0x0C |
| 197 | #define INTEGRATOR_SC_DEC_OFFSET 0x10 |
| 198 | #define INTEGRATOR_SC_ARB_OFFSET 0x14 |
| 199 | #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 |
| 200 | #define INTEGRATOR_SC_LOCK_OFFSET 0x1C |
| 201 | |
| 202 | #define INTEGRATOR_SC_BASE 0x11000000 |
| 203 | #define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET) |
| 204 | #define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET) |
| 205 | #define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET) |
| 206 | #define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET) |
| 207 | #define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET) |
| 208 | #define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET) |
| 209 | #define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) |
| 210 | #define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET) |
| 211 | |
| 212 | #define INTEGRATOR_SC_OSC_SYS_10MHz 0x20 |
| 213 | #define INTEGRATOR_SC_OSC_SYS_15MHz 0x34 |
| 214 | #define INTEGRATOR_SC_OSC_SYS_20MHz 0x48 |
| 215 | #define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C |
| 216 | #define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C |
| 217 | #define INTEGRATOR_SC_OSC_SYS_MASK 0xFF |
| 218 | |
| 219 | #define INTEGRATOR_SC_OSC_PCI_25MHz 0x100 |
| 220 | #define INTEGRATOR_SC_OSC_PCI_33MHz 0x0 |
| 221 | #define INTEGRATOR_SC_OSC_PCI_MASK 0x100 |
| 222 | |
| 223 | #define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0) |
| 224 | #define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1) |
| 225 | #define INTEGRATOR_SC_CTRL_nFLWP (1 << 2) |
| 226 | #define INTEGRATOR_SC_CTRL_URTS0 (1 << 4) |
| 227 | #define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5) |
| 228 | #define INTEGRATOR_SC_CTRL_URTS1 (1 << 6) |
| 229 | #define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7) |
| 230 | |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 231 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 232 | * External Bus Interface |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 233 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 234 | */ |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 235 | #define INTEGRATOR_EBI_BASE 0x12000000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | |
| 237 | #define INTEGRATOR_EBI_CSR0_OFFSET 0x00 |
| 238 | #define INTEGRATOR_EBI_CSR1_OFFSET 0x04 |
| 239 | #define INTEGRATOR_EBI_CSR2_OFFSET 0x08 |
| 240 | #define INTEGRATOR_EBI_CSR3_OFFSET 0x0C |
| 241 | #define INTEGRATOR_EBI_LOCK_OFFSET 0x20 |
| 242 | |
| 243 | #define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET) |
| 244 | #define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) |
| 245 | #define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET) |
| 246 | #define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET) |
| 247 | #define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) |
| 248 | |
| 249 | #define INTEGRATOR_EBI_8_BIT 0x00 |
| 250 | #define INTEGRATOR_EBI_16_BIT 0x01 |
| 251 | #define INTEGRATOR_EBI_32_BIT 0x02 |
| 252 | #define INTEGRATOR_EBI_WRITE_ENABLE 0x04 |
| 253 | #define INTEGRATOR_EBI_SYNC 0x08 |
| 254 | #define INTEGRATOR_EBI_WS_2 0x00 |
| 255 | #define INTEGRATOR_EBI_WS_3 0x10 |
| 256 | #define INTEGRATOR_EBI_WS_4 0x20 |
| 257 | #define INTEGRATOR_EBI_WS_5 0x30 |
| 258 | #define INTEGRATOR_EBI_WS_6 0x40 |
| 259 | #define INTEGRATOR_EBI_WS_7 0x50 |
| 260 | #define INTEGRATOR_EBI_WS_8 0x60 |
| 261 | #define INTEGRATOR_EBI_WS_9 0x70 |
| 262 | #define INTEGRATOR_EBI_WS_10 0x80 |
| 263 | #define INTEGRATOR_EBI_WS_11 0x90 |
| 264 | #define INTEGRATOR_EBI_WS_12 0xA0 |
| 265 | #define INTEGRATOR_EBI_WS_13 0xB0 |
| 266 | #define INTEGRATOR_EBI_WS_14 0xC0 |
| 267 | #define INTEGRATOR_EBI_WS_15 0xD0 |
| 268 | #define INTEGRATOR_EBI_WS_16 0xE0 |
| 269 | #define INTEGRATOR_EBI_WS_17 0xF0 |
| 270 | |
| 271 | |
| 272 | #define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */ |
| 273 | #define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */ |
| 274 | #define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */ |
| 275 | #define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */ |
| 276 | #define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */ |
| 277 | #define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */ |
| 278 | #define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */ |
| 279 | |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 280 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 281 | * LED's & Switches |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 282 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 283 | */ |
| 284 | #define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 |
| 285 | #define INTEGRATOR_DBG_LEDS_OFFSET 0x04 |
| 286 | #define INTEGRATOR_DBG_SWITCH_OFFSET 0x08 |
| 287 | |
| 288 | #define INTEGRATOR_DBG_BASE 0x1A000000 |
| 289 | #define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET) |
| 290 | #define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET) |
| 291 | #define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET) |
| 292 | |
| 293 | |
Catalin Marinas | fea7722 | 2005-06-16 18:01:11 +0100 | [diff] [blame] | 294 | #if defined(CONFIG_ARCH_INTEGRATOR_AP) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 295 | #define INTEGRATOR_GPIO_BASE 0x1B000000 /* GPIO */ |
Catalin Marinas | fea7722 | 2005-06-16 18:01:11 +0100 | [diff] [blame] | 296 | #elif defined(CONFIG_ARCH_INTEGRATOR_CP) |
| 297 | #define INTEGRATOR_GPIO_BASE 0xC9000000 /* GPIO */ |
| 298 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | |
| 300 | /* ------------------------------------------------------------------------ |
| 301 | * KMI keyboard/mouse definitions |
| 302 | * ------------------------------------------------------------------------ |
| 303 | */ |
| 304 | /* PS2 Keyboard interface */ |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 305 | #define KMI0_BASE INTEGRATOR_KBD_BASE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 306 | |
| 307 | /* PS2 Mouse interface */ |
| 308 | #define KMI1_BASE INTEGRATOR_MOUSE_BASE |
| 309 | |
| 310 | /* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */ |
| 311 | |
| 312 | /* ------------------------------------------------------------------------ |
| 313 | * Where in the memory map does PCI live? |
| 314 | * ------------------------------------------------------------------------ |
| 315 | * This represents a fairly liberal usage of address space. Even though |
| 316 | * the V3 only has two windows (therefore we need to map stuff on the fly), |
| 317 | * we maintain the same addresses, even if they're not mapped. |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 318 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 319 | */ |
| 320 | #define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */ |
| 321 | /* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? |
| 322 | */ |
| 323 | #define PHYS_PCI_IO_BASE 0x60000000 /* 16M to xxx */ |
| 324 | /* unused (128-16)M from B1000000-B7FFFFFF |
| 325 | */ |
| 326 | #define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ |
| 327 | /* unused ((128-16)M - 64K) from XXX |
| 328 | */ |
| 329 | #define PHYS_PCI_V3_BASE 0x62000000 |
| 330 | |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 331 | #define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 332 | |
| 333 | /* 'export' these to UHAL */ |
| 334 | #define UHAL_PCI_IO PCI_IO_BASE |
| 335 | #define UHAL_PCI_MEM PCI_MEM_BASE |
| 336 | #define UHAL_PCI_ALLOC_IO_BASE 0x00004000 |
| 337 | #define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE |
| 338 | #define UHAL_PCI_MAX_SLOT 20 |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 339 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 340 | /* ======================================================================== |
| 341 | * Start of uHAL definitions |
| 342 | * ======================================================================== |
| 343 | */ |
| 344 | |
| 345 | /* ------------------------------------------------------------------------ |
| 346 | * Integrator Interrupt Controllers |
| 347 | * ------------------------------------------------------------------------ |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 348 | * |
| 349 | * Offsets from interrupt controller base |
| 350 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 351 | * System Controller interrupt controller base is |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 352 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 353 | * INTEGRATOR_IC_BASE + (header_number << 6) |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 354 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 355 | * Core Module interrupt controller base is |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 356 | * |
| 357 | * INTEGRATOR_HDR_IC |
| 358 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 359 | */ |
| 360 | #define IRQ_STATUS 0 |
| 361 | #define IRQ_RAW_STATUS 0x04 |
| 362 | #define IRQ_ENABLE 0x08 |
| 363 | #define IRQ_ENABLE_SET 0x08 |
| 364 | #define IRQ_ENABLE_CLEAR 0x0C |
| 365 | |
| 366 | #define INT_SOFT_SET 0x10 |
| 367 | #define INT_SOFT_CLEAR 0x14 |
| 368 | |
| 369 | #define FIQ_STATUS 0x20 |
| 370 | #define FIQ_RAW_STATUS 0x24 |
| 371 | #define FIQ_ENABLE 0x28 |
| 372 | #define FIQ_ENABLE_SET 0x28 |
| 373 | #define FIQ_ENABLE_CLEAR 0x2C |
| 374 | |
| 375 | |
| 376 | /* ------------------------------------------------------------------------ |
| 377 | * Interrupts |
| 378 | * ------------------------------------------------------------------------ |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 379 | * |
| 380 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 381 | * Each Core Module has two interrupts controllers, one on the core module |
| 382 | * itself and one in the system controller on the motherboard. The |
| 383 | * READ_INT macro in target.s reads both interrupt controllers and returns |
| 384 | * a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller |
| 385 | * and bits 24 to 31 are from the core module. |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 386 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 387 | * The following definitions relate to the bitmask returned by READ_INT. |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 388 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 389 | */ |
| 390 | |
| 391 | /* ------------------------------------------------------------------------ |
| 392 | * LED's - The header LED is not accessible via the uHAL API |
| 393 | * ------------------------------------------------------------------------ |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 394 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | */ |
| 396 | #define GREEN_LED 0x01 |
| 397 | #define YELLOW_LED 0x02 |
| 398 | #define RED_LED 0x04 |
| 399 | #define GREEN_LED_2 0x08 |
| 400 | #define ALL_LEDS 0x0F |
| 401 | |
| 402 | #define LED_BANK INTEGRATOR_DBG_LEDS |
| 403 | |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 404 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 405 | * Memory definitions - run uHAL out of SSRAM. |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 406 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 407 | */ |
| 408 | #define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE |
| 409 | |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 410 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 411 | * Clean base - dummy |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 412 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 413 | */ |
Russell King | 1e8b041 | 2008-11-13 14:43:03 +0000 | [diff] [blame] | 414 | #define CLEAN_BASE INTEGRATOR_BOOT_ROM_HI |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 415 | |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 416 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 417 | * Timer definitions |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 418 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 419 | * Only use timer 1 & 2 |
| 420 | * (both run at 24MHz and will need the clock divider set to 16). |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 421 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 422 | * Timer 0 runs at bus frequency and therefore could vary and currently |
| 423 | * uHAL can't handle that. |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 424 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 425 | */ |
| 426 | |
| 427 | #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE |
| 428 | #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) |
| 429 | #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) |
| 430 | |
| 431 | #define MAX_TIMER 2 |
| 432 | #define MAX_PERIOD 699050 |
| 433 | #define TICKS_PER_uSEC 24 |
| 434 | |
Russell King | 1f9c381 | 2005-05-03 12:22:19 +0100 | [diff] [blame] | 435 | /* |
| 436 | * These are useconds NOT ticks. |
| 437 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 438 | */ |
| 439 | #define mSEC_1 1000 |
| 440 | #define mSEC_5 (mSEC_1 * 5) |
| 441 | #define mSEC_10 (mSEC_1 * 10) |
| 442 | #define mSEC_25 (mSEC_1 * 25) |
| 443 | #define SEC_1 (mSEC_1 * 1000) |
| 444 | |
| 445 | #define INTEGRATOR_CSR_BASE 0x10000000 |
| 446 | #define INTEGRATOR_CSR_SIZE 0x10000000 |
| 447 | |
| 448 | #endif |
| 449 | |
| 450 | /* END */ |