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Kukjin Kim7d30e8b2011-02-14 16:33:10 +09001/* linux/arch/arm/mach-exynos4/cpu.c
Changhwan Youn2b12b5c2010-07-26 21:08:52 +09002 *
Kukjin Kim7d30e8b2011-02-14 16:33:10 +09003 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
Changhwan Youn2b12b5c2010-07-26 21:08:52 +09005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/sched.h>
12#include <linux/sysdev.h>
13
14#include <asm/mach/map.h>
15#include <asm/mach/irq.h>
16
17#include <asm/proc-fns.h>
Kyungmin Park1cf0eb72010-10-21 15:22:36 +090018#include <asm/hardware/cache-l2x0.h>
Changhwan Younaab74d32011-07-16 10:49:51 +090019#include <asm/hardware/gic.h>
Changhwan Youn2b12b5c2010-07-26 21:08:52 +090020
21#include <plat/cpu.h>
22#include <plat/clock.h>
MyungJoo Ham0e9e5262011-07-20 21:08:18 +090023#include <plat/devs.h>
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090024#include <plat/exynos4.h>
MyungJoo Ham0e9e5262011-07-20 21:08:18 +090025#include <plat/adc-core.h>
Hyuk Lee1036c3a2010-10-05 19:07:41 +090026#include <plat/sdhci.h>
Jonghun Hane61b1702011-07-21 15:46:26 +090027#include <plat/fb-core.h>
Sylwester Nawrocki604eefe2011-03-12 08:58:01 +090028#include <plat/fimc-core.h>
Sylwester Nawrocki5f272752011-07-06 16:04:09 +090029#include <plat/iic-core.h>
Kyungmin Parkd2edddf2011-08-19 20:25:05 +090030#include <plat/reset.h>
Changhwan Youn2b12b5c2010-07-26 21:08:52 +090031
32#include <mach/regs-irq.h>
Kyungmin Parkd2edddf2011-08-19 20:25:05 +090033#include <mach/regs-pmu.h>
Changhwan Youn2b12b5c2010-07-26 21:08:52 +090034
Changhwan Youn2b12b5c2010-07-26 21:08:52 +090035extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
36 unsigned int irq_start);
37extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
38
39/* Initial IO mappings */
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090040static struct map_desc exynos4_iodesc[] __initdata = {
Changhwan Youn2b12b5c2010-07-26 21:08:52 +090041 {
Changhwan Youn2b740152011-03-11 10:39:35 +090042 .virtual = (unsigned long)S5P_VA_SYSTIMER,
43 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
44 .length = SZ_4K,
45 .type = MT_DEVICE,
46 }, {
Changhwan Youn766211e2010-08-27 17:57:44 +090047 .virtual = (unsigned long)S5P_VA_SYSRAM,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090048 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
Changhwan Youn766211e2010-08-27 17:57:44 +090049 .length = SZ_4K,
50 .type = MT_DEVICE,
51 }, {
Kukjin Kimc598c472010-08-18 21:45:49 +090052 .virtual = (unsigned long)S5P_VA_CMU,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090053 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
Kukjin Kimc598c472010-08-18 21:45:49 +090054 .length = SZ_128K,
55 .type = MT_DEVICE,
Kukjin Kim19a2c062010-08-31 16:30:51 +090056 }, {
Changhwan Yound6d8b482010-12-03 17:15:40 +090057 .virtual = (unsigned long)S5P_VA_PMU,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090058 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
Changhwan Yound6d8b482010-12-03 17:15:40 +090059 .length = SZ_64K,
60 .type = MT_DEVICE,
61 }, {
Kukjin Kim19a2c062010-08-31 16:30:51 +090062 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090063 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
Kukjin Kim19a2c062010-08-31 16:30:51 +090064 .length = SZ_4K,
65 .type = MT_DEVICE,
66 }, {
67 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090068 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
Kukjin Kim19a2c062010-08-31 16:30:51 +090069 .length = SZ_8K,
70 .type = MT_DEVICE,
71 }, {
72 .virtual = (unsigned long)S5P_VA_L2CC,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090073 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
Kukjin Kim19a2c062010-08-31 16:30:51 +090074 .length = SZ_4K,
75 .type = MT_DEVICE,
76 }, {
Jongpill Lee37ea63b2010-10-14 15:46:18 +090077 .virtual = (unsigned long)S5P_VA_GPIO1,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090078 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
Kukjin Kim19a2c062010-08-31 16:30:51 +090079 .length = SZ_4K,
80 .type = MT_DEVICE,
81 }, {
Jongpill Lee37ea63b2010-10-14 15:46:18 +090082 .virtual = (unsigned long)S5P_VA_GPIO2,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090083 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
Jongpill Lee37ea63b2010-10-14 15:46:18 +090084 .length = SZ_4K,
85 .type = MT_DEVICE,
86 }, {
87 .virtual = (unsigned long)S5P_VA_GPIO3,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090088 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
Jongpill Lee37ea63b2010-10-14 15:46:18 +090089 .length = SZ_256,
90 .type = MT_DEVICE,
91 }, {
Sunyoung Kangdd0b7e22010-12-22 07:21:17 +090092 .virtual = (unsigned long)S5P_VA_DMC0,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +090093 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
Sunyoung Kangdd0b7e22010-12-22 07:21:17 +090094 .length = SZ_4K,
95 .type = MT_DEVICE,
96 }, {
Kukjin Kim19a2c062010-08-31 16:30:51 +090097 .virtual = (unsigned long)S3C_VA_UART,
98 .pfn = __phys_to_pfn(S3C_PA_UART),
99 .length = SZ_512K,
100 .type = MT_DEVICE,
Daein Moon09596ba2010-10-25 16:30:40 +0900101 }, {
102 .virtual = (unsigned long)S5P_VA_SROMC,
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900103 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
Daein Moon09596ba2010-10-25 16:30:40 +0900104 .length = SZ_4K,
105 .type = MT_DEVICE,
Joonyoung Shim8f1d1692011-04-08 13:22:10 +0900106 }, {
Kukjin Kim08115a12011-06-01 15:09:05 -0700107 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
Joonyoung Shim8f1d1692011-04-08 13:22:10 +0900108 .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
109 .length = SZ_4K,
110 .type = MT_DEVICE,
Changhwan Youneb13f2b2011-07-16 10:48:47 +0900111 }, {
112 .virtual = (unsigned long)S5P_VA_GIC_CPU,
113 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
114 .length = SZ_64K,
115 .type = MT_DEVICE,
116 }, {
117 .virtual = (unsigned long)S5P_VA_GIC_DIST,
118 .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
119 .length = SZ_64K,
120 .type = MT_DEVICE,
121 },
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900122};
123
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900124static void exynos4_idle(void)
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900125{
126 if (!need_resched())
127 cpu_do_idle();
128
129 local_irq_enable();
130}
131
Kyungmin Parkd2edddf2011-08-19 20:25:05 +0900132static void exynos4_sw_reset(void)
133{
134 __raw_writel(0x1, S5P_SWRESET);
135}
136
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900137/*
138 * exynos4_map_io
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900139 *
140 * register the standard cpu IO areas
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900141 */
142void __init exynos4_map_io(void)
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900143{
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900144 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
Hyuk Lee1036c3a2010-10-05 19:07:41 +0900145
146 /* initialize device information early */
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900147 exynos4_default_sdhci0();
148 exynos4_default_sdhci1();
149 exynos4_default_sdhci2();
150 exynos4_default_sdhci3();
Sylwester Nawrocki604eefe2011-03-12 08:58:01 +0900151
MyungJoo Ham0e9e5262011-07-20 21:08:18 +0900152 s3c_adc_setname("samsung-adc-v3");
153
Sylwester Nawrocki604eefe2011-03-12 08:58:01 +0900154 s3c_fimc_setname(0, "exynos4-fimc");
155 s3c_fimc_setname(1, "exynos4-fimc");
156 s3c_fimc_setname(2, "exynos4-fimc");
157 s3c_fimc_setname(3, "exynos4-fimc");
Sylwester Nawrocki5f272752011-07-06 16:04:09 +0900158
159 /* The I2C bus controllers are directly compatible with s3c2440 */
160 s3c_i2c0_setname("s3c2440-i2c");
161 s3c_i2c1_setname("s3c2440-i2c");
162 s3c_i2c2_setname("s3c2440-i2c");
Jonghun Hane61b1702011-07-21 15:46:26 +0900163
164 s5p_fb_setname(0, "exynos4-fb");
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900165}
166
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900167void __init exynos4_init_clocks(int xtal)
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900168{
169 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
170
171 s3c24xx_register_baseclocks(xtal);
172 s5p_register_clocks(xtal);
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900173 exynos4_register_clocks();
174 exynos4_setup_clocks();
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900175}
176
Changhwan Younaab74d32011-07-16 10:49:51 +0900177static void exynos4_gic_irq_eoi(struct irq_data *d)
178{
179 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
180
181 gic_data->cpu_base = S5P_VA_GIC_CPU +
182 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
183}
184
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900185void __init exynos4_init_irq(void)
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900186{
187 int irq;
188
Changhwan Youn069d4e72011-07-16 10:49:53 +0900189 gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
Changhwan Younaab74d32011-07-16 10:49:51 +0900190 gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900191
192 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
Changhwan Youn1f2d6c42010-11-29 17:04:46 +0900193
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900194 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
195 COMBINER_IRQ(irq, 0));
196 combiner_cascade_irq(irq, IRQ_SPI(irq));
197 }
198
199 /* The parameters of s5p_init_irq() are for VIC init.
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900200 * Theses parameters should be NULL and 0 because EXYNOS4
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900201 * uses GIC instead of VIC.
202 */
203 s5p_init_irq(NULL, 0);
204}
205
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900206struct sysdev_class exynos4_sysclass = {
207 .name = "exynos4-core",
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900208};
209
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900210static struct sys_device exynos4_sysdev = {
211 .cls = &exynos4_sysclass,
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900212};
213
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900214static int __init exynos4_core_init(void)
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900215{
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900216 return sysdev_class_register(&exynos4_sysclass);
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900217}
218
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900219core_initcall(exynos4_core_init);
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900220
Kyungmin Park1cf0eb72010-10-21 15:22:36 +0900221#ifdef CONFIG_CACHE_L2X0
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900222static int __init exynos4_l2x0_cache_init(void)
Kyungmin Park1cf0eb72010-10-21 15:22:36 +0900223{
224 /* TAG, Data Latency Control: 2cycle */
225 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
226 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
227
228 /* L2X0 Prefetch Control */
229 __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
230
231 /* L2X0 Power Control */
232 __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
233 S5P_VA_L2CC + L2X0_POWER_CTRL);
234
Changhwan Youna50eb1c2010-11-26 13:21:53 +0900235 l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
Kyungmin Park1cf0eb72010-10-21 15:22:36 +0900236
237 return 0;
238}
239
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900240early_initcall(exynos4_l2x0_cache_init);
Kyungmin Park1cf0eb72010-10-21 15:22:36 +0900241#endif
242
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900243int __init exynos4_init(void)
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900244{
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900245 printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900246
247 /* set idle function */
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900248 pm_idle = exynos4_idle;
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900249
Kyungmin Parkd2edddf2011-08-19 20:25:05 +0900250 /* set sw_reset function */
251 s5p_reset_hook = exynos4_sw_reset;
252
Kukjin Kim7d30e8b2011-02-14 16:33:10 +0900253 return sysdev_register(&exynos4_sysdev);
Changhwan Youn2b12b5c2010-07-26 21:08:52 +0900254}