Jassi Brar | 5033f43 | 2010-11-22 15:37:25 +0900 | [diff] [blame] | 1 | /* sound/soc/samsung/ac97.c |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 2 | * |
| 3 | * ALSA SoC Audio Layer - S3C AC97 Controller driver |
| 4 | * Evolved from s3c2443-ac97.c |
| 5 | * |
| 6 | * Copyright (c) 2010 Samsung Electronics Co. Ltd |
| 7 | * Author: Jaswinder Singh <jassi.brar@samsung.com> |
| 8 | * Credits: Graeme Gregory, Sean Choi |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/clk.h> |
| 20 | |
| 21 | #include <sound/soc.h> |
| 22 | |
| 23 | #include <plat/regs-ac97.h> |
| 24 | #include <mach/dma.h> |
| 25 | #include <plat/audio.h> |
| 26 | |
Jassi Brar | 4b640cf | 2010-11-22 15:35:57 +0900 | [diff] [blame] | 27 | #include "dma.h" |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 28 | |
| 29 | #define AC_CMD_ADDR(x) (x << 16) |
| 30 | #define AC_CMD_DATA(x) (x & 0xffff) |
| 31 | |
Seungwhan Youn | 4f644ea | 2011-01-07 13:46:52 +0900 | [diff] [blame^] | 32 | #define S3C_AC97_DAI_PCM 0 |
| 33 | #define S3C_AC97_DAI_MIC 1 |
| 34 | |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 35 | struct s3c_ac97_info { |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 36 | struct clk *ac97_clk; |
| 37 | void __iomem *regs; |
| 38 | struct mutex lock; |
| 39 | struct completion done; |
| 40 | }; |
| 41 | static struct s3c_ac97_info s3c_ac97; |
| 42 | |
| 43 | static struct s3c2410_dma_client s3c_dma_client_out = { |
| 44 | .name = "AC97 PCMOut" |
| 45 | }; |
| 46 | |
| 47 | static struct s3c2410_dma_client s3c_dma_client_in = { |
| 48 | .name = "AC97 PCMIn" |
| 49 | }; |
| 50 | |
| 51 | static struct s3c2410_dma_client s3c_dma_client_micin = { |
| 52 | .name = "AC97 MicIn" |
| 53 | }; |
| 54 | |
| 55 | static struct s3c_dma_params s3c_ac97_pcm_out = { |
| 56 | .client = &s3c_dma_client_out, |
| 57 | .dma_size = 4, |
| 58 | }; |
| 59 | |
| 60 | static struct s3c_dma_params s3c_ac97_pcm_in = { |
| 61 | .client = &s3c_dma_client_in, |
| 62 | .dma_size = 4, |
| 63 | }; |
| 64 | |
| 65 | static struct s3c_dma_params s3c_ac97_mic_in = { |
| 66 | .client = &s3c_dma_client_micin, |
| 67 | .dma_size = 4, |
| 68 | }; |
| 69 | |
| 70 | static void s3c_ac97_activate(struct snd_ac97 *ac97) |
| 71 | { |
| 72 | u32 ac_glbctrl, stat; |
| 73 | |
| 74 | stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7; |
| 75 | if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE) |
| 76 | return; /* Return if already active */ |
| 77 | |
| 78 | INIT_COMPLETION(s3c_ac97.done); |
| 79 | |
| 80 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 81 | ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON; |
| 82 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 83 | msleep(1); |
| 84 | |
| 85 | ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE; |
| 86 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 87 | msleep(1); |
| 88 | |
| 89 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 90 | ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; |
| 91 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 92 | |
| 93 | if (!wait_for_completion_timeout(&s3c_ac97.done, HZ)) |
Mark Brown | 4a6f998 | 2010-09-23 16:48:54 +0100 | [diff] [blame] | 94 | pr_err("AC97: Unable to activate!"); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | static unsigned short s3c_ac97_read(struct snd_ac97 *ac97, |
| 98 | unsigned short reg) |
| 99 | { |
| 100 | u32 ac_glbctrl, ac_codec_cmd; |
| 101 | u32 stat, addr, data; |
| 102 | |
| 103 | mutex_lock(&s3c_ac97.lock); |
| 104 | |
| 105 | s3c_ac97_activate(ac97); |
| 106 | |
| 107 | INIT_COMPLETION(s3c_ac97.done); |
| 108 | |
| 109 | ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD); |
| 110 | ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg); |
| 111 | writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); |
| 112 | |
| 113 | udelay(50); |
| 114 | |
| 115 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 116 | ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; |
| 117 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 118 | |
| 119 | if (!wait_for_completion_timeout(&s3c_ac97.done, HZ)) |
Mark Brown | 4a6f998 | 2010-09-23 16:48:54 +0100 | [diff] [blame] | 120 | pr_err("AC97: Unable to read!"); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 121 | |
| 122 | stat = readl(s3c_ac97.regs + S3C_AC97_STAT); |
| 123 | addr = (stat >> 16) & 0x7f; |
| 124 | data = (stat & 0xffff); |
| 125 | |
| 126 | if (addr != reg) |
Jassi Brar | 99ce3a3 | 2010-11-22 15:36:03 +0900 | [diff] [blame] | 127 | pr_err("ac97: req addr = %02x, rep addr = %02x\n", |
Mark Brown | 4a6f998 | 2010-09-23 16:48:54 +0100 | [diff] [blame] | 128 | reg, addr); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 129 | |
| 130 | mutex_unlock(&s3c_ac97.lock); |
| 131 | |
| 132 | return (unsigned short)data; |
| 133 | } |
| 134 | |
| 135 | static void s3c_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
| 136 | unsigned short val) |
| 137 | { |
| 138 | u32 ac_glbctrl, ac_codec_cmd; |
| 139 | |
| 140 | mutex_lock(&s3c_ac97.lock); |
| 141 | |
| 142 | s3c_ac97_activate(ac97); |
| 143 | |
| 144 | INIT_COMPLETION(s3c_ac97.done); |
| 145 | |
| 146 | ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD); |
| 147 | ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val); |
| 148 | writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); |
| 149 | |
| 150 | udelay(50); |
| 151 | |
| 152 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 153 | ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE; |
| 154 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 155 | |
| 156 | if (!wait_for_completion_timeout(&s3c_ac97.done, HZ)) |
Mark Brown | 4a6f998 | 2010-09-23 16:48:54 +0100 | [diff] [blame] | 157 | pr_err("AC97: Unable to write!"); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 158 | |
| 159 | ac_codec_cmd = readl(s3c_ac97.regs + S3C_AC97_CODEC_CMD); |
| 160 | ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ; |
| 161 | writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); |
| 162 | |
| 163 | mutex_unlock(&s3c_ac97.lock); |
| 164 | } |
| 165 | |
| 166 | static void s3c_ac97_cold_reset(struct snd_ac97 *ac97) |
| 167 | { |
Mark Brown | 8d85d74 | 2010-09-23 17:41:46 +0100 | [diff] [blame] | 168 | pr_debug("AC97: Cold reset\n"); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 169 | writel(S3C_AC97_GLBCTRL_COLDRESET, |
| 170 | s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 171 | msleep(1); |
| 172 | |
| 173 | writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 174 | msleep(1); |
| 175 | } |
| 176 | |
| 177 | static void s3c_ac97_warm_reset(struct snd_ac97 *ac97) |
| 178 | { |
| 179 | u32 stat; |
| 180 | |
| 181 | stat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT) & 0x7; |
| 182 | if (stat == S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE) |
| 183 | return; /* Return if already active */ |
| 184 | |
Mark Brown | 8d85d74 | 2010-09-23 17:41:46 +0100 | [diff] [blame] | 185 | pr_debug("AC97: Warm reset\n"); |
| 186 | |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 187 | writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 188 | msleep(1); |
| 189 | |
| 190 | writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 191 | msleep(1); |
| 192 | |
| 193 | s3c_ac97_activate(ac97); |
| 194 | } |
| 195 | |
| 196 | static irqreturn_t s3c_ac97_irq(int irq, void *dev_id) |
| 197 | { |
| 198 | u32 ac_glbctrl, ac_glbstat; |
| 199 | |
| 200 | ac_glbstat = readl(s3c_ac97.regs + S3C_AC97_GLBSTAT); |
| 201 | |
| 202 | if (ac_glbstat & S3C_AC97_GLBSTAT_CODECREADY) { |
| 203 | |
| 204 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 205 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE; |
| 206 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 207 | |
| 208 | complete(&s3c_ac97.done); |
| 209 | } |
| 210 | |
| 211 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 212 | ac_glbctrl |= (1<<30); /* Clear interrupt */ |
| 213 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 214 | |
| 215 | return IRQ_HANDLED; |
| 216 | } |
| 217 | |
| 218 | struct snd_ac97_bus_ops soc_ac97_ops = { |
| 219 | .read = s3c_ac97_read, |
| 220 | .write = s3c_ac97_write, |
| 221 | .warm_reset = s3c_ac97_warm_reset, |
| 222 | .reset = s3c_ac97_cold_reset, |
| 223 | }; |
| 224 | EXPORT_SYMBOL_GPL(soc_ac97_ops); |
| 225 | |
| 226 | static int s3c_ac97_hw_params(struct snd_pcm_substream *substream, |
| 227 | struct snd_pcm_hw_params *params, |
| 228 | struct snd_soc_dai *dai) |
| 229 | { |
| 230 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 231 | struct snd_soc_dai *cpu_dai = rtd->cpu_dai; |
Daniel Mack | 5f712b2 | 2010-03-22 10:11:15 +0100 | [diff] [blame] | 232 | struct s3c_dma_params *dma_data; |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 233 | |
| 234 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
Daniel Mack | 5f712b2 | 2010-03-22 10:11:15 +0100 | [diff] [blame] | 235 | dma_data = &s3c_ac97_pcm_out; |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 236 | else |
Daniel Mack | 5f712b2 | 2010-03-22 10:11:15 +0100 | [diff] [blame] | 237 | dma_data = &s3c_ac97_pcm_in; |
| 238 | |
| 239 | snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 240 | |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | static int s3c_ac97_trigger(struct snd_pcm_substream *substream, int cmd, |
| 245 | struct snd_soc_dai *dai) |
| 246 | { |
| 247 | u32 ac_glbctrl; |
| 248 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
Daniel Mack | 5f712b2 | 2010-03-22 10:11:15 +0100 | [diff] [blame] | 249 | struct s3c_dma_params *dma_data = |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 250 | snd_soc_dai_get_dma_data(rtd->cpu_dai, substream); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 251 | |
| 252 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 253 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
| 254 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK; |
| 255 | else |
| 256 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK; |
| 257 | |
| 258 | switch (cmd) { |
| 259 | case SNDRV_PCM_TRIGGER_START: |
| 260 | case SNDRV_PCM_TRIGGER_RESUME: |
| 261 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 262 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
| 263 | ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA; |
| 264 | else |
| 265 | ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA; |
| 266 | break; |
| 267 | |
| 268 | case SNDRV_PCM_TRIGGER_STOP: |
| 269 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 270 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 271 | break; |
| 272 | } |
| 273 | |
| 274 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 275 | |
Daniel Mack | 5f712b2 | 2010-03-22 10:11:15 +0100 | [diff] [blame] | 276 | s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 277 | |
| 278 | return 0; |
| 279 | } |
| 280 | |
| 281 | static int s3c_ac97_hw_mic_params(struct snd_pcm_substream *substream, |
| 282 | struct snd_pcm_hw_params *params, |
| 283 | struct snd_soc_dai *dai) |
| 284 | { |
| 285 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 286 | struct snd_soc_dai *cpu_dai = rtd->cpu_dai; |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 287 | |
| 288 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
| 289 | return -ENODEV; |
| 290 | else |
Daniel Mack | 5f712b2 | 2010-03-22 10:11:15 +0100 | [diff] [blame] | 291 | snd_soc_dai_set_dma_data(cpu_dai, substream, &s3c_ac97_mic_in); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 292 | |
| 293 | return 0; |
| 294 | } |
| 295 | |
| 296 | static int s3c_ac97_mic_trigger(struct snd_pcm_substream *substream, |
| 297 | int cmd, struct snd_soc_dai *dai) |
| 298 | { |
| 299 | u32 ac_glbctrl; |
| 300 | struct snd_soc_pcm_runtime *rtd = substream->private_data; |
Daniel Mack | 5f712b2 | 2010-03-22 10:11:15 +0100 | [diff] [blame] | 301 | struct s3c_dma_params *dma_data = |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 302 | snd_soc_dai_get_dma_data(rtd->cpu_dai, substream); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 303 | |
| 304 | ac_glbctrl = readl(s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 305 | ac_glbctrl &= ~S3C_AC97_GLBCTRL_MICINTM_MASK; |
| 306 | |
| 307 | switch (cmd) { |
| 308 | case SNDRV_PCM_TRIGGER_START: |
| 309 | case SNDRV_PCM_TRIGGER_RESUME: |
| 310 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
| 311 | ac_glbctrl |= S3C_AC97_GLBCTRL_MICINTM_DMA; |
| 312 | break; |
| 313 | |
| 314 | case SNDRV_PCM_TRIGGER_STOP: |
| 315 | case SNDRV_PCM_TRIGGER_SUSPEND: |
| 316 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
| 317 | break; |
| 318 | } |
| 319 | |
| 320 | writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); |
| 321 | |
Daniel Mack | 5f712b2 | 2010-03-22 10:11:15 +0100 | [diff] [blame] | 322 | s3c2410_dma_ctrl(dma_data->channel, S3C2410_DMAOP_STARTED); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 323 | |
| 324 | return 0; |
| 325 | } |
| 326 | |
| 327 | static struct snd_soc_dai_ops s3c_ac97_dai_ops = { |
| 328 | .hw_params = s3c_ac97_hw_params, |
| 329 | .trigger = s3c_ac97_trigger, |
| 330 | }; |
| 331 | |
| 332 | static struct snd_soc_dai_ops s3c_ac97_mic_dai_ops = { |
| 333 | .hw_params = s3c_ac97_hw_mic_params, |
| 334 | .trigger = s3c_ac97_mic_trigger, |
| 335 | }; |
| 336 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 337 | static struct snd_soc_dai_driver s3c_ac97_dai[] = { |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 338 | [S3C_AC97_DAI_PCM] = { |
Jassi Brar | 99ce3a3 | 2010-11-22 15:36:03 +0900 | [diff] [blame] | 339 | .name = "samsung-ac97", |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 340 | .ac97_control = 1, |
| 341 | .playback = { |
| 342 | .stream_name = "AC97 Playback", |
| 343 | .channels_min = 2, |
| 344 | .channels_max = 2, |
| 345 | .rates = SNDRV_PCM_RATE_8000_48000, |
| 346 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, |
| 347 | .capture = { |
| 348 | .stream_name = "AC97 Capture", |
| 349 | .channels_min = 2, |
| 350 | .channels_max = 2, |
| 351 | .rates = SNDRV_PCM_RATE_8000_48000, |
| 352 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, |
| 353 | .ops = &s3c_ac97_dai_ops, |
| 354 | }, |
| 355 | [S3C_AC97_DAI_MIC] = { |
Jassi Brar | 99ce3a3 | 2010-11-22 15:36:03 +0900 | [diff] [blame] | 356 | .name = "samsung-ac97-mic", |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 357 | .ac97_control = 1, |
| 358 | .capture = { |
| 359 | .stream_name = "AC97 Mic Capture", |
| 360 | .channels_min = 1, |
| 361 | .channels_max = 1, |
| 362 | .rates = SNDRV_PCM_RATE_8000_48000, |
| 363 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, |
| 364 | .ops = &s3c_ac97_mic_dai_ops, |
| 365 | }, |
| 366 | }; |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 367 | |
| 368 | static __devinit int s3c_ac97_probe(struct platform_device *pdev) |
| 369 | { |
| 370 | struct resource *mem_res, *dmatx_res, *dmarx_res, *dmamic_res, *irq_res; |
| 371 | struct s3c_audio_pdata *ac97_pdata; |
| 372 | int ret; |
| 373 | |
| 374 | ac97_pdata = pdev->dev.platform_data; |
| 375 | if (!ac97_pdata || !ac97_pdata->cfg_gpio) { |
| 376 | dev_err(&pdev->dev, "cfg_gpio callback not provided!\n"); |
| 377 | return -EINVAL; |
| 378 | } |
| 379 | |
| 380 | /* Check for availability of necessary resource */ |
| 381 | dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
| 382 | if (!dmatx_res) { |
| 383 | dev_err(&pdev->dev, "Unable to get AC97-TX dma resource\n"); |
| 384 | return -ENXIO; |
| 385 | } |
| 386 | |
| 387 | dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
| 388 | if (!dmarx_res) { |
| 389 | dev_err(&pdev->dev, "Unable to get AC97-RX dma resource\n"); |
| 390 | return -ENXIO; |
| 391 | } |
| 392 | |
| 393 | dmamic_res = platform_get_resource(pdev, IORESOURCE_DMA, 2); |
| 394 | if (!dmamic_res) { |
| 395 | dev_err(&pdev->dev, "Unable to get AC97-MIC dma resource\n"); |
| 396 | return -ENXIO; |
| 397 | } |
| 398 | |
| 399 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 400 | if (!mem_res) { |
| 401 | dev_err(&pdev->dev, "Unable to get register resource\n"); |
| 402 | return -ENXIO; |
| 403 | } |
| 404 | |
| 405 | irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 406 | if (!irq_res) { |
| 407 | dev_err(&pdev->dev, "AC97 IRQ not provided!\n"); |
| 408 | return -ENXIO; |
| 409 | } |
| 410 | |
| 411 | if (!request_mem_region(mem_res->start, |
Jassi Brar | 99ce3a3 | 2010-11-22 15:36:03 +0900 | [diff] [blame] | 412 | resource_size(mem_res), "ac97")) { |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 413 | dev_err(&pdev->dev, "Unable to request register region\n"); |
| 414 | return -EBUSY; |
| 415 | } |
| 416 | |
| 417 | s3c_ac97_pcm_out.channel = dmatx_res->start; |
| 418 | s3c_ac97_pcm_out.dma_addr = mem_res->start + S3C_AC97_PCM_DATA; |
| 419 | s3c_ac97_pcm_in.channel = dmarx_res->start; |
| 420 | s3c_ac97_pcm_in.dma_addr = mem_res->start + S3C_AC97_PCM_DATA; |
| 421 | s3c_ac97_mic_in.channel = dmamic_res->start; |
| 422 | s3c_ac97_mic_in.dma_addr = mem_res->start + S3C_AC97_MIC_DATA; |
| 423 | |
| 424 | init_completion(&s3c_ac97.done); |
| 425 | mutex_init(&s3c_ac97.lock); |
| 426 | |
| 427 | s3c_ac97.regs = ioremap(mem_res->start, resource_size(mem_res)); |
| 428 | if (s3c_ac97.regs == NULL) { |
| 429 | dev_err(&pdev->dev, "Unable to ioremap register region\n"); |
| 430 | ret = -ENXIO; |
| 431 | goto err1; |
| 432 | } |
| 433 | |
| 434 | s3c_ac97.ac97_clk = clk_get(&pdev->dev, "ac97"); |
| 435 | if (IS_ERR(s3c_ac97.ac97_clk)) { |
Jassi Brar | 99ce3a3 | 2010-11-22 15:36:03 +0900 | [diff] [blame] | 436 | dev_err(&pdev->dev, "ac97 failed to get ac97_clock\n"); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 437 | ret = -ENODEV; |
| 438 | goto err2; |
| 439 | } |
| 440 | clk_enable(s3c_ac97.ac97_clk); |
| 441 | |
| 442 | if (ac97_pdata->cfg_gpio(pdev)) { |
| 443 | dev_err(&pdev->dev, "Unable to configure gpio\n"); |
| 444 | ret = -EINVAL; |
| 445 | goto err3; |
| 446 | } |
| 447 | |
| 448 | ret = request_irq(irq_res->start, s3c_ac97_irq, |
| 449 | IRQF_DISABLED, "AC97", NULL); |
| 450 | if (ret < 0) { |
Jassi Brar | 99ce3a3 | 2010-11-22 15:36:03 +0900 | [diff] [blame] | 451 | dev_err(&pdev->dev, "ac97: interrupt request failed.\n"); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 452 | goto err4; |
| 453 | } |
| 454 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 455 | ret = snd_soc_register_dais(&pdev->dev, s3c_ac97_dai, |
| 456 | ARRAY_SIZE(s3c_ac97_dai)); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 457 | if (ret) |
| 458 | goto err5; |
| 459 | |
| 460 | return 0; |
| 461 | |
| 462 | err5: |
| 463 | free_irq(irq_res->start, NULL); |
| 464 | err4: |
| 465 | err3: |
| 466 | clk_disable(s3c_ac97.ac97_clk); |
| 467 | clk_put(s3c_ac97.ac97_clk); |
| 468 | err2: |
| 469 | iounmap(s3c_ac97.regs); |
| 470 | err1: |
| 471 | release_mem_region(mem_res->start, resource_size(mem_res)); |
| 472 | |
| 473 | return ret; |
| 474 | } |
| 475 | |
| 476 | static __devexit int s3c_ac97_remove(struct platform_device *pdev) |
| 477 | { |
| 478 | struct resource *mem_res, *irq_res; |
| 479 | |
Liam Girdwood | f0fba2a | 2010-03-17 20:15:21 +0000 | [diff] [blame] | 480 | snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(s3c_ac97_dai)); |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 481 | |
| 482 | irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 483 | if (irq_res) |
| 484 | free_irq(irq_res->start, NULL); |
| 485 | |
| 486 | clk_disable(s3c_ac97.ac97_clk); |
| 487 | clk_put(s3c_ac97.ac97_clk); |
| 488 | |
| 489 | iounmap(s3c_ac97.regs); |
| 490 | |
| 491 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 492 | if (mem_res) |
| 493 | release_mem_region(mem_res->start, resource_size(mem_res)); |
| 494 | |
| 495 | return 0; |
| 496 | } |
| 497 | |
| 498 | static struct platform_driver s3c_ac97_driver = { |
| 499 | .probe = s3c_ac97_probe, |
| 500 | .remove = s3c_ac97_remove, |
| 501 | .driver = { |
Jassi Brar | e610467 | 2010-11-22 15:36:00 +0900 | [diff] [blame] | 502 | .name = "samsung-ac97", |
Jassi Brar | fc93ea2 | 2010-01-27 14:59:08 +0900 | [diff] [blame] | 503 | .owner = THIS_MODULE, |
| 504 | }, |
| 505 | }; |
| 506 | |
| 507 | static int __init s3c_ac97_init(void) |
| 508 | { |
| 509 | return platform_driver_register(&s3c_ac97_driver); |
| 510 | } |
| 511 | module_init(s3c_ac97_init); |
| 512 | |
| 513 | static void __exit s3c_ac97_exit(void) |
| 514 | { |
| 515 | platform_driver_unregister(&s3c_ac97_driver); |
| 516 | } |
| 517 | module_exit(s3c_ac97_exit); |
| 518 | |
| 519 | MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>"); |
| 520 | MODULE_DESCRIPTION("AC97 driver for the Samsung SoC"); |
| 521 | MODULE_LICENSE("GPL"); |
Jassi Brar | e610467 | 2010-11-22 15:36:00 +0900 | [diff] [blame] | 522 | MODULE_ALIAS("platform:samsung-ac97"); |