David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 1 | #ifndef _ASM_POWERPC_PGTABLE_PPC32_H |
| 2 | #define _ASM_POWERPC_PGTABLE_PPC32_H |
| 3 | |
David Gibson | d1953c8 | 2007-05-08 12:46:49 +1000 | [diff] [blame] | 4 | #include <asm-generic/pgtable-nopmd.h> |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 5 | |
| 6 | #ifndef __ASSEMBLY__ |
| 7 | #include <linux/sched.h> |
| 8 | #include <linux/threads.h> |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 9 | #include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */ |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 10 | |
| 11 | extern unsigned long va_to_phys(unsigned long address); |
| 12 | extern pte_t *va_to_pte(unsigned long address); |
| 13 | extern unsigned long ioremap_bot, ioremap_base; |
| 14 | #endif /* __ASSEMBLY__ */ |
| 15 | |
| 16 | /* |
| 17 | * The PowerPC MMU uses a hash table containing PTEs, together with |
| 18 | * a set of 16 segment registers (on 32-bit implementations), to define |
| 19 | * the virtual to physical address mapping. |
| 20 | * |
| 21 | * We use the hash table as an extended TLB, i.e. a cache of currently |
| 22 | * active mappings. We maintain a two-level page table tree, much |
| 23 | * like that used by the i386, for the sake of the Linux memory |
| 24 | * management code. Low-level assembler code in hashtable.S |
| 25 | * (procedure hash_page) is responsible for extracting ptes from the |
| 26 | * tree and putting them into the hash table when necessary, and |
| 27 | * updating the accessed and modified bits in the page table tree. |
| 28 | */ |
| 29 | |
| 30 | /* |
| 31 | * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk. |
| 32 | * We also use the two level tables, but we can put the real bits in them |
| 33 | * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0, |
| 34 | * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has |
| 35 | * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit |
| 36 | * based upon user/super access. The TLB does not have accessed nor write |
| 37 | * protect. We assume that if the TLB get loaded with an entry it is |
| 38 | * accessed, and overload the changed bit for write protect. We use |
| 39 | * two bits in the software pte that are supposed to be set to zero in |
| 40 | * the TLB entry (24 and 25) for these indicators. Although the level 1 |
| 41 | * descriptor contains the guarded and writethrough/copyback bits, we can |
| 42 | * set these at the page level since they get copied from the Mx_TWC |
| 43 | * register when the TLB entry is loaded. We will use bit 27 for guard, since |
| 44 | * that is where it exists in the MD_TWC, and bit 26 for writethrough. |
| 45 | * These will get masked from the level 2 descriptor at TLB load time, and |
| 46 | * copied to the MD_TWC before it gets loaded. |
| 47 | * Large page sizes added. We currently support two sizes, 4K and 8M. |
| 48 | * This also allows a TLB hander optimization because we can directly |
| 49 | * load the PMD into MD_TWC. The 8M pages are only used for kernel |
| 50 | * mapping of well known areas. The PMD (PGD) entries contain control |
| 51 | * flags in addition to the address, so care must be taken that the |
| 52 | * software no longer assumes these are only pointers. |
| 53 | */ |
| 54 | |
| 55 | /* |
| 56 | * At present, all PowerPC 400-class processors share a similar TLB |
| 57 | * architecture. The instruction and data sides share a unified, |
| 58 | * 64-entry, fully-associative TLB which is maintained totally under |
| 59 | * software control. In addition, the instruction side has a |
| 60 | * hardware-managed, 4-entry, fully-associative TLB which serves as a |
| 61 | * first level to the shared TLB. These two TLBs are known as the UTLB |
| 62 | * and ITLB, respectively (see "mmu.h" for definitions). |
| 63 | */ |
| 64 | |
| 65 | /* |
| 66 | * The normal case is that PTEs are 32-bits and we have a 1-page |
| 67 | * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus |
| 68 | * |
| 69 | * For any >32-bit physical address platform, we can use the following |
| 70 | * two level page table layout where the pgdir is 8KB and the MS 13 bits |
| 71 | * are an index to the second level table. The combined pgdir/pmd first |
| 72 | * level has 2048 entries and the second level has 512 64-bit PTE entries. |
| 73 | * -Matt |
| 74 | */ |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 75 | /* PGDIR_SHIFT determines what a top-level page table entry can map */ |
David Gibson | d1953c8 | 2007-05-08 12:46:49 +1000 | [diff] [blame] | 76 | #define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT) |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 77 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
| 78 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) |
| 79 | |
| 80 | /* |
| 81 | * entries per page directory level: our page-table tree is two-level, so |
| 82 | * we don't really have any PMD directory. |
| 83 | */ |
| 84 | #define PTRS_PER_PTE (1 << PTE_SHIFT) |
| 85 | #define PTRS_PER_PMD 1 |
| 86 | #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) |
| 87 | |
| 88 | #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) |
| 89 | #define FIRST_USER_ADDRESS 0 |
| 90 | |
| 91 | #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT) |
| 92 | #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS) |
| 93 | |
| 94 | #define pte_ERROR(e) \ |
David Gibson | 0aeafb0 | 2007-05-04 16:47:51 +1000 | [diff] [blame] | 95 | printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \ |
| 96 | (unsigned long long)pte_val(e)) |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 97 | #define pgd_ERROR(e) \ |
| 98 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) |
| 99 | |
| 100 | /* |
| 101 | * Just any arbitrary offset to the start of the vmalloc VM area: the |
| 102 | * current 64MB value just means that there will be a 64MB "hole" after the |
| 103 | * physical memory until the kernel virtual memory starts. That means that |
| 104 | * any out-of-bounds memory accesses will hopefully be caught. |
| 105 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced |
| 106 | * area for the same reason. ;) |
| 107 | * |
| 108 | * We no longer map larger than phys RAM with the BATs so we don't have |
| 109 | * to worry about the VMALLOC_OFFSET causing problems. We do have to worry |
| 110 | * about clashes between our early calls to ioremap() that start growing down |
| 111 | * from ioremap_base being run into the VM area allocations (growing upwards |
| 112 | * from VMALLOC_START). For this reason we have ioremap_bot to check when |
| 113 | * we actually run into our mappings setup in the early boot with the VM |
| 114 | * system. This really does become a problem for machines with good amounts |
| 115 | * of RAM. -- Cort |
| 116 | */ |
| 117 | #define VMALLOC_OFFSET (0x1000000) /* 16M */ |
| 118 | #ifdef PPC_PIN_SIZE |
| 119 | #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) |
| 120 | #else |
| 121 | #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) |
| 122 | #endif |
| 123 | #define VMALLOC_END ioremap_bot |
| 124 | |
| 125 | /* |
| 126 | * Bits in a linux-style PTE. These match the bits in the |
| 127 | * (hardware-defined) PowerPC PTE as closely as possible. |
| 128 | */ |
| 129 | |
| 130 | #if defined(CONFIG_40x) |
| 131 | |
| 132 | /* There are several potential gotchas here. The 40x hardware TLBLO |
| 133 | field looks like this: |
| 134 | |
| 135 | 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
| 136 | RPN..................... 0 0 EX WR ZSEL....... W I M G |
| 137 | |
| 138 | Where possible we make the Linux PTE bits match up with this |
| 139 | |
| 140 | - bits 20 and 21 must be cleared, because we use 4k pages (40x can |
| 141 | support down to 1k pages), this is done in the TLBMiss exception |
| 142 | handler. |
| 143 | - We use only zones 0 (for kernel pages) and 1 (for user pages) |
| 144 | of the 16 available. Bit 24-26 of the TLB are cleared in the TLB |
| 145 | miss handler. Bit 27 is PAGE_USER, thus selecting the correct |
| 146 | zone. |
| 147 | - PRESENT *must* be in the bottom two bits because swap cache |
| 148 | entries use the top 30 bits. Because 40x doesn't support SMP |
| 149 | anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 |
| 150 | is cleared in the TLB miss handler before the TLB entry is loaded. |
| 151 | - All other bits of the PTE are loaded into TLBLO without |
| 152 | modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for |
| 153 | software PTE bits. We actually use use bits 21, 24, 25, and |
| 154 | 30 respectively for the software bits: ACCESSED, DIRTY, RW, and |
| 155 | PRESENT. |
| 156 | */ |
| 157 | |
| 158 | /* Definitions for 40x embedded chips. */ |
| 159 | #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */ |
| 160 | #define _PAGE_FILE 0x001 /* when !present: nonlinear file mapping */ |
| 161 | #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */ |
| 162 | #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */ |
| 163 | #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */ |
| 164 | #define _PAGE_USER 0x010 /* matches one of the zone permission bits */ |
| 165 | #define _PAGE_RW 0x040 /* software: Writes permitted */ |
| 166 | #define _PAGE_DIRTY 0x080 /* software: dirty page */ |
| 167 | #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */ |
| 168 | #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */ |
| 169 | #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ |
| 170 | |
| 171 | #define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */ |
| 172 | #define _PMD_BAD 0x802 |
| 173 | #define _PMD_SIZE 0x0e0 /* size field, != 0 for large-page PMD entry */ |
| 174 | #define _PMD_SIZE_4M 0x0c0 |
| 175 | #define _PMD_SIZE_16M 0x0e0 |
| 176 | #define PMD_PAGE_SIZE(pmdval) (1024 << (((pmdval) & _PMD_SIZE) >> 4)) |
| 177 | |
| 178 | #elif defined(CONFIG_44x) |
| 179 | /* |
| 180 | * Definitions for PPC440 |
| 181 | * |
| 182 | * Because of the 3 word TLB entries to support 36-bit addressing, |
| 183 | * the attribute are difficult to map in such a fashion that they |
| 184 | * are easily loaded during exception processing. I decided to |
| 185 | * organize the entry so the ERPN is the only portion in the |
| 186 | * upper word of the PTE and the attribute bits below are packed |
| 187 | * in as sensibly as they can be in the area below a 4KB page size |
| 188 | * oriented RPN. This at least makes it easy to load the RPN and |
| 189 | * ERPN fields in the TLB. -Matt |
| 190 | * |
| 191 | * Note that these bits preclude future use of a page size |
| 192 | * less than 4KB. |
| 193 | * |
| 194 | * |
| 195 | * PPC 440 core has following TLB attribute fields; |
| 196 | * |
| 197 | * TLB1: |
| 198 | * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
| 199 | * RPN................................. - - - - - - ERPN....... |
| 200 | * |
| 201 | * TLB2: |
| 202 | * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
| 203 | * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR |
| 204 | * |
| 205 | * There are some constrains and options, to decide mapping software bits |
| 206 | * into TLB entry. |
| 207 | * |
| 208 | * - PRESENT *must* be in the bottom three bits because swap cache |
| 209 | * entries use the top 29 bits for TLB2. |
| 210 | * |
| 211 | * - FILE *must* be in the bottom three bits because swap cache |
| 212 | * entries use the top 29 bits for TLB2. |
| 213 | * |
| 214 | * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it |
| 215 | * doesn't support SMP. So we can use this as software bit, like |
| 216 | * DIRTY. |
| 217 | * |
| 218 | * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used |
| 219 | * for memory protection related functions (see PTE structure in |
| 220 | * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the |
| 221 | * above bits. Note that the bit values are CPU specific, not architecture |
| 222 | * specific. |
| 223 | * |
| 224 | * The kernel PTE entry holds an arch-dependent swp_entry structure under |
| 225 | * certain situations. In other words, in such situations some portion of |
| 226 | * the PTE bits are used as a swp_entry. In the PPC implementation, the |
| 227 | * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still |
| 228 | * hold protection values. That means the three protection bits are |
| 229 | * reserved for both PTE and SWAP entry at the most significant three |
| 230 | * LSBs. |
| 231 | * |
| 232 | * There are three protection bits available for SWAP entry: |
| 233 | * _PAGE_PRESENT |
| 234 | * _PAGE_FILE |
| 235 | * _PAGE_HASHPTE (if HW has) |
| 236 | * |
| 237 | * So those three bits have to be inside of 0-2nd LSB of PTE. |
| 238 | * |
| 239 | */ |
| 240 | |
| 241 | #define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ |
| 242 | #define _PAGE_RW 0x00000002 /* S: Write permission */ |
| 243 | #define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */ |
| 244 | #define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ |
| 245 | #define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */ |
| 246 | #define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */ |
| 247 | #define _PAGE_USER 0x00000040 /* S: User page */ |
| 248 | #define _PAGE_ENDIAN 0x00000080 /* H: E bit */ |
| 249 | #define _PAGE_GUARDED 0x00000100 /* H: G bit */ |
| 250 | #define _PAGE_DIRTY 0x00000200 /* S: Page dirty */ |
| 251 | #define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ |
| 252 | #define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ |
| 253 | |
| 254 | /* TODO: Add large page lowmem mapping support */ |
| 255 | #define _PMD_PRESENT 0 |
| 256 | #define _PMD_PRESENT_MASK (PAGE_MASK) |
| 257 | #define _PMD_BAD (~PAGE_MASK) |
| 258 | |
| 259 | /* ERPN in a PTE never gets cleared, ignore it */ |
| 260 | #define _PTE_NONE_MASK 0xffffffff00000000ULL |
| 261 | |
| 262 | #elif defined(CONFIG_FSL_BOOKE) |
| 263 | /* |
| 264 | MMU Assist Register 3: |
| 265 | |
| 266 | 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63 |
| 267 | RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR |
| 268 | |
| 269 | - PRESENT *must* be in the bottom three bits because swap cache |
| 270 | entries use the top 29 bits. |
| 271 | |
| 272 | - FILE *must* be in the bottom three bits because swap cache |
| 273 | entries use the top 29 bits. |
| 274 | */ |
| 275 | |
| 276 | /* Definitions for FSL Book-E Cores */ |
| 277 | #define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */ |
| 278 | #define _PAGE_USER 0x00002 /* S: User page (maps to UR) */ |
| 279 | #define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */ |
| 280 | #define _PAGE_ACCESSED 0x00004 /* S: Page referenced */ |
| 281 | #define _PAGE_HWWRITE 0x00008 /* H: Dirty & RW, set in exception */ |
| 282 | #define _PAGE_RW 0x00010 /* S: Write permission */ |
| 283 | #define _PAGE_HWEXEC 0x00020 /* H: UX permission */ |
| 284 | |
| 285 | #define _PAGE_ENDIAN 0x00040 /* H: E bit */ |
| 286 | #define _PAGE_GUARDED 0x00080 /* H: G bit */ |
| 287 | #define _PAGE_COHERENT 0x00100 /* H: M bit */ |
| 288 | #define _PAGE_NO_CACHE 0x00200 /* H: I bit */ |
| 289 | #define _PAGE_WRITETHRU 0x00400 /* H: W bit */ |
| 290 | |
| 291 | #ifdef CONFIG_PTE_64BIT |
| 292 | #define _PAGE_DIRTY 0x08000 /* S: Page dirty */ |
| 293 | |
| 294 | /* ERPN in a PTE never gets cleared, ignore it */ |
| 295 | #define _PTE_NONE_MASK 0xffffffffffff0000ULL |
| 296 | #else |
| 297 | #define _PAGE_DIRTY 0x00800 /* S: Page dirty */ |
| 298 | #endif |
| 299 | |
| 300 | #define _PMD_PRESENT 0 |
| 301 | #define _PMD_PRESENT_MASK (PAGE_MASK) |
| 302 | #define _PMD_BAD (~PAGE_MASK) |
| 303 | |
| 304 | #elif defined(CONFIG_8xx) |
| 305 | /* Definitions for 8xx embedded chips. */ |
| 306 | #define _PAGE_PRESENT 0x0001 /* Page is valid */ |
| 307 | #define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */ |
| 308 | #define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */ |
| 309 | #define _PAGE_SHARED 0x0004 /* No ASID (context) compare */ |
| 310 | |
| 311 | /* These five software bits must be masked out when the entry is loaded |
| 312 | * into the TLB. |
| 313 | */ |
| 314 | #define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */ |
| 315 | #define _PAGE_GUARDED 0x0010 /* software: guarded access */ |
| 316 | #define _PAGE_DIRTY 0x0020 /* software: page changed */ |
| 317 | #define _PAGE_RW 0x0040 /* software: user write access allowed */ |
| 318 | #define _PAGE_ACCESSED 0x0080 /* software: page referenced */ |
| 319 | |
| 320 | /* Setting any bits in the nibble with the follow two controls will |
| 321 | * require a TLB exception handler change. It is assumed unused bits |
| 322 | * are always zero. |
| 323 | */ |
| 324 | #define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */ |
| 325 | #define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */ |
| 326 | |
| 327 | #define _PMD_PRESENT 0x0001 |
| 328 | #define _PMD_BAD 0x0ff0 |
| 329 | #define _PMD_PAGE_MASK 0x000c |
| 330 | #define _PMD_PAGE_8M 0x000c |
| 331 | |
| 332 | /* |
| 333 | * The 8xx TLB miss handler allegedly sets _PAGE_ACCESSED in the PTE |
| 334 | * for an address even if _PAGE_PRESENT is not set, as a performance |
| 335 | * optimization. This is a bug if you ever want to use swap unless |
| 336 | * _PAGE_ACCESSED is 2, which it isn't, or unless you have 8xx-specific |
| 337 | * definitions for __swp_entry etc. below, which would be gross. |
| 338 | * -- paulus |
| 339 | */ |
| 340 | #define _PTE_NONE_MASK _PAGE_ACCESSED |
| 341 | |
| 342 | #else /* CONFIG_6xx */ |
| 343 | /* Definitions for 60x, 740/750, etc. */ |
| 344 | #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ |
| 345 | #define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */ |
| 346 | #define _PAGE_FILE 0x004 /* when !present: nonlinear file mapping */ |
| 347 | #define _PAGE_USER 0x004 /* usermode access allowed */ |
| 348 | #define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */ |
| 349 | #define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ |
| 350 | #define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ |
| 351 | #define _PAGE_WRITETHRU 0x040 /* W: cache write-through */ |
| 352 | #define _PAGE_DIRTY 0x080 /* C: page changed */ |
| 353 | #define _PAGE_ACCESSED 0x100 /* R: page referenced */ |
| 354 | #define _PAGE_EXEC 0x200 /* software: i-cache coherency required */ |
| 355 | #define _PAGE_RW 0x400 /* software: user write access allowed */ |
| 356 | |
| 357 | #define _PTE_NONE_MASK _PAGE_HASHPTE |
| 358 | |
| 359 | #define _PMD_PRESENT 0 |
| 360 | #define _PMD_PRESENT_MASK (PAGE_MASK) |
| 361 | #define _PMD_BAD (~PAGE_MASK) |
| 362 | #endif |
| 363 | |
| 364 | /* |
| 365 | * Some bits are only used on some cpu families... |
| 366 | */ |
| 367 | #ifndef _PAGE_HASHPTE |
| 368 | #define _PAGE_HASHPTE 0 |
| 369 | #endif |
| 370 | #ifndef _PTE_NONE_MASK |
| 371 | #define _PTE_NONE_MASK 0 |
| 372 | #endif |
| 373 | #ifndef _PAGE_SHARED |
| 374 | #define _PAGE_SHARED 0 |
| 375 | #endif |
| 376 | #ifndef _PAGE_HWWRITE |
| 377 | #define _PAGE_HWWRITE 0 |
| 378 | #endif |
| 379 | #ifndef _PAGE_HWEXEC |
| 380 | #define _PAGE_HWEXEC 0 |
| 381 | #endif |
| 382 | #ifndef _PAGE_EXEC |
| 383 | #define _PAGE_EXEC 0 |
| 384 | #endif |
| 385 | #ifndef _PMD_PRESENT_MASK |
| 386 | #define _PMD_PRESENT_MASK _PMD_PRESENT |
| 387 | #endif |
| 388 | #ifndef _PMD_SIZE |
| 389 | #define _PMD_SIZE 0 |
| 390 | #define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE() |
| 391 | #endif |
| 392 | |
| 393 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) |
| 394 | |
| 395 | /* |
| 396 | * Note: the _PAGE_COHERENT bit automatically gets set in the hardware |
| 397 | * PTE if CONFIG_SMP is defined (hash_page does this); there is no need |
| 398 | * to have it in the Linux PTE, and in fact the bit could be reused for |
| 399 | * another purpose. -- paulus. |
| 400 | */ |
| 401 | |
| 402 | #ifdef CONFIG_44x |
| 403 | #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED) |
| 404 | #else |
| 405 | #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED) |
| 406 | #endif |
| 407 | #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE) |
| 408 | #define _PAGE_KERNEL (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE) |
| 409 | |
| 410 | #ifdef CONFIG_PPC_STD_MMU |
| 411 | /* On standard PPC MMU, no user access implies kernel read/write access, |
| 412 | * so to write-protect kernel memory we must turn on user access */ |
| 413 | #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER) |
| 414 | #else |
| 415 | #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED) |
| 416 | #endif |
| 417 | |
| 418 | #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED) |
| 419 | #define _PAGE_RAM (_PAGE_KERNEL | _PAGE_HWEXEC) |
| 420 | |
| 421 | #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) |
| 422 | /* We want the debuggers to be able to set breakpoints anywhere, so |
| 423 | * don't write protect the kernel text */ |
| 424 | #define _PAGE_RAM_TEXT _PAGE_RAM |
| 425 | #else |
| 426 | #define _PAGE_RAM_TEXT (_PAGE_KERNEL_RO | _PAGE_HWEXEC) |
| 427 | #endif |
| 428 | |
| 429 | #define PAGE_NONE __pgprot(_PAGE_BASE) |
| 430 | #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) |
| 431 | #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) |
| 432 | #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) |
| 433 | #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) |
| 434 | #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) |
| 435 | #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) |
| 436 | |
| 437 | #define PAGE_KERNEL __pgprot(_PAGE_RAM) |
| 438 | #define PAGE_KERNEL_NOCACHE __pgprot(_PAGE_IO) |
| 439 | |
| 440 | /* |
| 441 | * The PowerPC can only do execute protection on a segment (256MB) basis, |
| 442 | * not on a page basis. So we consider execute permission the same as read. |
| 443 | * Also, write permissions imply read permissions. |
| 444 | * This is the closest we can get.. |
| 445 | */ |
| 446 | #define __P000 PAGE_NONE |
| 447 | #define __P001 PAGE_READONLY_X |
| 448 | #define __P010 PAGE_COPY |
| 449 | #define __P011 PAGE_COPY_X |
| 450 | #define __P100 PAGE_READONLY |
| 451 | #define __P101 PAGE_READONLY_X |
| 452 | #define __P110 PAGE_COPY |
| 453 | #define __P111 PAGE_COPY_X |
| 454 | |
| 455 | #define __S000 PAGE_NONE |
| 456 | #define __S001 PAGE_READONLY_X |
| 457 | #define __S010 PAGE_SHARED |
| 458 | #define __S011 PAGE_SHARED_X |
| 459 | #define __S100 PAGE_READONLY |
| 460 | #define __S101 PAGE_READONLY_X |
| 461 | #define __S110 PAGE_SHARED |
| 462 | #define __S111 PAGE_SHARED_X |
| 463 | |
| 464 | #ifndef __ASSEMBLY__ |
| 465 | /* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a |
| 466 | * kernel without large page PMD support */ |
| 467 | extern unsigned long bad_call_to_PMD_PAGE_SIZE(void); |
| 468 | |
| 469 | /* |
| 470 | * Conversions between PTE values and page frame numbers. |
| 471 | */ |
| 472 | |
| 473 | /* in some case we want to additionaly adjust where the pfn is in the pte to |
| 474 | * allow room for more flags */ |
| 475 | #if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT) |
| 476 | #define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8) |
| 477 | #else |
| 478 | #define PFN_SHIFT_OFFSET (PAGE_SHIFT) |
| 479 | #endif |
| 480 | |
| 481 | #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET) |
| 482 | #define pte_page(x) pfn_to_page(pte_pfn(x)) |
| 483 | |
| 484 | #define pfn_pte(pfn, prot) __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\ |
| 485 | pgprot_val(prot)) |
| 486 | #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 487 | #endif /* __ASSEMBLY__ */ |
| 488 | |
| 489 | #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0) |
| 490 | #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT) |
| 491 | #define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0) |
| 492 | |
| 493 | #define pmd_none(pmd) (!pmd_val(pmd)) |
| 494 | #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD) |
| 495 | #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK) |
| 496 | #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0) |
| 497 | |
| 498 | #ifndef __ASSEMBLY__ |
| 499 | /* |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 500 | * The following only work if pte_present() is true. |
| 501 | * Undefined behaviour if not.. |
| 502 | */ |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 503 | static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; } |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 504 | static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } |
| 505 | static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } |
| 506 | static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } |
| 507 | |
| 508 | static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; } |
| 509 | static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; } |
| 510 | |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 511 | static inline pte_t pte_wrprotect(pte_t pte) { |
| 512 | pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; } |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 513 | static inline pte_t pte_mkclean(pte_t pte) { |
| 514 | pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; } |
| 515 | static inline pte_t pte_mkold(pte_t pte) { |
| 516 | pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } |
| 517 | |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 518 | static inline pte_t pte_mkwrite(pte_t pte) { |
| 519 | pte_val(pte) |= _PAGE_RW; return pte; } |
| 520 | static inline pte_t pte_mkdirty(pte_t pte) { |
| 521 | pte_val(pte) |= _PAGE_DIRTY; return pte; } |
| 522 | static inline pte_t pte_mkyoung(pte_t pte) { |
| 523 | pte_val(pte) |= _PAGE_ACCESSED; return pte; } |
| 524 | |
| 525 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
| 526 | { |
| 527 | pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); |
| 528 | return pte; |
| 529 | } |
| 530 | |
| 531 | /* |
| 532 | * When flushing the tlb entry for a page, we also need to flush the hash |
| 533 | * table entry. flush_hash_pages is assembler (for speed) in hashtable.S. |
| 534 | */ |
| 535 | extern int flush_hash_pages(unsigned context, unsigned long va, |
| 536 | unsigned long pmdval, int count); |
| 537 | |
| 538 | /* Add an HPTE to the hash table */ |
| 539 | extern void add_hash_page(unsigned context, unsigned long va, |
| 540 | unsigned long pmdval); |
| 541 | |
| 542 | /* |
| 543 | * Atomic PTE updates. |
| 544 | * |
| 545 | * pte_update clears and sets bit atomically, and returns |
| 546 | * the old pte value. In the 64-bit PTE case we lock around the |
| 547 | * low PTE word since we expect ALL flag bits to be there |
| 548 | */ |
| 549 | #ifndef CONFIG_PTE_64BIT |
| 550 | static inline unsigned long pte_update(pte_t *p, unsigned long clr, |
| 551 | unsigned long set) |
| 552 | { |
| 553 | unsigned long old, tmp; |
| 554 | |
| 555 | __asm__ __volatile__("\ |
| 556 | 1: lwarx %0,0,%3\n\ |
| 557 | andc %1,%0,%4\n\ |
| 558 | or %1,%1,%5\n" |
| 559 | PPC405_ERR77(0,%3) |
| 560 | " stwcx. %1,0,%3\n\ |
| 561 | bne- 1b" |
| 562 | : "=&r" (old), "=&r" (tmp), "=m" (*p) |
| 563 | : "r" (p), "r" (clr), "r" (set), "m" (*p) |
| 564 | : "cc" ); |
| 565 | return old; |
| 566 | } |
| 567 | #else |
| 568 | static inline unsigned long long pte_update(pte_t *p, unsigned long clr, |
| 569 | unsigned long set) |
| 570 | { |
| 571 | unsigned long long old; |
| 572 | unsigned long tmp; |
| 573 | |
| 574 | __asm__ __volatile__("\ |
| 575 | 1: lwarx %L0,0,%4\n\ |
| 576 | lwzx %0,0,%3\n\ |
| 577 | andc %1,%L0,%5\n\ |
| 578 | or %1,%1,%6\n" |
| 579 | PPC405_ERR77(0,%3) |
| 580 | " stwcx. %1,0,%4\n\ |
| 581 | bne- 1b" |
| 582 | : "=&r" (old), "=&r" (tmp), "=m" (*p) |
| 583 | : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p) |
| 584 | : "cc" ); |
| 585 | return old; |
| 586 | } |
| 587 | #endif |
| 588 | |
| 589 | /* |
| 590 | * set_pte stores a linux PTE into the linux page table. |
| 591 | * On machines which use an MMU hash table we avoid changing the |
| 592 | * _PAGE_HASHPTE bit. |
| 593 | */ |
| 594 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, |
| 595 | pte_t *ptep, pte_t pte) |
| 596 | { |
| 597 | #if _PAGE_HASHPTE != 0 |
| 598 | pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE); |
| 599 | #else |
| 600 | *ptep = pte; |
| 601 | #endif |
| 602 | } |
| 603 | |
| 604 | /* |
| 605 | * 2.6 calles this without flushing the TLB entry, this is wrong |
| 606 | * for our hash-based implementation, we fix that up here |
| 607 | */ |
| 608 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG |
| 609 | static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep) |
| 610 | { |
| 611 | unsigned long old; |
| 612 | old = pte_update(ptep, _PAGE_ACCESSED, 0); |
| 613 | #if _PAGE_HASHPTE != 0 |
| 614 | if (old & _PAGE_HASHPTE) { |
| 615 | unsigned long ptephys = __pa(ptep) & PAGE_MASK; |
| 616 | flush_hash_pages(context, addr, ptephys, 1); |
| 617 | } |
| 618 | #endif |
| 619 | return (old & _PAGE_ACCESSED) != 0; |
| 620 | } |
| 621 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ |
| 622 | __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep) |
| 623 | |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 624 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR |
| 625 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, |
| 626 | pte_t *ptep) |
| 627 | { |
| 628 | return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0)); |
| 629 | } |
| 630 | |
| 631 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
| 632 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, |
| 633 | pte_t *ptep) |
| 634 | { |
| 635 | pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0); |
| 636 | } |
| 637 | |
| 638 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS |
| 639 | static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) |
| 640 | { |
| 641 | unsigned long bits = pte_val(entry) & |
| 642 | (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW); |
| 643 | pte_update(ptep, 0, bits); |
| 644 | } |
| 645 | |
| 646 | #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \ |
Benjamin Herrenschmidt | 8dab524 | 2007-06-16 10:16:12 -0700 | [diff] [blame] | 647 | ({ \ |
| 648 | int __changed = !pte_same(*(__ptep), __entry); \ |
| 649 | if (__changed) { \ |
| 650 | __ptep_set_access_flags(__ptep, __entry, __dirty); \ |
| 651 | flush_tlb_page_nohash(__vma, __address); \ |
| 652 | } \ |
| 653 | __changed; \ |
| 654 | }) |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 655 | |
| 656 | /* |
| 657 | * Macro to mark a page protection value as "uncacheable". |
| 658 | */ |
| 659 | #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED)) |
| 660 | |
| 661 | struct file; |
| 662 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, |
| 663 | unsigned long size, pgprot_t vma_prot); |
| 664 | #define __HAVE_PHYS_MEM_ACCESS_PROT |
| 665 | |
| 666 | #define __HAVE_ARCH_PTE_SAME |
| 667 | #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0) |
| 668 | |
| 669 | /* |
| 670 | * Note that on Book E processors, the pmd contains the kernel virtual |
| 671 | * (lowmem) address of the pte page. The physical address is less useful |
| 672 | * because everything runs with translation enabled (even the TLB miss |
| 673 | * handler). On everything else the pmd contains the physical address |
| 674 | * of the pte page. -- paulus |
| 675 | */ |
| 676 | #ifndef CONFIG_BOOKE |
| 677 | #define pmd_page_vaddr(pmd) \ |
| 678 | ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) |
| 679 | #define pmd_page(pmd) \ |
| 680 | (mem_map + (pmd_val(pmd) >> PAGE_SHIFT)) |
| 681 | #else |
| 682 | #define pmd_page_vaddr(pmd) \ |
| 683 | ((unsigned long) (pmd_val(pmd) & PAGE_MASK)) |
| 684 | #define pmd_page(pmd) \ |
| 685 | (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT)) |
| 686 | #endif |
| 687 | |
| 688 | /* to find an entry in a kernel page-table-directory */ |
| 689 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) |
| 690 | |
| 691 | /* to find an entry in a page-table-directory */ |
| 692 | #define pgd_index(address) ((address) >> PGDIR_SHIFT) |
| 693 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) |
| 694 | |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 695 | /* Find an entry in the third-level page table.. */ |
| 696 | #define pte_index(address) \ |
| 697 | (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) |
| 698 | #define pte_offset_kernel(dir, addr) \ |
| 699 | ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr)) |
| 700 | #define pte_offset_map(dir, addr) \ |
| 701 | ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr)) |
| 702 | #define pte_offset_map_nested(dir, addr) \ |
| 703 | ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr)) |
| 704 | |
| 705 | #define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0) |
| 706 | #define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1) |
| 707 | |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 708 | /* |
| 709 | * Encode and decode a swap entry. |
| 710 | * Note that the bits we use in a PTE for representing a swap entry |
| 711 | * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the |
| 712 | *_PAGE_HASHPTE bit (if used). -- paulus |
| 713 | */ |
| 714 | #define __swp_type(entry) ((entry).val & 0x1f) |
| 715 | #define __swp_offset(entry) ((entry).val >> 5) |
| 716 | #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) }) |
| 717 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 }) |
| 718 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) |
| 719 | |
| 720 | /* Encode and decode a nonlinear file mapping entry */ |
| 721 | #define PTE_FILE_MAX_BITS 29 |
| 722 | #define pte_to_pgoff(pte) (pte_val(pte) >> 3) |
| 723 | #define pgoff_to_pte(off) ((pte_t) { ((off) << 3) | _PAGE_FILE }) |
| 724 | |
David Gibson | f88df14 | 2007-04-30 16:30:56 +1000 | [diff] [blame] | 725 | /* |
| 726 | * No page table caches to initialise |
| 727 | */ |
| 728 | #define pgtable_cache_init() do { } while (0) |
| 729 | |
| 730 | extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep, |
| 731 | pmd_t **pmdp); |
| 732 | |
| 733 | #endif /* !__ASSEMBLY__ */ |
| 734 | |
| 735 | #endif /* _ASM_POWERPC_PGTABLE_PPC32_H */ |