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Kukjin Kim2bc02c02011-08-24 17:25:09 +09001/*
Kukjin Kima8550392012-03-09 14:19:10 -08002 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
Kukjin Kim2bc02c02011-08-24 17:25:09 +09003 * http://www.samsung.com
4 *
5 * EXYNOS4210 - Clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/err.h>
14#include <linux/clk.h>
15#include <linux/io.h>
Jonghwan Choiacd35612011-08-24 21:52:45 +090016#include <linux/syscore_ops.h>
Kukjin Kim2bc02c02011-08-24 17:25:09 +090017
18#include <plat/cpu-freq.h>
19#include <plat/clock.h>
20#include <plat/cpu.h>
21#include <plat/pll.h>
22#include <plat/s5p-clock.h>
23#include <plat/clock-clksrc.h>
Jonghwan Choiacd35612011-08-24 21:52:45 +090024#include <plat/pm.h>
Kukjin Kim2bc02c02011-08-24 17:25:09 +090025
26#include <mach/hardware.h>
27#include <mach/map.h>
28#include <mach/regs-clock.h>
KyongHo Chobca10b92012-04-04 09:23:02 -070029#include <mach/sysmmu.h>
Kukjin Kim2bc02c02011-08-24 17:25:09 +090030
Kukjin Kimcc511b82011-12-27 08:18:36 +010031#include "common.h"
Kukjin Kimce9c00e2012-03-09 13:51:24 -080032#include "clock-exynos4.h"
Kukjin Kimcc511b82011-12-27 08:18:36 +010033
Kukjin Kim7cdf04d2012-01-27 14:56:17 +090034#ifdef CONFIG_PM_SLEEP
Jonghwan Choiacd35612011-08-24 21:52:45 +090035static struct sleep_save exynos4210_clock_save[] = {
Kukjin Kima8550392012-03-09 14:19:10 -080036 SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
37 SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
38 SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
39 SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
40 SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
41 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
42 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
43 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
Jonghwan Choiacd35612011-08-24 21:52:45 +090044};
Kukjin Kim7cdf04d2012-01-27 14:56:17 +090045#endif
Jonghwan Choiacd35612011-08-24 21:52:45 +090046
Kukjin Kim2bc02c02011-08-24 17:25:09 +090047static struct clksrc_clk *sysclks[] = {
48 /* nothing here yet */
49};
50
Sachin Kamat8bf56462012-07-17 07:52:03 +090051static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
52 .clk = {
53 .name = "mout_g2d0",
54 },
55 .sources = &exynos4_clkset_mout_g2d0,
56 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
57};
58
59static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
60 .clk = {
61 .name = "mout_g2d1",
62 },
63 .sources = &exynos4_clkset_mout_g2d1,
64 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
65};
66
67static struct clk *exynos4210_clkset_mout_g2d_list[] = {
68 [0] = &exynos4210_clk_mout_g2d0.clk,
69 [1] = &exynos4210_clk_mout_g2d1.clk,
70};
71
72static struct clksrc_sources exynos4210_clkset_mout_g2d = {
73 .sources = exynos4210_clkset_mout_g2d_list,
74 .nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
75};
76
Kukjin Kim2bc02c02011-08-24 17:25:09 +090077static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
78{
Kukjin Kima8550392012-03-09 14:19:10 -080079 return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
Kukjin Kim2bc02c02011-08-24 17:25:09 +090080}
81
82static struct clksrc_clk clksrcs[] = {
83 {
84 .clk = {
85 .name = "sclk_sata",
86 .id = -1,
87 .enable = exynos4_clksrc_mask_fsys_ctrl,
88 .ctrlbit = (1 << 24),
89 },
Kukjin Kima8550392012-03-09 14:19:10 -080090 .sources = &exynos4_clkset_mout_corebus,
91 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
92 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
Kukjin Kim2bc02c02011-08-24 17:25:09 +090093 }, {
94 .clk = {
95 .name = "sclk_fimd",
96 .devname = "exynos4-fb.1",
97 .enable = exynos4_clksrc_mask_lcd1_ctrl,
98 .ctrlbit = (1 << 0),
99 },
Kukjin Kima8550392012-03-09 14:19:10 -0800100 .sources = &exynos4_clkset_group,
101 .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
102 .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
Sachin Kamat8bf56462012-07-17 07:52:03 +0900103 }, {
104 .clk = {
105 .name = "sclk_fimg2d",
106 },
107 .sources = &exynos4210_clkset_mout_g2d,
108 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
109 .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
Kukjin Kim2bc02c02011-08-24 17:25:09 +0900110 },
111};
112
113static struct clk init_clocks_off[] = {
114 {
115 .name = "sataphy",
116 .id = -1,
Kukjin Kima8550392012-03-09 14:19:10 -0800117 .parent = &exynos4_clk_aclk_133.clk,
Kukjin Kim2bc02c02011-08-24 17:25:09 +0900118 .enable = exynos4_clk_ip_fsys_ctrl,
119 .ctrlbit = (1 << 3),
120 }, {
121 .name = "sata",
122 .id = -1,
Kukjin Kima8550392012-03-09 14:19:10 -0800123 .parent = &exynos4_clk_aclk_133.clk,
Kukjin Kim2bc02c02011-08-24 17:25:09 +0900124 .enable = exynos4_clk_ip_fsys_ctrl,
125 .ctrlbit = (1 << 10),
126 }, {
127 .name = "fimd",
128 .devname = "exynos4-fb.1",
129 .enable = exynos4_clk_ip_lcd1_ctrl,
130 .ctrlbit = (1 << 0),
KyongHo Chobca10b92012-04-04 09:23:02 -0700131 }, {
132 .name = SYSMMU_CLOCK_NAME,
133 .devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
134 .enable = exynos4_clk_ip_image_ctrl,
135 .ctrlbit = (1 << 3),
136 }, {
137 .name = SYSMMU_CLOCK_NAME,
138 .devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11),
139 .enable = exynos4_clk_ip_lcd1_ctrl,
140 .ctrlbit = (1 << 4),
Sachin Kamat8bf56462012-07-17 07:52:03 +0900141 }, {
142 .name = "fimg2d",
143 .enable = exynos4_clk_ip_image_ctrl,
144 .ctrlbit = (1 << 0),
Kukjin Kim2bc02c02011-08-24 17:25:09 +0900145 },
146};
147
Jonghwan Choiacd35612011-08-24 21:52:45 +0900148#ifdef CONFIG_PM_SLEEP
149static int exynos4210_clock_suspend(void)
150{
151 s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
152
153 return 0;
154}
155
156static void exynos4210_clock_resume(void)
157{
158 s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
159}
160
161#else
162#define exynos4210_clock_suspend NULL
163#define exynos4210_clock_resume NULL
164#endif
165
Kukjin Kime745e062012-01-21 10:47:14 +0900166static struct syscore_ops exynos4210_clock_syscore_ops = {
Jonghwan Choiacd35612011-08-24 21:52:45 +0900167 .suspend = exynos4210_clock_suspend,
168 .resume = exynos4210_clock_resume,
169};
170
Kukjin Kim2bc02c02011-08-24 17:25:09 +0900171void __init exynos4210_register_clocks(void)
172{
173 int ptr;
174
Kukjin Kima8550392012-03-09 14:19:10 -0800175 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
176 exynos4_clk_mout_mpll.reg_src.shift = 8;
177 exynos4_clk_mout_mpll.reg_src.size = 1;
Kukjin Kim2bc02c02011-08-24 17:25:09 +0900178
179 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
180 s3c_register_clksrc(sysclks[ptr], 1);
181
182 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
183
184 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
185 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
Jonghwan Choiacd35612011-08-24 21:52:45 +0900186
187 register_syscore_ops(&exynos4210_clock_syscore_ops);
Kukjin Kim2bc02c02011-08-24 17:25:09 +0900188}