Sylwester Nawrocki | 02399e3 | 2013-03-26 08:20:30 -0300 | [diff] [blame] | 1 | Samsung S5P/EXYNOS SoC series MIPI CSI-2 receiver (MIPI CSIS) |
| 2 | ------------------------------------------------------------- |
| 3 | |
| 4 | Required properties: |
| 5 | |
| 6 | - compatible : "samsung,s5pv210-csis" for S5PV210 (S5PC110), |
| 7 | "samsung,exynos4210-csis" for Exynos4210 (S5PC210), |
Sylwester Nawrocki | f7354e6 | 2013-05-31 10:38:23 -0300 | [diff] [blame] | 8 | "samsung,exynos4212-csis" for Exynos4212/Exynos4412, |
| 9 | "samsung,exynos5250-csis" for Exynos5250; |
Sylwester Nawrocki | 02399e3 | 2013-03-26 08:20:30 -0300 | [diff] [blame] | 10 | - reg : offset and length of the register set for the device; |
| 11 | - interrupts : should contain MIPI CSIS interrupt; the format of the |
| 12 | interrupt specifier depends on the interrupt controller; |
| 13 | - bus-width : maximum number of data lanes supported (SoC specific); |
| 14 | - vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V); |
| 15 | - vddcore-supply : MIPI CSIS Core voltage supply (e.g. 1.1V); |
| 16 | - clocks : list of clock specifiers, corresponding to entries in |
| 17 | clock-names property; |
| 18 | - clock-names : must contain "csis", "sclk_csis" entries, matching entries |
| 19 | in the clocks property. |
| 20 | |
| 21 | Optional properties: |
| 22 | |
| 23 | - clock-frequency : The IP's main (system bus) clock frequency in Hz, default |
| 24 | value when this property is not specified is 166 MHz; |
| 25 | - samsung,csis-wclk : CSI-2 wrapper clock selection. If this property is present |
| 26 | external clock from CMU will be used, or the bus clock if |
| 27 | if it's not specified. |
| 28 | |
| 29 | The device node should contain one 'port' child node with one child 'endpoint' |
| 30 | node, according to the bindings defined in Documentation/devicetree/bindings/ |
| 31 | media/video-interfaces.txt. The following are properties specific to those nodes. |
| 32 | |
| 33 | port node |
| 34 | --------- |
| 35 | |
| 36 | - reg : (required) must be 3 for camera C input (CSIS0) or 4 for |
| 37 | camera D input (CSIS1); |
| 38 | |
| 39 | endpoint node |
| 40 | ------------- |
| 41 | |
| 42 | - data-lanes : (required) an array specifying active physical MIPI-CSI2 |
| 43 | data input lanes and their mapping to logical lanes; the |
| 44 | array's content is unused, only its length is meaningful; |
| 45 | |
| 46 | - samsung,csis-hs-settle : (optional) differential receiver (HS-RX) settle time; |
| 47 | |
| 48 | |
| 49 | Example: |
| 50 | |
| 51 | reg0: regulator@0 { |
| 52 | }; |
| 53 | |
| 54 | reg1: regulator@1 { |
| 55 | }; |
| 56 | |
| 57 | /* SoC properties */ |
| 58 | |
| 59 | csis_0: csis@11880000 { |
| 60 | compatible = "samsung,exynos4210-csis"; |
| 61 | reg = <0x11880000 0x1000>; |
| 62 | interrupts = <0 78 0>; |
| 63 | #address-cells = <1>; |
| 64 | #size-cells = <0>; |
| 65 | }; |
| 66 | |
| 67 | /* Board properties */ |
| 68 | |
| 69 | csis_0: csis@11880000 { |
| 70 | clock-frequency = <166000000>; |
| 71 | vddio-supply = <®0>; |
| 72 | vddcore-supply = <®1>; |
| 73 | port { |
| 74 | reg = <3>; /* 3 - CSIS0, 4 - CSIS1 */ |
| 75 | csis0_ep: endpoint { |
| 76 | remote-endpoint = <...>; |
| 77 | data-lanes = <1>, <2>; |
| 78 | samsung,csis-hs-settle = <12>; |
| 79 | }; |
| 80 | }; |
| 81 | }; |